[PATCH] D152714: [AArch64][Optimization]Solving the FCCMP issue

[Priyanshi Agarwal via Phabricator via llvm-commits]

ipriyanshi1708 updated this revision to Diff 537097.
ipriyanshi1708 marked 2 inline comments as done.
ipriyanshi1708 added a comment.

Updated the code


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152714/new/

https://reviews.llvm.org/D152714

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/andcompare.ll


Index: llvm/test/CodeGen/AArch64/andcompare.ll
===================================================================
--- llvm/test/CodeGen/AArch64/andcompare.ll
+++ llvm/test/CodeGen/AArch64/andcompare.ll
@@ -2522,6 +2522,29 @@
   ret i32 %r
 }
 
+define i1 @and_fcmp(float %0, float %1) {
+; SDISEL-LABEL: and_fcmp:
+; SDISEL:       // %bb.0:
+; SDISEL-NEXT:    fcmp s1, s1
+; SDISEL-NEXT:    fccmp s0, s0, #0, vs
+; SDISEL-NEXT:    cset w0, vs
+; SDISEL-NEXT:    ret
+;
+; GISEL-LABEL: and_fcmp:
+; GISEL:       // %bb.0:
+; GISEL-NEXT:    fcmp s0, #0.0
+; GISEL-NEXT:    cset w8, vs
+; GISEL-NEXT:    fcmp s1, #0.0
+; GISEL-NEXT:    cset w9, vs
+; GISEL-NEXT:    and w0, w8, w9
+; GISEL-NEXT:    ret
+
+  %3 = fcmp uno float %0, 0.000000e+00
+  %4 = fcmp uno float %1, 0.000000e+00
+  %5 = and i1 %3, %4
+  ret i1 %5
+}
+
 
 ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
 ; CHECK: {{.*}}
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16381,6 +16381,36 @@
   return SDValue();
 }
 
+static SDValue performANDSETCCCombine(SDNode *N,
+                                      TargetLowering::DAGCombinerInfo &DCI) {
+  SDValue SetCC = N->getOperand(0);
+  EVT VT = N->getValueType(0);
+  SelectionDAG &DAG = DCI.DAG;
+
+  if (SetCC.getOpcode() == ISD::SETCC &&
+      SetCC.getOperand(0).getValueType() == MVT::f32) {
+
+    SDValue Cmp;
+    AArch64CC::CondCode AArch64CC;
+
+    if (!DCI.isBeforeLegalize() &&
+        (Cmp = emitConjunction(DAG, SDValue(N, 0), AArch64CC))) {
+
+      unsigned ZeroReg = VT.getSizeInBits() == 32 ? AArch64::WZR : AArch64::XZR;
+      AArch64CC::CondCode InvertedCC =
+          AArch64CC::getInvertedCondCode(AArch64CC);
+
+      SDLoc DL(N);
+      // Transform and(fcmp(a, b), fcmp(c, d)) into fccmp(fcmp(a, b), c, d)
+      return DAG.getNode(AArch64ISD::CSINC, DL, VT,
+                         DAG.getRegister(ZeroReg, VT),
+                         DAG.getRegister(ZeroReg, VT),
+                         DAG.getConstant(InvertedCC, DL, MVT::i32), Cmp);
+    }
+  }
+  return SDValue();
+}
+
 static SDValue performANDCombine(SDNode *N,
                                  TargetLowering::DAGCombinerInfo &DCI) {
   SelectionDAG &DAG = DCI.DAG;
@@ -16391,6 +16421,9 @@
   if (SDValue R = performANDORCSELCombine(N, DAG))
     return R;
 
+  if (SDValue R = performANDSETCCCombine(N,DCI))
+    return R;
+
   if (!DAG.getTargetLoweringInfo().isTypeLegal(VT))
     return SDValue();
 


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