[PATCH] D154136: [RISCV] Add SEW to RISCVInversePseudoTable
Min-Yih Hsu via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jun 29 21:52:40 PDT 2023
myhsu added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVInstrFormats.td:222
+ // SEW = 0 is used to denote that the RVInst is not SEW specific.
+ // TODO: make field smaller by using bit<2> where 0b00 = E8, 0b01=E16,
+ // 0b10=E32, 0b11=E64.
----------------
craig.topper wrote:
> nit: bits<2> not bit<2>
making the field smaller: using something similar to `MxSet` might help. For instance:
```
let SEW = MxSet2<eew>.m in ...
```
Repository:
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https://reviews.llvm.org/D154136/new/
https://reviews.llvm.org/D154136
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