[PATCH] D153669: [RISCV] Add missing Read classe to some compressed instructions.

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc added a comment.

Typo in title: `classe`->`classes`.
IIUC, the change has no influence to scheduler but static machine code analyser like `llvm-mca`, since there is no C instructions when doing scheduling.



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoC.td:554
 def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
-                      "c.jr", "$rs1">, Sched<[WriteJmpReg]> {
+                      "c.jr", "$rs1">, Sched<[WriteJmpReg, ReadJalr]> {
   let isBarrier = 1;
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Comment not aim for this patch:
Do we really need a SchedWrite `WriteJmpReg`? It's only used in C instructions and it won't influence scheduler actually.
I think it can be removed and replaced by `WriteJalr`.


Repository:
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  https://reviews.llvm.org/D153669/new/

https://reviews.llvm.org/D153669