[PATCH] D153669: [RISCV] Add missing Read classe to some compressed instructions.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: michaelmaitland, jrtc27, asb, wangpc, monkchiang.
Herald added subscribers: jobnoorman, luke, VincentWu, vkmr, frasercrmck, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, gbedwell, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya, arichardson.
Herald added a reviewer: andreadb.
Herald added a project: All.
craig.topper requested review of this revision.
Herald added subscribers: eopXD, MaskRay.
Herald added a project: LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153669

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoC.td
  llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass-c.s


Index: llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass-c.s
===================================================================
--- llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass-c.s
+++ llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass-c.s
@@ -25,12 +25,12 @@
 
 # CHECK:      Iterations:        1
 # CHECK-NEXT: Instructions:      18
-# CHECK-NEXT: Total Cycles:      24
+# CHECK-NEXT: Total Cycles:      20
 # CHECK-NEXT: Total uOps:        18
 
 # CHECK:      Dispatch Width:    2
-# CHECK-NEXT: uOps Per Cycle:    0.75
-# CHECK-NEXT: IPC:               0.75
+# CHECK-NEXT: uOps Per Cycle:    0.90
+# CHECK-NEXT: IPC:               0.90
 # CHECK-NEXT: Block RThroughput: 9.0
 
 # CHECK:      Instruction Info:
@@ -98,26 +98,26 @@
 
 # CHECK:      Timeline view:
 # CHECK-NEXT:                     0123456789
-# CHECK-NEXT: Index     0123456789          0123
+# CHECK-NEXT: Index     0123456789
 
-# CHECK:      [0,0]     DeeE .    .    .    .  .   lui	a0, 1
-# CHECK-NEXT: [0,1]     .DeeE.    .    .    .  .   add	a0, a0, a0
-# CHECK-NEXT: [0,2]     . DeeE    .    .    .  .   addi	a0, a0, 1
-# CHECK-NEXT: [0,3]     .  DeeE   .    .    .  .   addw	a0, a0, a0
-# CHECK-NEXT: [0,4]     .   DeeE  .    .    .  .   addiw	a0, a0, 1
-# CHECK-NEXT: [0,5]     .    DeeE .    .    .  .   sub	a0, a0, a0
-# CHECK-NEXT: [0,6]     .    .DeeE.    .    .  .   subw	a0, a0, a0
-# CHECK-NEXT: [0,7]     .    . DeeE    .    .  .   and	a0, a0, a0
-# CHECK-NEXT: [0,8]     .    .  DeeE   .    .  .   andi	a0, a0, 1
-# CHECK-NEXT: [0,9]     .    .   DeeE  .    .  .   or	a0, a0, a0
-# CHECK-NEXT: [0,10]    .    .    DeeE .    .  .   xor	a0, a0, a0
-# CHECK-NEXT: [0,11]    .    .    .DeeE.    .  .   slli	a0, a0, 1
-# CHECK-NEXT: [0,12]    .    .    . DeeE    .  .   srli	a0, a0, 1
-# CHECK-NEXT: [0,13]    .    .    .  DeeE   .  .   srai	a0, a0, 1
-# CHECK-NEXT: [0,14]    .    .    .   DeeE  .  .   add	a0, a0, a0
-# CHECK-NEXT: [0,15]    .    .    .    . DeeE  .   beqz	a0, .Ltmp0
-# CHECK-NEXT: [0,16]    .    .    .    . DeeE  .   add	a0, a0, a0
-# CHECK-NEXT: [0,17]    .    .    .    .    DeeE   bnez	a0, .Ltmp1
+# CHECK:      [0,0]     DeeE .    .    .   .   lui	a0, 1
+# CHECK-NEXT: [0,1]     .DeeE.    .    .   .   add	a0, a0, a0
+# CHECK-NEXT: [0,2]     . DeeE    .    .   .   addi	a0, a0, 1
+# CHECK-NEXT: [0,3]     .  DeeE   .    .   .   addw	a0, a0, a0
+# CHECK-NEXT: [0,4]     .   DeeE  .    .   .   addiw	a0, a0, 1
+# CHECK-NEXT: [0,5]     .    DeeE .    .   .   sub	a0, a0, a0
+# CHECK-NEXT: [0,6]     .    .DeeE.    .   .   subw	a0, a0, a0
+# CHECK-NEXT: [0,7]     .    . DeeE    .   .   and	a0, a0, a0
+# CHECK-NEXT: [0,8]     .    .  DeeE   .   .   andi	a0, a0, 1
+# CHECK-NEXT: [0,9]     .    .   DeeE  .   .   or	a0, a0, a0
+# CHECK-NEXT: [0,10]    .    .    DeeE .   .   xor	a0, a0, a0
+# CHECK-NEXT: [0,11]    .    .    .DeeE.   .   slli	a0, a0, 1
+# CHECK-NEXT: [0,12]    .    .    . DeeE   .   srli	a0, a0, 1
+# CHECK-NEXT: [0,13]    .    .    .  DeeE  .   srai	a0, a0, 1
+# CHECK-NEXT: [0,14]    .    .    .   DeeE .   add	a0, a0, a0
+# CHECK-NEXT: [0,15]    .    .    .    DeeE.   beqz	a0, .Ltmp0
+# CHECK-NEXT: [0,16]    .    .    .    DeeE.   add	a0, a0, a0
+# CHECK-NEXT: [0,17]    .    .    .    .DeeE   bnez	a0, .Ltmp1
 
 # CHECK:      Average Wait times (based on the timeline view):
 # CHECK-NEXT: [0]: Executions
Index: llvm/lib/Target/RISCV/RISCVInstrInfoC.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoC.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoC.td
@@ -509,8 +509,8 @@
   let isBarrier=1;
 }
 
-def C_BEQZ : Bcz<0b110, "c.beqz", GPRC>, Sched<[WriteJmp]>;
-def C_BNEZ : Bcz<0b111, "c.bnez", GPRC>, Sched<[WriteJmp]>;
+def C_BEQZ : Bcz<0b110, "c.beqz", GPRC>, Sched<[WriteJmp, ReadJmp]>;
+def C_BNEZ : Bcz<0b111, "c.bnez", GPRC>, Sched<[WriteJmp, ReadJmp]>;
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_SLLI : RVInst16CI<0b000, 0b10, (outs GPRNoX0:$rd_wb),
@@ -551,7 +551,7 @@
 
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 def C_JR : RVInst16CR<0b1000, 0b10, (outs), (ins GPRNoX0:$rs1),
-                      "c.jr", "$rs1">, Sched<[WriteJmpReg]> {
+                      "c.jr", "$rs1">, Sched<[WriteJmpReg, ReadJalr]> {
   let isBarrier = 1;
   let isTerminator = 1;
   let rs2 = 0;


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