[llvm] 78c1985 - [NFC] Autogenerate CodeGen/ARM/machine-cse-cmp.ll
Amaury Séchet via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 24 17:45:44 PDT 2023
Author: Amaury Séchet
Date: 2023-06-25T00:44:30Z
New Revision: 78c1985f9985fcf1a3be45e949497c2577dd806a
URL: https://github.com/llvm/llvm-project/commit/78c1985f9985fcf1a3be45e949497c2577dd806a
DIFF: https://github.com/llvm/llvm-project/commit/78c1985f9985fcf1a3be45e949497c2577dd806a.diff
LOG: [NFC] Autogenerate CodeGen/ARM/machine-cse-cmp.ll
Added:
Modified:
llvm/test/CodeGen/ARM/machine-cse-cmp.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/ARM/machine-cse-cmp.ll b/llvm/test/CodeGen/ARM/machine-cse-cmp.ll
index 36899d6baa7c0..483932ccbd7e1 100644
--- a/llvm/test/CodeGen/ARM/machine-cse-cmp.ll
+++ b/llvm/test/CodeGen/ARM/machine-cse-cmp.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
;rdar://8003725
@@ -7,12 +8,14 @@ declare void @llvm.trap()
@G2 = external global i32
define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) {
-entry:
; CHECK-LABEL: f1:
-; CHECK: cmp
-; CHECK: moveq
-; CHECK-NOT: cmp
-; CHECK: mov{{eq|ne}}
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: moveq r3, r2
+; CHECK-NEXT: movne r1, r2
+; CHECK-NEXT: add r0, r1, r3
+; CHECK-NEXT: bx lr
+entry:
%tmp1 = icmp eq i32 %cond1, 0
%tmp2 = select i1 %tmp1, i32 %x1, i32 %x2
%tmp3 = select i1 %tmp1, i32 %x2, i32 %x3
@@ -26,12 +29,27 @@ entry:
; CSE of cmp across BB boundary
; rdar://10660865
define void @f2() nounwind ssp {
-entry:
; CHECK-LABEL: f2:
-; CHECK: cmp
-; CHECK: bxlt
-; CHECK-NOT: cmp
-; CHECK: movle
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: push {lr}
+; CHECK-NEXT: movw r0, :lower16:(L_foo$non_lazy_ptr-(LPC1_0+8))
+; CHECK-NEXT: movt r0, :upper16:(L_foo$non_lazy_ptr-(LPC1_0+8))
+; CHECK-NEXT: LPC1_0:
+; CHECK-NEXT: ldr r0, [pc, r0]
+; CHECK-NEXT: ldr r2, [r0]
+; CHECK-NEXT: cmp r2, #1
+; CHECK-NEXT: poplt {lr}
+; CHECK-NEXT: bxlt lr
+; CHECK-NEXT: LBB1_1: @ %for.body.lr.ph
+; CHECK-NEXT: movw r0, :lower16:(L_bar$non_lazy_ptr-(LPC1_1+8))
+; CHECK-NEXT: movle r2, #1
+; CHECK-NEXT: movt r0, :upper16:(L_bar$non_lazy_ptr-(LPC1_1+8))
+; CHECK-NEXT: mov r1, #0
+; CHECK-NEXT: LPC1_1:
+; CHECK-NEXT: ldr r0, [pc, r0]
+; CHECK-NEXT: bl _memset
+; CHECK-NEXT: trap
+entry:
%0 = load i32, ptr @foo, align 4
%cmp28 = icmp sgt i32 %0, 0
br i1 %cmp28, label %for.body.lr.ph, label %for.cond1.preheader
@@ -51,11 +69,22 @@ declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
; rdar://12462006
define ptr @f3(ptr %base, ptr nocapture %offset, i32 %size) nounwind {
-entry:
; CHECK-LABEL: f3:
-; CHECK-NOT: sub
-; CHECK: cmp
-; CHECK: blt
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: ldr r3, [r1]
+; CHECK-NEXT: mov r9, #0
+; CHECK-NEXT: cmp r3, r2
+; CHECK-NEXT: blt LBB2_2
+; CHECK-NEXT: @ %bb.1: @ %if.end
+; CHECK-NEXT: sub r3, r3, r2
+; CHECK-NEXT: add r9, r0, r3
+; CHECK-NEXT: sub r2, r2, r3
+; CHECK-NEXT: add r2, r3, r2
+; CHECK-NEXT: str r2, [r1]
+; CHECK-NEXT: LBB2_2: @ %return
+; CHECK-NEXT: mov r0, r9
+; CHECK-NEXT: bx lr
+entry:
%0 = load i32, ptr %offset, align 4
%cmp = icmp slt i32 %0, %size
%s = sub nsw i32 %0, %size
@@ -67,11 +96,6 @@ if.end:
%sub = sub nsw i32 %0, %size2
%s2 = sub nsw i32 %s, %size
%s3 = sub nsw i32 %sub, %s2
-; CHECK: sub [[R1:r[0-9]+]], [[R2:r[0-9]+]], r2
-; CHECK: sub [[R3:r[0-9]+]], r2, [[R1]]
-; CHECK: add [[R4:r[0-9]+]], [[R1]], [[R3]]
-; CHECK-NOT: sub
-; CHECK: str
store i32 %s3, ptr %offset, align 4
%add.ptr = getelementptr inbounds i8, ptr %base, i32 %sub
br label %return
@@ -83,15 +107,23 @@ ret ptr %retval.0
; The cmp of %val should not be hoisted above the preceding conditional branch
define void @f4(ptr %ptr1, ptr %ptr2, i64 %val) {
-entry:
; CHECK-LABEL: f4:
-; CHECK: cmp
-; CHECK: movne
-; CHECK: strne
-; CHECK: orrs
-; CHECK-NOT: subs
-; CHECK-NOT: sbcs
-; CHECK: beq
+; CHECK: @ %bb.0: @ %entry
+; CHECK-NEXT: cmp r0, #0
+; CHECK-NEXT: movne r9, #0
+; CHECK-NEXT: strne r9, [r0]
+; CHECK-NEXT: orrs r0, r2, r3
+; CHECK-NEXT: beq LBB3_2
+; CHECK-NEXT: @ %bb.1: @ %if.end
+; CHECK-NEXT: subs r0, r2, #10
+; CHECK-NEXT: sbcs r0, r3, #0
+; CHECK-NEXT: bxlt lr
+; CHECK-NEXT: LBB3_2: @ %if.end3
+; CHECK-NEXT: subs r0, r2, #10
+; CHECK-NEXT: sbc r3, r3, #0
+; CHECK-NEXT: stm r1, {r0, r3}
+; CHECK-NEXT: bx lr
+entry:
%tobool.not = icmp eq ptr %ptr1, null
br i1 %tobool.not, label %if.end, label %if.then
@@ -100,17 +132,12 @@ if.then:
br label %if.end
if.end:
-; CHECK: subs
-; CHECK: sbcs
-; CHECK: bxlt lr
%tobool1 = icmp ne i64 %val, 0
%cmp = icmp slt i64 %val, 10
%or.cond = and i1 %tobool1, %cmp
br i1 %or.cond, label %cleanup, label %if.end3
if.end3:
-; CHECK: subs
-; CHECK: sbc
%sub = add nsw i64 %val, -10
store i64 %sub, ptr %ptr2, align 8
br label %cleanup
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