[llvm] fb60dda - [GlobalIsel][X86] selectDivRem - fix typo in 64-bit AH handling code

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-06-18T17:37:17+01:00
New Revision: fb60dda1893eb9d0420de25b84fb023dc8424aeb

URL: https://github.com/llvm/llvm-project/commit/fb60dda1893eb9d0420de25b84fb023dc8424aeb
DIFF: https://github.com/llvm/llvm-project/commit/fb60dda1893eb9d0420de25b84fb023dc8424aeb.diff

LOG: [GlobalIsel][X86] selectDivRem - fix typo in 64-bit AH handling code

This function was lifted from fast-isel, and still referred to the Instruction::SRem/URrem opcodes, instead of the G_SREM/G_UREM opcodes.

But it turns out these aren't necessary at all as only the G_SREM/G_UREM codepaths will use the AH register for DivRemResultReg anyhow.

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86InstructionSelector.cpp
    llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
    llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86InstructionSelector.cpp b/llvm/lib/Target/X86/X86InstructionSelector.cpp
index 404a8da53a442..c962c5204b04f 100644
--- a/llvm/lib/Target/X86/X86InstructionSelector.cpp
+++ b/llvm/lib/Target/X86/X86InstructionSelector.cpp
@@ -1728,9 +1728,7 @@ bool X86InstructionSelector::selectDivRem(MachineInstr &I,
   // won't generate explicit references to the GR8_NOREX registers. If
   // the allocator and/or the backend get enhanced to be more robust in
   // that regard, this can be, and should be, removed.
-  if ((I.getOpcode() == Instruction::SRem ||
-       I.getOpcode() == Instruction::URem) &&
-      OpEntry.DivRemResultReg == X86::AH && STI.is64Bit()) {
+  if (OpEntry.DivRemResultReg == X86::AH && STI.is64Bit()) {
     Register SourceSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
     Register ResultSuperReg = MRI.createVirtualRegister(&X86::GR16RegClass);
     BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), SourceSuperReg)

diff  --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
index 8b04f3dba51f8..0988883145bcd 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
@@ -77,8 +77,10 @@ body:             |
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit
     ; CHECK-NEXT: $ax = MOVSX16rr8 [[COPY1]]
     ; CHECK-NEXT: IDIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr8 = COPY $ah
-    ; CHECK-NEXT: $al = COPY [[COPY4]]
+    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY $ax
+    ; CHECK-NEXT: [[SHR16ri:%[0-9]+]]:gr16 = SHR16ri [[COPY4]], 8, implicit-def $eflags
+    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr8 = SUBREG_TO_REG 0, [[SHR16ri]], %subreg.sub_8bit
+    ; CHECK-NEXT: $al = COPY [[SUBREG_TO_REG]]
     ; CHECK-NEXT: RET 0, implicit $al
     %2:gpr(s32) = COPY $edi
     %0:gpr(s8) = G_TRUNC %2(s32)

diff  --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir
index e55f93e54f2ed..657cf49994973 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir
@@ -77,8 +77,10 @@ body:             |
     ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit
     ; CHECK-NEXT: $ax = MOVZX16rr8 [[COPY1]]
     ; CHECK-NEXT: DIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr8 = COPY $ah
-    ; CHECK-NEXT: $al = COPY [[COPY4]]
+    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY $ax
+    ; CHECK-NEXT: [[SHR16ri:%[0-9]+]]:gr16 = SHR16ri [[COPY4]], 8, implicit-def $eflags
+    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr8 = SUBREG_TO_REG 0, [[SHR16ri]], %subreg.sub_8bit
+    ; CHECK-NEXT: $al = COPY [[SUBREG_TO_REG]]
     ; CHECK-NEXT: RET 0, implicit $al
     %2:gpr(s32) = COPY $edi
     %0:gpr(s8) = G_TRUNC %2(s32)