[llvm] 46479ea - [GlobalIsel][X86] Regenerate srem/urem select test coverage
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 18 09:21:25 PDT 2023
Author: Simon Pilgrim
Date: 2023-06-18T17:06:32+01:00
New Revision: 46479ea785efe834bfc65b2dc53a70a1b8210319
URL: https://github.com/llvm/llvm-project/commit/46479ea785efe834bfc65b2dc53a70a1b8210319
DIFF: https://github.com/llvm/llvm-project/commit/46479ea785efe834bfc65b2dc53a70a1b8210319.diff
LOG: [GlobalIsel][X86] Regenerate srem/urem select test coverage
Added:
Modified:
llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
index a0551f1f59dcf..8b04f3dba51f8 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-srem.mir
@@ -70,15 +70,16 @@ body: |
; CHECK-LABEL: name: test_srem_i8
; CHECK: liveins: $edi, $esi
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
- ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
- ; CHECK: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit
- ; CHECK: $ax = MOVSX16rr8 [[COPY1]]
- ; CHECK: IDIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
- ; CHECK: [[COPY4:%[0-9]+]]:gr8 = COPY $ah
- ; CHECK: $al = COPY [[COPY4]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit
+ ; CHECK-NEXT: $ax = MOVSX16rr8 [[COPY1]]
+ ; CHECK-NEXT: IDIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr8 = COPY $ah
+ ; CHECK-NEXT: $al = COPY [[COPY4]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:gpr(s32) = COPY $edi
%0:gpr(s8) = G_TRUNC %2(s32)
%3:gpr(s32) = COPY $esi
@@ -131,16 +132,17 @@ body: |
; CHECK-LABEL: name: test_srem_i16
; CHECK: liveins: $edi, $esi
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
- ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
- ; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
- ; CHECK: $ax = COPY [[COPY1]]
- ; CHECK: CWD implicit-def $ax, implicit-def $dx, implicit $ax
- ; CHECK: IDIV16r [[COPY3]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
- ; CHECK: [[COPY4:%[0-9]+]]:gr16 = COPY $dx
- ; CHECK: $ax = COPY [[COPY4]]
- ; CHECK: RET 0, implicit $ax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
+ ; CHECK-NEXT: $ax = COPY [[COPY1]]
+ ; CHECK-NEXT: CWD implicit-def $ax, implicit-def $dx, implicit $ax
+ ; CHECK-NEXT: IDIV16r [[COPY3]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY $dx
+ ; CHECK-NEXT: $ax = COPY [[COPY4]]
+ ; CHECK-NEXT: RET 0, implicit $ax
%2:gpr(s32) = COPY $edi
%0:gpr(s16) = G_TRUNC %2(s32)
%3:gpr(s32) = COPY $esi
@@ -191,14 +193,15 @@ body: |
; CHECK-LABEL: name: test_srem_i32
; CHECK: liveins: $edi, $esi
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; CHECK: $eax = COPY [[COPY]]
- ; CHECK: CDQ implicit-def $eax, implicit-def $edx, implicit $eax
- ; CHECK: IDIV32r [[COPY1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
- ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $edx
- ; CHECK: $eax = COPY [[COPY2]]
- ; CHECK: RET 0, implicit $eax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK-NEXT: $eax = COPY [[COPY]]
+ ; CHECK-NEXT: CDQ implicit-def $eax, implicit-def $edx, implicit $eax
+ ; CHECK-NEXT: IDIV32r [[COPY1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $edx
+ ; CHECK-NEXT: $eax = COPY [[COPY2]]
+ ; CHECK-NEXT: RET 0, implicit $eax
%0:gpr(s32) = COPY $edi
%1:gpr(s32) = COPY $esi
%2:gpr(s32) = G_SREM %0, %1
@@ -247,14 +250,15 @@ body: |
; CHECK-LABEL: name: test_srem_i64
; CHECK: liveins: $rdi, $rsi
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK: $rax = COPY [[COPY]]
- ; CHECK: CQO implicit-def $rax, implicit-def $rdx, implicit $rax
- ; CHECK: IDIV64r [[COPY1]], implicit-def $rax, implicit-def $rdx, implicit-def $eflags, implicit $rax, implicit $rdx
- ; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
- ; CHECK: $rax = COPY [[COPY2]]
- ; CHECK: RET 0, implicit $rax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK-NEXT: $rax = COPY [[COPY]]
+ ; CHECK-NEXT: CQO implicit-def $rax, implicit-def $rdx, implicit $rax
+ ; CHECK-NEXT: IDIV64r [[COPY1]], implicit-def $rax, implicit-def $rdx, implicit-def $eflags, implicit $rax, implicit $rdx
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
+ ; CHECK-NEXT: $rax = COPY [[COPY2]]
+ ; CHECK-NEXT: RET 0, implicit $rax
%0:gpr(s64) = COPY $rdi
%1:gpr(s64) = COPY $rsi
%2:gpr(s64) = G_SREM %0, %1
diff --git a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir
index c25db2b6f0fe8..e55f93e54f2ed 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/x86_64-select-urem.mir
@@ -70,15 +70,16 @@ body: |
; CHECK-LABEL: name: test_urem_i8
; CHECK: liveins: $edi, $esi
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
- ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
- ; CHECK: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit
- ; CHECK: $ax = MOVZX16rr8 [[COPY1]]
- ; CHECK: DIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
- ; CHECK: [[COPY4:%[0-9]+]]:gr8 = COPY $ah
- ; CHECK: $al = COPY [[COPY4]]
- ; CHECK: RET 0, implicit $al
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr8 = COPY [[COPY2]].sub_8bit
+ ; CHECK-NEXT: $ax = MOVZX16rr8 [[COPY1]]
+ ; CHECK-NEXT: DIV8r [[COPY3]], implicit-def $al, implicit-def $ah, implicit-def $eflags, implicit $ax
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr8 = COPY $ah
+ ; CHECK-NEXT: $al = COPY [[COPY4]]
+ ; CHECK-NEXT: RET 0, implicit $al
%2:gpr(s32) = COPY $edi
%0:gpr(s8) = G_TRUNC %2(s32)
%3:gpr(s32) = COPY $esi
@@ -131,17 +132,18 @@ body: |
; CHECK-LABEL: name: test_urem_i16
; CHECK: liveins: $edi, $esi
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
- ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
- ; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
- ; CHECK: $ax = COPY [[COPY1]]
- ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
- ; CHECK: $dx = COPY [[MOV32r0_]].sub_16bit
- ; CHECK: DIV16r [[COPY3]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
- ; CHECK: [[COPY4:%[0-9]+]]:gr16 = COPY $dx
- ; CHECK: $ax = COPY [[COPY4]]
- ; CHECK: RET 0, implicit $ax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[COPY2]].sub_16bit
+ ; CHECK-NEXT: $ax = COPY [[COPY1]]
+ ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK-NEXT: $dx = COPY [[MOV32r0_]].sub_16bit
+ ; CHECK-NEXT: DIV16r [[COPY3]], implicit-def $ax, implicit-def $dx, implicit-def $eflags, implicit $ax, implicit $dx
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gr16 = COPY $dx
+ ; CHECK-NEXT: $ax = COPY [[COPY4]]
+ ; CHECK-NEXT: RET 0, implicit $ax
%2:gpr(s32) = COPY $edi
%0:gpr(s16) = G_TRUNC %2(s32)
%3:gpr(s32) = COPY $esi
@@ -192,15 +194,16 @@ body: |
; CHECK-LABEL: name: test_urem_i32
; CHECK: liveins: $edi, $esi
- ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
- ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
- ; CHECK: $eax = COPY [[COPY]]
- ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
- ; CHECK: $edx = COPY [[MOV32r0_]]
- ; CHECK: DIV32r [[COPY1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
- ; CHECK: [[COPY2:%[0-9]+]]:gr32 = COPY $edx
- ; CHECK: $eax = COPY [[COPY2]]
- ; CHECK: RET 0, implicit $eax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
+ ; CHECK-NEXT: $eax = COPY [[COPY]]
+ ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK-NEXT: $edx = COPY [[MOV32r0_]]
+ ; CHECK-NEXT: DIV32r [[COPY1]], implicit-def $eax, implicit-def $edx, implicit-def $eflags, implicit $eax, implicit $edx
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $edx
+ ; CHECK-NEXT: $eax = COPY [[COPY2]]
+ ; CHECK-NEXT: RET 0, implicit $eax
%0:gpr(s32) = COPY $edi
%1:gpr(s32) = COPY $esi
%2:gpr(s32) = G_UREM %0, %1
@@ -249,15 +252,16 @@ body: |
; CHECK-LABEL: name: test_urem_i64
; CHECK: liveins: $rdi, $rsi
- ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
- ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
- ; CHECK: $rax = COPY [[COPY]]
- ; CHECK: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
- ; CHECK: $rdx = SUBREG_TO_REG 0, [[MOV32r0_]], %subreg.sub_32bit
- ; CHECK: DIV64r [[COPY1]], implicit-def $rax, implicit-def $rdx, implicit-def $eflags, implicit $rax, implicit $rdx
- ; CHECK: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
- ; CHECK: $rax = COPY [[COPY2]]
- ; CHECK: RET 0, implicit $rax
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
+ ; CHECK-NEXT: $rax = COPY [[COPY]]
+ ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
+ ; CHECK-NEXT: $rdx = SUBREG_TO_REG 0, [[MOV32r0_]], %subreg.sub_32bit
+ ; CHECK-NEXT: DIV64r [[COPY1]], implicit-def $rax, implicit-def $rdx, implicit-def $eflags, implicit $rax, implicit $rdx
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
+ ; CHECK-NEXT: $rax = COPY [[COPY2]]
+ ; CHECK-NEXT: RET 0, implicit $rax
%0:gpr(s64) = COPY $rdi
%1:gpr(s64) = COPY $rsi
%2:gpr(s64) = G_UREM %0, %1
More information about the llvm-commits
mailing list