[llvm] 833438e - [Hexagon] Handle all compares of i1 and vNi1

Krzysztof Parzyszek via llvm-commits llvm-commits at lists.llvm.org
Sat Jun 17 16:39:23 PDT 2023


Author: Krzysztof Parzyszek
Date: 2023-06-17T16:31:21-07:00
New Revision: 833438eef0663d16d4224e25602749f50b661a17

URL: https://github.com/llvm/llvm-project/commit/833438eef0663d16d4224e25602749f50b661a17
DIFF: https://github.com/llvm/llvm-project/commit/833438eef0663d16d4224e25602749f50b661a17.diff

LOG: [Hexagon] Handle all compares of i1 and vNi1

Fixes https://github.com/llvm/llvm-project/issues/63363

Added: 
    llvm/test/CodeGen/Hexagon/isel/cmp-i1.ll
    llvm/test/CodeGen/Hexagon/isel/cmp-v2i1.ll
    llvm/test/CodeGen/Hexagon/isel/cmp-v4i1.ll
    llvm/test/CodeGen/Hexagon/isel/cmp-v8i1.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
    llvm/lib/Target/Hexagon/HexagonPatterns.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 3b0570951f8e8..d8068f018b667 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1731,6 +1731,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
     setOperationAction(ISD::STORE, VT, Custom);
   }
 
+  // Normalize integer compares to EQ/GT/UGT
   for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16,
                  MVT::v2i32}) {
     setCondCodeAction(ISD::SETNE,  VT, Expand);
@@ -1742,6 +1743,14 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
     setCondCodeAction(ISD::SETULT, VT, Expand);
   }
 
+  // Normalize boolean compares to [U]LE/[U]LT
+  for (MVT VT : {MVT::i1, MVT::v2i1, MVT::v4i1, MVT::v8i1}) {
+    setCondCodeAction(ISD::SETGE,  VT, Expand);
+    setCondCodeAction(ISD::SETGT,  VT, Expand);
+    setCondCodeAction(ISD::SETUGE, VT, Expand);
+    setCondCodeAction(ISD::SETUGT, VT, Expand);
+  }
+
   // Custom-lower bitcasts from i8 to v8i1.
   setOperationAction(ISD::BITCAST,        MVT::i8,    Custom);
   setOperationAction(ISD::SETCC,          MVT::v2i16, Custom);

diff  --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index d1c44db74de28..47cdf8759a166 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -845,9 +845,32 @@ def: Pat<(i32 (zext (i1 (setne I32:$Rs, anyimm:$s8)))),
 
 def: Pat<(i1 (seteq I1:$Ps, (i1 -1))), (I1:$Ps)>;
 def: Pat<(i1 (setne I1:$Ps, (i1 -1))), (C2_not I1:$Ps)>;
-def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)),  (C2_xor I1:$Ps, (C2_not I1:$Pt))>;
+def: Pat<(i1 (seteq I1:$Ps, I1:$Pt)),  (C2_not (C2_xor I1:$Ps, I1:$Pt))>;
 def: Pat<(i1 (setne I1:$Ps, I1:$Pt)),  (C2_xor I1:$Ps, I1:$Pt)>;
 
+multiclass BoolE_pat<PatFrag OpPred, ValueType ResTy> {
+  def: Pat<(ResTy (seteq OpPred:$Ps, OpPred:$Pt)), (C2_not (C2_xor $Ps, $Pt))>;
+  def: Pat<(ResTy (setne OpPred:$Ps, OpPred:$Pt)), (C2_xor $Ps, $Pt)>;
+}
+
+defm: BoolE_pat<I1,   i1>;
+defm: BoolE_pat<V2I1, v2i1>;
+defm: BoolE_pat<V4I1, v4i1>;
+defm: BoolE_pat<V8I1, v8i1>;
+
+multiclass BoolL_pat<PatFrag OpPred, ValueType ResTy> {
+  // Signed "true" == -1
+  def: Pat<(ResTy (setlt  OpPred:$Ps, OpPred:$Pt)), (C2_andn $Ps, $Pt)>;
+  def: Pat<(ResTy (setle  OpPred:$Ps, OpPred:$Pt)), (C2_orn  $Ps, $Pt)>;
+  def: Pat<(ResTy (setult OpPred:$Ps, OpPred:$Pt)), (C2_andn $Pt, $Ps)>;
+  def: Pat<(ResTy (setule OpPred:$Ps, OpPred:$Pt)), (C2_orn  $Pt, $Ps)>;
+}
+
+defm: BoolL_pat<I1,   i1>;
+defm: BoolL_pat<V2I1, v2i1>;
+defm: BoolL_pat<V4I1, v4i1>;
+defm: BoolL_pat<V8I1, v8i1>;
+
 // Floating-point comparisons with checks for ordered/unordered status.
 
 class T3<InstHexagon MI1, InstHexagon MI2, InstHexagon MI3>

diff  --git a/llvm/test/CodeGen/Hexagon/isel/cmp-i1.ll b/llvm/test/CodeGen/Hexagon/isel/cmp-i1.ll
new file mode 100644
index 0000000000000..7d589d21ed948
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel/cmp-i1.ll
@@ -0,0 +1,282 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+define void @f0(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f0:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = xor(p0,p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,#0,#1)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load i1, ptr %a0
+  %v1 = load i1, ptr %a1
+  %v2 = icmp eq i1 %v0, %v1
+  store i1 %v2, ptr %a2
+  ret void
+}
+
+define void @f1(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f1:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = xor(p0,p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load i1, ptr %a0
+  %v1 = load i1, ptr %a1
+  %v2 = icmp ne i1 %v0, %v1
+  store i1 %v2, ptr %a2
+  ret void
+}
+
+define void @f2(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f2:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load i1, ptr %a0
+  %v1 = load i1, ptr %a1
+  %v2 = icmp slt i1 %v0, %v1
+  store i1 %v2, ptr %a2
+  ret void
+}
+
+define void @f3(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f3:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load i1, ptr %a0
+  %v1 = load i1, ptr %a1
+  %v2 = icmp sle i1 %v0, %v1
+  store i1 %v2, ptr %a2
+  ret void
+}
+
+define void @f4(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f4:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load i1, ptr %a0
+  %v1 = load i1, ptr %a1
+  %v2 = icmp sgt i1 %v0, %v1
+  store i1 %v2, ptr %a2
+  ret void
+}
+
+define void @f5(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f5:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load i1, ptr %a0
+  %v1 = load i1, ptr %a1
+  %v2 = icmp sge i1 %v0, %v1
+  store i1 %v2, ptr %a2
+  ret void
+}
+
+define void @f6(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f6:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load i1, ptr %a0
+  %v1 = load i1, ptr %a1
+  %v2 = icmp ult i1 %v0, %v1
+  store i1 %v2, ptr %a2
+  ret void
+}
+
+define void @f7(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f7:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load i1, ptr %a0
+  %v1 = load i1, ptr %a1
+  %v2 = icmp ule i1 %v0, %v1
+  store i1 %v2, ptr %a2
+  ret void
+}
+
+define void @f8(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f8:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load i1, ptr %a0
+  %v1 = load i1, ptr %a1
+  %v2 = icmp ugt i1 %v0, %v1
+  store i1 %v2, ptr %a2
+  ret void
+}
+
+define void @f9(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f9:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = mux(p0,#1,#0)
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load i1, ptr %a0
+  %v1 = load i1, ptr %a1
+  %v2 = icmp uge i1 %v0, %v1
+  store i1 %v2, ptr %a2
+  ret void
+}

diff  --git a/llvm/test/CodeGen/Hexagon/isel/cmp-v2i1.ll b/llvm/test/CodeGen/Hexagon/isel/cmp-v2i1.ll
new file mode 100644
index 0000000000000..1f3df1122c64c
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel/cmp-v2i1.ll
@@ -0,0 +1,285 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+define void @f0(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f0:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = xor(p0,p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = not(p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <2 x i1>, ptr %a0
+  %v1 = load <2 x i1>, ptr %a1
+  %v2 = icmp eq <2 x i1> %v0, %v1
+  store <2 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f1(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f1:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = xor(p0,p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <2 x i1>, ptr %a0
+  %v1 = load <2 x i1>, ptr %a1
+  %v2 = icmp ne <2 x i1> %v0, %v1
+  store <2 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f2(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f2:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <2 x i1>, ptr %a0
+  %v1 = load <2 x i1>, ptr %a1
+  %v2 = icmp slt <2 x i1> %v0, %v1
+  store <2 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f3(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f3:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <2 x i1>, ptr %a0
+  %v1 = load <2 x i1>, ptr %a1
+  %v2 = icmp sle <2 x i1> %v0, %v1
+  store <2 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f4(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f4:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <2 x i1>, ptr %a0
+  %v1 = load <2 x i1>, ptr %a1
+  %v2 = icmp sgt <2 x i1> %v0, %v1
+  store <2 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f5(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f5:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <2 x i1>, ptr %a0
+  %v1 = load <2 x i1>, ptr %a1
+  %v2 = icmp sge <2 x i1> %v0, %v1
+  store <2 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f6(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f6:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <2 x i1>, ptr %a0
+  %v1 = load <2 x i1>, ptr %a1
+  %v2 = icmp ult <2 x i1> %v0, %v1
+  store <2 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f7(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f7:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <2 x i1>, ptr %a0
+  %v1 = load <2 x i1>, ptr %a1
+  %v2 = icmp ule <2 x i1> %v0, %v1
+  store <2 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f8(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f8:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <2 x i1>, ptr %a0
+  %v1 = load <2 x i1>, ptr %a1
+  %v2 = icmp ugt <2 x i1> %v0, %v1
+  store <2 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f9(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f9:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <2 x i1>, ptr %a0
+  %v1 = load <2 x i1>, ptr %a1
+  %v2 = icmp uge <2 x i1> %v0, %v1
+  store <2 x i1> %v2, ptr %a2
+  ret void
+}

diff  --git a/llvm/test/CodeGen/Hexagon/isel/cmp-v4i1.ll b/llvm/test/CodeGen/Hexagon/isel/cmp-v4i1.ll
new file mode 100644
index 0000000000000..e5c0abff4ce4e
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel/cmp-v4i1.ll
@@ -0,0 +1,285 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+define void @f0(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f0:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = xor(p0,p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = not(p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <4 x i1>, ptr %a0
+  %v1 = load <4 x i1>, ptr %a1
+  %v2 = icmp eq <4 x i1> %v0, %v1
+  store <4 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f1(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f1:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = xor(p0,p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <4 x i1>, ptr %a0
+  %v1 = load <4 x i1>, ptr %a1
+  %v2 = icmp ne <4 x i1> %v0, %v1
+  store <4 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f2(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f2:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <4 x i1>, ptr %a0
+  %v1 = load <4 x i1>, ptr %a1
+  %v2 = icmp slt <4 x i1> %v0, %v1
+  store <4 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f3(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f3:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <4 x i1>, ptr %a0
+  %v1 = load <4 x i1>, ptr %a1
+  %v2 = icmp sle <4 x i1> %v0, %v1
+  store <4 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f4(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f4:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <4 x i1>, ptr %a0
+  %v1 = load <4 x i1>, ptr %a1
+  %v2 = icmp sgt <4 x i1> %v0, %v1
+  store <4 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f5(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f5:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <4 x i1>, ptr %a0
+  %v1 = load <4 x i1>, ptr %a1
+  %v2 = icmp sge <4 x i1> %v0, %v1
+  store <4 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f6(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f6:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <4 x i1>, ptr %a0
+  %v1 = load <4 x i1>, ptr %a1
+  %v2 = icmp ult <4 x i1> %v0, %v1
+  store <4 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f7(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f7:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <4 x i1>, ptr %a0
+  %v1 = load <4 x i1>, ptr %a1
+  %v2 = icmp ule <4 x i1> %v0, %v1
+  store <4 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f8(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f8:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <4 x i1>, ptr %a0
+  %v1 = load <4 x i1>, ptr %a1
+  %v2 = icmp ugt <4 x i1> %v0, %v1
+  store <4 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f9(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f9:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <4 x i1>, ptr %a0
+  %v1 = load <4 x i1>, ptr %a1
+  %v2 = icmp uge <4 x i1> %v0, %v1
+  store <4 x i1> %v2, ptr %a2
+  ret void
+}

diff  --git a/llvm/test/CodeGen/Hexagon/isel/cmp-v8i1.ll b/llvm/test/CodeGen/Hexagon/isel/cmp-v8i1.ll
new file mode 100644
index 0000000000000..144bde4d58988
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel/cmp-v8i1.ll
@@ -0,0 +1,285 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+define void @f0(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f0:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = xor(p0,p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = not(p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <8 x i1>, ptr %a0
+  %v1 = load <8 x i1>, ptr %a1
+  %v2 = icmp eq <8 x i1> %v0, %v1
+  store <8 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f1(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f1:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = xor(p0,p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <8 x i1>, ptr %a0
+  %v1 = load <8 x i1>, ptr %a1
+  %v2 = icmp ne <8 x i1> %v0, %v1
+  store <8 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f2(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f2:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <8 x i1>, ptr %a0
+  %v1 = load <8 x i1>, ptr %a1
+  %v2 = icmp slt <8 x i1> %v0, %v1
+  store <8 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f3(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f3:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <8 x i1>, ptr %a0
+  %v1 = load <8 x i1>, ptr %a1
+  %v2 = icmp sle <8 x i1> %v0, %v1
+  store <8 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f4(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f4:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <8 x i1>, ptr %a0
+  %v1 = load <8 x i1>, ptr %a1
+  %v2 = icmp sgt <8 x i1> %v0, %v1
+  store <8 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f5(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f5:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <8 x i1>, ptr %a0
+  %v1 = load <8 x i1>, ptr %a1
+  %v2 = icmp sge <8 x i1> %v0, %v1
+  store <8 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f6(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f6:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <8 x i1>, ptr %a0
+  %v1 = load <8 x i1>, ptr %a1
+  %v2 = icmp ult <8 x i1> %v0, %v1
+  store <8 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f7(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f7:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p1,!p0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <8 x i1>, ptr %a0
+  %v1 = load <8 x i1>, ptr %a1
+  %v2 = icmp ule <8 x i1> %v0, %v1
+  store <8 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f8(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f8:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = and(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <8 x i1>, ptr %a0
+  %v1 = load <8 x i1>, ptr %a1
+  %v2 = icmp ugt <8 x i1> %v0, %v1
+  store <8 x i1> %v2, ptr %a2
+  ret void
+}
+
+define void @f9(ptr %a0, ptr %a1, ptr %a2) {
+; CHECK-LABEL: f9:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1 = memub(r1+#0)
+; CHECK-NEXT:     r0 = memub(r0+#0)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = r0
+; CHECK-NEXT:     p1 = r1
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = or(p0,!p1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r3 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r3.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = load <8 x i1>, ptr %a0
+  %v1 = load <8 x i1>, ptr %a1
+  %v2 = icmp uge <8 x i1> %v0, %v1
+  store <8 x i1> %v2, ptr %a2
+  ret void
+}


        


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