[llvm] d1c3ec6 - [Hexagon] Add missing patterns for truncate to vNi1

[Krzysztof Parzyszek via llvm-commits]

Author: Krzysztof Parzyszek
Date: 2023-06-17T16:31:21-07:00
New Revision: d1c3ec61d6543aeef8577c1baa5331fec9248c8d

URL: https://github.com/llvm/llvm-project/commit/d1c3ec61d6543aeef8577c1baa5331fec9248c8d
DIFF: https://github.com/llvm/llvm-project/commit/d1c3ec61d6543aeef8577c1baa5331fec9248c8d.diff

LOG: [Hexagon] Add missing patterns for truncate to vNi1

Added: 
    llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll

Modified: 
    llvm/lib/Target/Hexagon/HexagonPatterns.td

Removed: 
    


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diff  --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index 48a79cb9074d6..d1c44db74de28 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -562,6 +562,20 @@ def: Pat<(v4i8 (trunc V4I16:$Rs)),
 def: Pat<(v2i16 (trunc V2I32:$Rs)),
          (A2_combine_ll (HiReg $Rs), (LoReg $Rs))>;
 
+// Truncate to vNi1
+def: Pat<(v2i1 (trunc V2I32:$Rs)),
+         (A4_vcmpweqi (A2_andp V2I32:$Rs, (A2_combineii (i32 1), (i32 1))),
+                      (i32 1))>;
+def: Pat<(v4i1 (trunc V4I16:$Rs)),
+         (A4_vcmpheqi (Combinew (A2_andir (HiReg $Rs), (i32 0x00010001)),
+                                (A2_andir (LoReg $Rs), (i32 0x00010001))),
+                      (i32 1))>;
+def: Pat<(v8i1 (trunc V8I8:$Rs)),
+         (A4_vcmpbeqi (Combinew (A2_andir (HiReg $Rs), (i32 0x01010101)),
+                                (A2_andir (LoReg $Rs), (i32 0x01010101))),
+                      (i32 1))>;
+
+
 // Saturation:
 // Note: saturation assumes the same signed-ness for the input and the
 // output.

diff  --git a/llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll b/llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll
new file mode 100644
index 0000000000000..1394d49587de2
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/isel/trunc-vNi1.ll
@@ -0,0 +1,70 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+define void @f0(<2 x i32> %a0, ptr %a1) {
+; CHECK-LABEL: f0:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r5:4 = combine(#1,#1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r1:0 = and(r1:0,r5:4)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = vcmpw.eq(r1:0,#1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = trunc <2 x i32> %a0 to <2 x i1>
+  store <2 x i1> %v0, ptr %a1, align 1
+  ret void
+}
+
+define void @f1(<4 x i16> %a0, ptr %a1) {
+; CHECK-LABEL: f1:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = and(r0,##65537)
+; CHECK-NEXT:     r1 = and(r1,##65537)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = vcmph.eq(r1:0,#1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = trunc <4 x i16> %a0 to <4 x i1>
+  store <4 x i1> %v0, ptr %a1, align 1
+  ret void
+}
+
+define void @f2(<8 x i8> %a0, ptr %a1) {
+; CHECK-LABEL: f2:
+; CHECK:         .cfi_startproc
+; CHECK-NEXT:  // %bb.0: // %b0
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = and(r0,##16843009)
+; CHECK-NEXT:     r1 = and(r1,##16843009)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     p0 = vcmpb.eq(r1:0,#1)
+; CHECK-NEXT:    }
+; CHECK-NEXT:    {
+; CHECK-NEXT:     r0 = p0
+; CHECK-NEXT:     jumpr r31
+; CHECK-NEXT:     memb(r2+#0) = r0.new
+; CHECK-NEXT:    }
+b0:
+  %v0 = trunc <8 x i8> %a0 to <8 x i1>
+  store <8 x i1> %v0, ptr %a1, align 1
+  ret void
+}