[PATCH] D153204: RISCVAsmParser: support comments in more places

[Fangrui Song via Phabricator via llvm-commits]

MaskRay updated this revision to Diff 532415.
MaskRay edited the summary of this revision.
MaskRay added a comment.

support vsetvli


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153204/new/

https://reviews.llvm.org/D153204

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/test/MC/RISCV/rvi-pseudos.s
  llvm/test/MC/RISCV/rvv/vsetvl.s


Index: llvm/test/MC/RISCV/rvv/vsetvl.s
===================================================================
--- llvm/test/MC/RISCV/rvv/vsetvl.s
+++ llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -154,7 +154,7 @@
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
 # CHECK-UNKNOWN: 57 f6 07 cd <unknown>
 
-vsetivli a2, 31, e32, m1, ta, ma
+/**/vsetivli /**/a2/**/, /**/31/**/, /**/e32/**/, /**/m1/**/, /**/ta/**/, /**/ma/**/
 # CHECK-INST: vsetivli a2, 31, e32, m1, ta, ma
 # CHECK-ENCODING: [0x57,0xf6,0x0f,0xcd]
 # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' or 'Zve64x' (Vector Extensions for Embedded Processors){{$}}
Index: llvm/test/MC/RISCV/rvi-pseudos.s
===================================================================
--- llvm/test/MC/RISCV/rvi-pseudos.s
+++ llvm/test/MC/RISCV/rvi-pseudos.s
@@ -229,3 +229,13 @@
 # CHECK: auipc a5, %pcrel_hi(a_symbol-4)
 # CHECK: addi  a5, a5, %pcrel_lo(.Lpcrel_hi37)
 lla a5, a_symbol - 4
+
+# CHECK: .Lpcrel_hi38:
+# CHECK: auipc a5, %pcrel_hi(a_symbol-5)
+# CHECK: addi  a5, a5, %pcrel_lo(.Lpcrel_hi38)
+/**/lla /**/a5/**/, /**/a_symbol/**/ - /**/5/**/
+
+# CHECK: .Lpcrel_hi39:
+# CHECK: auipc a5, %pcrel_hi(a_symbol+5)
+# CHECK: addi  a5, a5, %pcrel_lo(.Lpcrel_hi39)
+/**/lla /**/a5/**/, /**/a_symbol/**/ + /**/5/**/
Index: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
===================================================================
--- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -1617,7 +1617,7 @@
       Operands.push_back(RISCVOperand::createToken("(", FirstS));
     SMLoc S = getLoc();
     SMLoc E = SMLoc::getFromPointer(S.getPointer() + Name.size());
-    getLexer().Lex();
+    Lex();
     Operands.push_back(RISCVOperand::createReg(RegNo, S, E));
   }
 
@@ -1978,11 +1978,11 @@
     return MatchOperand_Success;
   case AsmToken::Plus:
     Opcode = MCBinaryExpr::Add;
-    getLexer().Lex();
+    Lex();
     break;
   case AsmToken::Minus:
     Opcode = MCBinaryExpr::Sub;
-    getLexer().Lex();
+    Lex();
     break;
   }
 
@@ -2130,8 +2130,7 @@
   if (parseVTypeToken(Identifier, State, Sew, Lmul, Fractional, TailAgnostic,
                       MaskAgnostic))
     return MatchOperand_NoMatch;
-
-  getLexer().Lex();
+  Lex();
 
   while (parseOptionalToken(AsmToken::Comma)) {
     if (getLexer().isNot(AsmToken::Identifier))
@@ -2142,8 +2141,7 @@
     if (parseVTypeToken(Identifier, State, Sew, Lmul, Fractional, TailAgnostic,
                         MaskAgnostic))
       break;
-
-    getLexer().Lex();
+    Lex();
   }
 
   if (getLexer().is(AsmToken::EndOfStatement) && State == VTypeState_Done) {


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