[llvm] 01b5128 - [AMDGPU] Generate checks for load-constant tests
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 16 22:50:58 PDT 2023
Author: Jay Foad
Date: 2023-06-17T06:47:15+01:00
New Revision: 01b512882d75c5fd64ca0e78f28acd3f0e2254d8
URL: https://github.com/llvm/llvm-project/commit/01b512882d75c5fd64ca0e78f28acd3f0e2254d8
DIFF: https://github.com/llvm/llvm-project/commit/01b512882d75c5fd64ca0e78f28acd3f0e2254d8.diff
LOG: [AMDGPU] Generate checks for load-constant tests
Differential Revision: https://reviews.llvm.org/D153139
Added:
Modified:
llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-f32.ll b/llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
index 94f6772f791c0..b5f38c641da74 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
@@ -1,12 +1,58 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s
; Tests whether a load chain of 8 constants gets vectorized into a wider load.
-; FUNC-LABEL: {{^}}constant_load_v8f32:
-; GCN: s_load_dwordx8
-; EG: VTX_READ_128
-; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v8f32(ptr addrspace(4) noalias nocapture readonly %weights, ptr addrspace(1) noalias nocapture %out_ptr) {
+; GFX6-LABEL: constant_load_v8f32:
+; GFX6: ; %bb.0: ; %entry
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dword s16, s[10:11], 0x0
+; GFX6-NEXT: s_load_dwordx8 s[0:7], s[8:9], 0x0
+; GFX6-NEXT: s_mov_b32 s15, 0xf000
+; GFX6-NEXT: s_mov_b32 s14, -1
+; GFX6-NEXT: s_mov_b32 s12, s10
+; GFX6-NEXT: s_mov_b32 s13, s11
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s16
+; GFX6-NEXT: v_add_f32_e32 v0, s0, v0
+; GFX6-NEXT: v_add_f32_e32 v0, s1, v0
+; GFX6-NEXT: v_add_f32_e32 v0, s2, v0
+; GFX6-NEXT: v_add_f32_e32 v0, s3, v0
+; GFX6-NEXT: v_add_f32_e32 v0, s4, v0
+; GFX6-NEXT: v_add_f32_e32 v0, s5, v0
+; GFX6-NEXT: v_add_f32_e32 v0, s6, v0
+; GFX6-NEXT: v_add_f32_e32 v0, s7, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[12:15], 0
+; GFX6-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v8f32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 1, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 2 @6
+; EG-NEXT: ALU 9, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T2.XYZW, T1.X, 0, #1
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: VTX_READ_128 T1.XYZW, T1.X, 16, #1
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: MOV T0.X, KC0[2].Z,
+; EG-NEXT: MOV * T1.X, KC0[2].Y,
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: ADD * T0.W, T2.X, T0.X,
+; EG-NEXT: ADD * T0.W, T2.Y, PV.W,
+; EG-NEXT: ADD * T0.W, T2.Z, PV.W,
+; EG-NEXT: ADD * T0.W, T2.W, PV.W,
+; EG-NEXT: ADD * T0.W, T1.X, PV.W,
+; EG-NEXT: ADD * T0.W, T1.Y, PV.W,
+; EG-NEXT: ADD * T0.W, T1.Z, PV.W,
+; EG-NEXT: ADD T0.X, T1.W, PV.W,
+; EG-NEXT: LSHR * T1.X, KC0[2].Z, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%out_ptr.promoted = load float, ptr addrspace(1) %out_ptr, align 4
%tmp = load float, ptr addrspace(4) %weights, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-f64.ll b/llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
index 6984650ebbf0f..9382f1eb4f15a 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
@@ -1,12 +1,48 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
-; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6-NOHSA %s
+; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GFX7-HSA %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8-NOHSA %s
; FUNC-LABEL: {{^}}constant_load_f64:
-; GCN: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}]
-; GCN-NOHSA: buffer_store_dwordx2
-; GCN-HSA: flat_store_dwordx2
define amdgpu_kernel void @constant_load_f64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_f64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_f64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_f64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
%ld = load double, ptr addrspace(4) %in
store double %ld, ptr addrspace(1) %out
ret void
@@ -15,9 +51,74 @@ define amdgpu_kernel void @constant_load_f64(ptr addrspace(1) %out, ptr addrspac
attributes #0 = { nounwind }
; Tests whether a load-chain of 8 constants of 64bit each gets vectorized into a wider load.
-; FUNC-LABEL: {{^}}constant_load_2v4f64:
-; GCN: s_load_dwordx16
define amdgpu_kernel void @constant_load_2v4f64(ptr addrspace(4) noalias nocapture readonly %weights, ptr addrspace(1) noalias nocapture %out_ptr) {
+; GFX6-NOHSA-LABEL: constant_load_2v4f64:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[24:25], s[18:19], 0x0
+; GFX6-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s23, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s22, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s20, s18
+; GFX6-NOHSA-NEXT: s_mov_b32 s21, s19
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX6-NOHSA-NEXT: v_add_f64 v[0:1], s[0:1], v[0:1]
+; GFX6-NOHSA-NEXT: v_add_f64 v[0:1], s[2:3], v[0:1]
+; GFX6-NOHSA-NEXT: v_add_f64 v[0:1], s[4:5], v[0:1]
+; GFX6-NOHSA-NEXT: v_add_f64 v[0:1], s[6:7], v[0:1]
+; GFX6-NOHSA-NEXT: v_add_f64 v[0:1], s[8:9], v[0:1]
+; GFX6-NOHSA-NEXT: v_add_f64 v[0:1], s[10:11], v[0:1]
+; GFX6-NOHSA-NEXT: v_add_f64 v[0:1], s[12:13], v[0:1]
+; GFX6-NOHSA-NEXT: v_add_f64 v[0:1], s[14:15], v[0:1]
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[20:23], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_2v4f64:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[20:21], s[18:19], 0x0
+; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s19
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX7-HSA-NEXT: v_add_f64 v[0:1], s[0:1], v[0:1]
+; GFX7-HSA-NEXT: v_add_f64 v[0:1], s[2:3], v[0:1]
+; GFX7-HSA-NEXT: v_add_f64 v[0:1], s[4:5], v[0:1]
+; GFX7-HSA-NEXT: v_add_f64 v[0:1], s[6:7], v[0:1]
+; GFX7-HSA-NEXT: v_add_f64 v[0:1], s[8:9], v[0:1]
+; GFX7-HSA-NEXT: v_add_f64 v[0:1], s[10:11], v[0:1]
+; GFX7-HSA-NEXT: v_add_f64 v[0:1], s[12:13], v[0:1]
+; GFX7-HSA-NEXT: v_add_f64 v[0:1], s[14:15], v[0:1]
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_2v4f64:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[20:21], s[18:19], 0x0
+; GFX8-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[16:17], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s19
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX8-NOHSA-NEXT: v_add_f64 v[0:1], s[0:1], v[0:1]
+; GFX8-NOHSA-NEXT: v_add_f64 v[0:1], s[2:3], v[0:1]
+; GFX8-NOHSA-NEXT: v_add_f64 v[0:1], s[4:5], v[0:1]
+; GFX8-NOHSA-NEXT: v_add_f64 v[0:1], s[6:7], v[0:1]
+; GFX8-NOHSA-NEXT: v_add_f64 v[0:1], s[8:9], v[0:1]
+; GFX8-NOHSA-NEXT: v_add_f64 v[0:1], s[10:11], v[0:1]
+; GFX8-NOHSA-NEXT: v_add_f64 v[0:1], s[12:13], v[0:1]
+; GFX8-NOHSA-NEXT: v_add_f64 v[0:1], s[14:15], v[0:1]
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8-NOHSA-NEXT: s_endpgm
entry:
%out_ptr.promoted = load double, ptr addrspace(1) %out_ptr, align 4
%tmp = load double, ptr addrspace(4) %weights, align 4
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index 482e412589022..7f946e1d592c4 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -1,367 +1,7960 @@
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=amdgcn -mtriple=amdgcn-- -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -march=amdgcn -mtriple=amdgcn-- -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -march=r600 -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
-; FUNC-LABEL: {{^}}constant_load_i1:
-; GCN: buffer_load_ubyte
-; GCN: v_and_b32_e32 v{{[0-9]+}}, 1
-; GCN: buffer_store_byte
-
-; EG: VTX_READ_8
-; EG: AND_INT
define amdgpu_kernel void @constant_load_i1(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_load_i1:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX6-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_i1:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_i1:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.X, 1,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL T0.X, T1.W, PV.W,
+; EG-NEXT: LSHL * T0.W, literal.x, PV.W,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load i1, ptr addrspace(4) %in
store i1 %load, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v2i1:
define amdgpu_kernel void @constant_load_v2i1(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_load_v2i1:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_v2i1:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v2i1:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.X, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL T0.X, T1.W, PV.W,
+; EG-NEXT: LSHL * T0.W, literal.x, PV.W,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <2 x i1>, ptr addrspace(4) %in
store <2 x i1> %load, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v3i1:
define amdgpu_kernel void @constant_load_v3i1(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_load_v3i1:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_v3i1:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v3i1:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: AND_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL T0.X, T0.X, PV.W,
+; EG-NEXT: LSHL * T0.W, literal.x, PV.W,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <3 x i1>, ptr addrspace(4) %in
store <3 x i1> %load, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v4i1:
define amdgpu_kernel void @constant_load_v4i1(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_load_v4i1:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_v4i1:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v4i1:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.X, literal.y,
+; EG-NEXT: 3(4.203895e-45), 15(2.101948e-44)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL T0.X, T1.W, PV.W,
+; EG-NEXT: LSHL * T0.W, literal.x, PV.W,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <4 x i1>, ptr addrspace(4) %in
store <4 x i1> %load, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v8i1:
define amdgpu_kernel void @constant_load_v8i1(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_load_v8i1:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_v8i1:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v8i1:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.X, literal.y,
+; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL T0.X, T1.W, PV.W,
+; EG-NEXT: LSHL * T0.W, literal.x, PV.W,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <8 x i1>, ptr addrspace(4) %in
store <8 x i1> %load, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v16i1:
define amdgpu_kernel void @constant_load_v16i1(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_load_v16i1:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_short v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_v16i1:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ushort v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_short v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v16i1:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.X, literal.y,
+; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL T0.X, T1.W, PV.W,
+; EG-NEXT: LSHL * T0.W, literal.x, PV.W,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <16 x i1>, ptr addrspace(4) %in
store <16 x i1> %load, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v32i1:
define amdgpu_kernel void @constant_load_v32i1(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_load_v32i1:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_v32i1:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v32i1:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <32 x i1>, ptr addrspace(4) %in
store <32 x i1> %load, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v64i1:
define amdgpu_kernel void @constant_load_v64i1(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_load_v64i1:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_v64i1:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v64i1:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <64 x i1>, ptr addrspace(4) %in
store <64 x i1> %load, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_i1_to_i32:
-; GCN: buffer_load_ubyte
-; GCN: buffer_store_dword
define amdgpu_kernel void @constant_zextload_i1_to_i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_i1_to_i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_i1_to_i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_i1_to_i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%a = load i1, ptr addrspace(4) %in
%ext = zext i1 %a to i32
store i32 %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_i1_to_i32:
-; GCN: buffer_load_ubyte
-; GCN: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1{{$}}
-; GCN: buffer_store_dword
-
-; EG: VTX_READ_8
-; EG: BFE_INT
define amdgpu_kernel void @constant_sextload_i1_to_i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_i1_to_i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_i1_to_i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_i1_to_i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, 1,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%a = load i1, ptr addrspace(4) %in
%ext = sext i1 %a to i32
store i32 %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v1i1_to_v1i32:
define amdgpu_kernel void @constant_zextload_v1i1_to_v1i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v1i1_to_v1i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v1i1_to_v1i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v1i1_to_v1i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <1 x i1>, ptr addrspace(4) %in
%ext = zext <1 x i1> %load to <1 x i32>
store <1 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v1i1_to_v1i32:
define amdgpu_kernel void @constant_sextload_v1i1_to_v1i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v1i1_to_v1i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v1i1_to_v1i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v1i1_to_v1i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, 1,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <1 x i1>, ptr addrspace(4) %in
%ext = sext <1 x i1> %load to <1 x i32>
store <1 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v2i1_to_v2i32:
define amdgpu_kernel void @constant_zextload_v2i1_to_v2i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v2i1_to_v2i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v2i1_to_v2i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v2
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v4
+; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v2i1_to_v2i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_UINT * T0.Y, T0.X, 1, 1,
+; EG-NEXT: AND_INT T0.X, T0.X, 1,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <2 x i1>, ptr addrspace(4) %in
%ext = zext <2 x i1> %load to <2 x i32>
store <2 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v2i1_to_v2i32:
define amdgpu_kernel void @constant_sextload_v2i1_to_v2i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v2i1_to_v2i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_i32 v1, v0, 1, 1
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v2i1_to_v2i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 1, v2
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 1
+; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v2i1_to_v2i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T1.X, T0.X, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T0.X, 1,
+; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT * T1.Y, PV.W, 0.0, 1,
%load = load <2 x i1>, ptr addrspace(4) %in
%ext = sext <2 x i1> %load to <2 x i32>
store <2 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v3i1_to_v3i32:
define amdgpu_kernel void @constant_zextload_v3i1_to_v3i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v3i1_to_v3i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v2, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v2
+; GFX6-NEXT: v_bfe_u32 v1, v2, 1, 1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 2, v2
+; GFX6-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v3i1_to_v3i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v5, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 2, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v5
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX8-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v3i1_to_v3i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 8, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XY, T2.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_UINT * T1.Y, T0.X, 1, 1,
+; EG-NEXT: AND_INT T1.X, T0.X, 1,
+; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: LSHR T0.X, T0.X, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
+; EG-NEXT: LSHR * T3.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <3 x i1>, ptr addrspace(4) %in
%ext = zext <3 x i1> %load to <3 x i32>
store <3 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v3i1_to_v3i32:
define amdgpu_kernel void @constant_sextload_v3i1_to_v3i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v3i1_to_v3i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v2, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_i32 v1, v2, 1, 1
+; GFX6-NEXT: v_bfe_i32 v0, v2, 0, 1
+; GFX6-NEXT: v_bfe_i32 v2, v2, 2, 1
+; GFX6-NEXT: buffer_store_dword v2, off, s[4:7], 0 offset:8
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v3i1_to_v3i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 2, v0
+; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1
+; GFX8-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v3i1_to_v3i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T0.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: LSHR * T0.W, T0.X, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT * T2.X, PV.W, 0.0, 1,
+; EG-NEXT: BFE_INT T3.X, T0.X, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T0.X, 1,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T0.X, PS, literal.x,
+; EG-NEXT: BFE_INT * T3.Y, PV.W, 0.0, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <3 x i1>, ptr addrspace(4) %in
%ext = sext <3 x i1> %load to <3 x i32>
store <3 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v4i1_to_v4i32:
define amdgpu_kernel void @constant_zextload_v4i1_to_v4i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v4i1_to_v4i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v1, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 3, v1
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v1
+; GFX6-NEXT: v_bfe_u32 v2, v1, 2, 1
+; GFX6-NEXT: v_bfe_u32 v1, v1, 1, 1
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v4i1_to_v4i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 2, v0
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 3, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v6
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v4i1_to_v4i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_UINT * T0.W, T0.X, literal.x, 1,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T0.Z, T0.X, literal.x, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T0.Y, T0.X, 1, 1,
+; EG-NEXT: AND_INT T0.X, T0.X, 1,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <4 x i1>, ptr addrspace(4) %in
%ext = zext <4 x i1> %load to <4 x i32>
store <4 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v4i1_to_v4i32:
define amdgpu_kernel void @constant_sextload_v4i1_to_v4i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v4i1_to_v4i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_i32 v3, v0, 3, 1
+; GFX6-NEXT: v_bfe_i32 v2, v0, 2, 1
+; GFX6-NEXT: v_bfe_i32 v1, v0, 1, 1
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v4i1_to_v4i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 2, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 3, v0
+; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 1
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v4i1_to_v4i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T1.X, T0.X, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T0.X, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T1.W, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T0.X, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T1.Z, PS, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T0.X, 1,
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: BFE_INT * T1.Y, PV.W, 0.0, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <4 x i1>, ptr addrspace(4) %in
%ext = sext <4 x i1> %load to <4 x i32>
store <4 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v8i1_to_v8i32:
define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v8i1_to_v8i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v4, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_u32 v3, v4, 3, 1
+; GFX6-NEXT: v_bfe_u32 v1, v4, 1, 1
+; GFX6-NEXT: v_lshrrev_b32_e32 v7, 7, v4
+; GFX6-NEXT: v_bfe_u32 v5, v4, 5, 1
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v4
+; GFX6-NEXT: v_bfe_u32 v2, v4, 2, 1
+; GFX6-NEXT: v_bfe_u32 v6, v4, 6, 1
+; GFX6-NEXT: v_bfe_u32 v4, v4, 4, 1
+; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v8i1_to_v8i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v1, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v11, s3
+; GFX8-NEXT: v_mov_b32_e32 v9, s1
+; GFX8-NEXT: v_mov_b32_e32 v10, s2
+; GFX8-NEXT: v_mov_b32_e32 v8, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 5, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v5, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v12, 3, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 4, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, 6, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 2, v1
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, 7, v1
+; GFX8-NEXT: v_and_b32_e32 v13, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v5
+; GFX8-NEXT: v_and_b32_e32 v5, 1, v12
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v6
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v4
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v3
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff, v5
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff, v13
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
+; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v8i1_to_v8i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 17, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T8.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T7.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T5.X, T5.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T5.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_UINT * T6.W, T5.X, literal.x, 1,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T6.Z, T5.X, literal.x, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T6.Y, T5.X, 1, 1,
+; EG-NEXT: BFE_UINT * T5.W, T5.X, literal.x, 1,
+; EG-NEXT: 7(9.809089e-45), 0(0.000000e+00)
+; EG-NEXT: AND_INT T6.X, T5.X, 1,
+; EG-NEXT: BFE_UINT T5.Z, T5.X, literal.x, 1,
+; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.y,
+; EG-NEXT: 6(8.407791e-45), 2(2.802597e-45)
+; EG-NEXT: BFE_UINT * T5.Y, T5.X, literal.x, 1,
+; EG-NEXT: 5(7.006492e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T5.X, T5.X, literal.x, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 4(5.605194e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR * T8.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <8 x i1>, ptr addrspace(4) %in
%ext = zext <8 x i1> %load to <8 x i32>
store <8 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v8i1_to_v8i32:
define amdgpu_kernel void @constant_sextload_v8i1_to_v8i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v8i1_to_v8i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v4, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_i32 v3, v4, 3, 1
+; GFX6-NEXT: v_bfe_i32 v2, v4, 2, 1
+; GFX6-NEXT: v_bfe_i32 v1, v4, 1, 1
+; GFX6-NEXT: v_bfe_i32 v0, v4, 0, 1
+; GFX6-NEXT: v_bfe_i32 v7, v4, 7, 1
+; GFX6-NEXT: v_bfe_i32 v6, v4, 6, 1
+; GFX6-NEXT: v_bfe_i32 v5, v4, 5, 1
+; GFX6-NEXT: v_bfe_i32 v4, v4, 4, 1
+; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v8i1_to_v8i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v11, s3
+; GFX8-NEXT: v_mov_b32_e32 v9, s1
+; GFX8-NEXT: v_mov_b32_e32 v10, s2
+; GFX8-NEXT: v_mov_b32_e32 v8, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, 4, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v5, 5, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 6, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, 7, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 2, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 3, v0
+; GFX8-NEXT: v_bfe_i32 v7, v7, 0, 1
+; GFX8-NEXT: v_bfe_i32 v6, v6, 0, 1
+; GFX8-NEXT: v_bfe_i32 v5, v5, 0, 1
+; GFX8-NEXT: v_bfe_i32 v4, v4, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 1
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1
+; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
+; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v8i1_to_v8i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 23, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T5.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T8.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T5.X, T5.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T5.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T0.W, T5.X, literal.x,
+; EG-NEXT: 7(9.809089e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T6.W, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T5.X, literal.x,
+; EG-NEXT: 6(8.407791e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T7.X, T5.X, 0.0, 1,
+; EG-NEXT: BFE_INT T6.Z, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T5.X, literal.x,
+; EG-NEXT: LSHR * T1.W, T5.X, literal.y,
+; EG-NEXT: 3(4.203895e-45), 5(7.006492e-45)
+; EG-NEXT: LSHR T8.X, KC0[2].Y, literal.x,
+; EG-NEXT: BFE_INT T6.Y, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T5.X, literal.x,
+; EG-NEXT: BFE_INT T7.W, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T5.X, literal.y,
+; EG-NEXT: 2(2.802597e-45), 4(5.605194e-45)
+; EG-NEXT: BFE_INT T6.X, PS, 0.0, 1,
+; EG-NEXT: BFE_INT T7.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T5.X, 1,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T5.X, PS, literal.x,
+; EG-NEXT: BFE_INT * T7.Y, PV.W, 0.0, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <8 x i1>, ptr addrspace(4) %in
%ext = sext <8 x i1> %load to <8 x i32>
store <8 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v16i1_to_v16i32:
define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v16i1_to_v16i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ushort v12, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_u32 v3, v12, 3, 1
+; GFX6-NEXT: v_bfe_u32 v1, v12, 1, 1
+; GFX6-NEXT: v_bfe_u32 v7, v12, 7, 1
+; GFX6-NEXT: v_bfe_u32 v5, v12, 5, 1
+; GFX6-NEXT: v_bfe_u32 v11, v12, 11, 1
+; GFX6-NEXT: v_bfe_u32 v9, v12, 9, 1
+; GFX6-NEXT: v_lshrrev_b32_e32 v15, 15, v12
+; GFX6-NEXT: v_bfe_u32 v13, v12, 13, 1
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v12
+; GFX6-NEXT: v_bfe_u32 v2, v12, 2, 1
+; GFX6-NEXT: v_bfe_u32 v6, v12, 6, 1
+; GFX6-NEXT: v_bfe_u32 v4, v12, 4, 1
+; GFX6-NEXT: v_bfe_u32 v10, v12, 10, 1
+; GFX6-NEXT: v_bfe_u32 v8, v12, 8, 1
+; GFX6-NEXT: v_bfe_u32 v14, v12, 14, 1
+; GFX6-NEXT: v_bfe_u32 v12, v12, 12, 1
+; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:48
+; GFX6-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:32
+; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v16i1_to_v16i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ushort v1, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v19, s3
+; GFX8-NEXT: v_mov_b32_e32 v18, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NEXT: v_mov_b32_e32 v0, 1
+; GFX8-NEXT: v_mov_b32_e32 v17, s1
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v16, s0
+; GFX8-NEXT: s_add_u32 s0, s0, 16
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v21, s3
+; GFX8-NEXT: v_mov_b32_e32 v23, s1
+; GFX8-NEXT: v_mov_b32_e32 v20, s2
+; GFX8-NEXT: v_mov_b32_e32 v22, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 12, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v8, 3, v1
+; GFX8-NEXT: v_and_b32_e32 v12, 1, v8
+; GFX8-NEXT: v_and_b32_e32 v8, 1, v3
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX8-NEXT: v_and_b32_e32 v13, 0xffff, v3
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 7, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, 14, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v11, 2, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX8-NEXT: v_lshrrev_b16_e32 v5, 13, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v9, 9, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 10, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, 4, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 6, v1
+; GFX8-NEXT: v_and_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_e32 v10, 1, v7
+; GFX8-NEXT: v_and_b32_e32 v14, 1, v11
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff, v12
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff, v3
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 11, v1
+; GFX8-NEXT: v_and_b32_e32 v12, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v11, 15, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 5, v1
+; GFX8-NEXT: v_and_b32_e32 v24, 1, v5
+; GFX8-NEXT: v_and_b32_e32 v9, 1, v9
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff, v1
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v9
+; GFX8-NEXT: v_and_b32_e32 v9, 0xffff, v24
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[8:11]
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[0:3]
+; GFX8-NEXT: flat_store_dwordx4 v[22:23], v[4:7]
+; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v16i1_to_v16i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 36, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T14.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T13.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T12.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T10.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_16 T7.X, T7.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T7.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: BFE_UINT * T8.W, T7.X, literal.x, 1,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T8.Z, T7.X, literal.x, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T8.Y, T7.X, 1, 1,
+; EG-NEXT: BFE_UINT * T9.W, T7.X, literal.x, 1,
+; EG-NEXT: 7(9.809089e-45), 0(0.000000e+00)
+; EG-NEXT: AND_INT T8.X, T7.X, 1,
+; EG-NEXT: BFE_UINT T9.Z, T7.X, literal.x, 1,
+; EG-NEXT: LSHR * T10.X, KC0[2].Y, literal.y,
+; EG-NEXT: 6(8.407791e-45), 2(2.802597e-45)
+; EG-NEXT: BFE_UINT T9.Y, T7.X, literal.x, 1,
+; EG-NEXT: BFE_UINT * T11.W, T7.X, literal.y, 1,
+; EG-NEXT: 5(7.006492e-45), 11(1.541428e-44)
+; EG-NEXT: BFE_UINT T9.X, T7.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T11.Z, T7.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 4(5.605194e-45), 10(1.401298e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T12.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T11.Y, T7.X, literal.y, 1,
+; EG-NEXT: LSHR * T7.W, T7.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 9(1.261169e-44)
+; EG-NEXT: 15(2.101948e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T11.X, T7.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T7.Z, T7.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 8(1.121039e-44), 14(1.961818e-44)
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T13.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT * T7.Y, T7.X, literal.y, 1,
+; EG-NEXT: 2(2.802597e-45), 13(1.821688e-44)
+; EG-NEXT: BFE_UINT T7.X, T7.X, literal.x, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 12(1.681558e-44), 48(6.726233e-44)
+; EG-NEXT: LSHR * T14.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <16 x i1>, ptr addrspace(4) %in
%ext = zext <16 x i1> %load to <16 x i32>
store <16 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v16i1_to_v16i32:
define amdgpu_kernel void @constant_sextload_v16i1_to_v16i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v16i1_to_v16i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ushort v12, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_i32 v3, v12, 3, 1
+; GFX6-NEXT: v_bfe_i32 v2, v12, 2, 1
+; GFX6-NEXT: v_bfe_i32 v1, v12, 1, 1
+; GFX6-NEXT: v_bfe_i32 v0, v12, 0, 1
+; GFX6-NEXT: v_bfe_i32 v7, v12, 7, 1
+; GFX6-NEXT: v_bfe_i32 v6, v12, 6, 1
+; GFX6-NEXT: v_bfe_i32 v5, v12, 5, 1
+; GFX6-NEXT: v_bfe_i32 v4, v12, 4, 1
+; GFX6-NEXT: v_bfe_i32 v11, v12, 11, 1
+; GFX6-NEXT: v_bfe_i32 v10, v12, 10, 1
+; GFX6-NEXT: v_bfe_i32 v9, v12, 9, 1
+; GFX6-NEXT: v_bfe_i32 v8, v12, 8, 1
+; GFX6-NEXT: v_bfe_i32 v15, v12, 15, 1
+; GFX6-NEXT: v_bfe_i32 v14, v12, 14, 1
+; GFX6-NEXT: v_bfe_i32 v13, v12, 13, 1
+; GFX6-NEXT: v_bfe_i32 v12, v12, 12, 1
+; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0 offset:48
+; GFX6-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:32
+; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v16i1_to_v16i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ushort v0, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v19, s3
+; GFX8-NEXT: v_mov_b32_e32 v18, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NEXT: v_mov_b32_e32 v17, s1
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v16, s0
+; GFX8-NEXT: s_add_u32 s0, s0, 16
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v21, s3
+; GFX8-NEXT: v_mov_b32_e32 v23, s1
+; GFX8-NEXT: v_mov_b32_e32 v20, s2
+; GFX8-NEXT: v_mov_b32_e32 v22, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v12, 12, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v13, 13, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v14, 14, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v15, 15, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v8, 8, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v9, 9, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v10, 10, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v11, 11, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, 4, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v5, 5, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 6, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, 7, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 2, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 3, v0
+; GFX8-NEXT: v_bfe_i32 v15, v15, 0, 1
+; GFX8-NEXT: v_bfe_i32 v14, v14, 0, 1
+; GFX8-NEXT: v_bfe_i32 v13, v13, 0, 1
+; GFX8-NEXT: v_bfe_i32 v12, v12, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 1
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1
+; GFX8-NEXT: v_bfe_i32 v7, v7, 0, 1
+; GFX8-NEXT: v_bfe_i32 v6, v6, 0, 1
+; GFX8-NEXT: v_bfe_i32 v5, v5, 0, 1
+; GFX8-NEXT: v_bfe_i32 v4, v4, 0, 1
+; GFX8-NEXT: v_bfe_i32 v11, v11, 0, 1
+; GFX8-NEXT: v_bfe_i32 v10, v10, 0, 1
+; GFX8-NEXT: v_bfe_i32 v9, v9, 0, 1
+; GFX8-NEXT: v_bfe_i32 v8, v8, 0, 1
+; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[12:15]
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[8:11]
+; GFX8-NEXT: flat_store_dwordx4 v[22:23], v[4:7]
+; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v16i1_to_v16i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 51, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T7.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XYZW, T14.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T11.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T9.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_16 T7.X, T7.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T7.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: LSHR * T0.W, T7.X, literal.x,
+; EG-NEXT: 7(9.809089e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T8.W, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T7.X, literal.x,
+; EG-NEXT: 6(8.407791e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T8.Z, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T7.X, literal.x,
+; EG-NEXT: LSHR * T1.W, T7.X, literal.y,
+; EG-NEXT: 11(1.541428e-44), 5(7.006492e-45)
+; EG-NEXT: LSHR T9.X, KC0[2].Y, literal.x,
+; EG-NEXT: BFE_INT T8.Y, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T7.X, literal.y,
+; EG-NEXT: BFE_INT T10.W, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T7.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 10(1.401298e-44)
+; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T8.X, PS, 0.0, 1,
+; EG-NEXT: BFE_INT T10.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T7.X, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 9(1.261169e-44), 16(2.242078e-44)
+; EG-NEXT: LSHR T11.X, PS, literal.x,
+; EG-NEXT: BFE_INT T10.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T7.X, literal.y,
+; EG-NEXT: LSHR * T1.W, T7.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 15(2.101948e-44)
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T10.X, PS, 0.0, 1,
+; EG-NEXT: BFE_INT T12.W, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T7.X, literal.x,
+; EG-NEXT: 14(1.961818e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T13.X, T7.X, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T7.X, literal.x,
+; EG-NEXT: BFE_INT T12.Z, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T7.X, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 3(4.203895e-45), 13(1.821688e-44)
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T14.X, PS, literal.x,
+; EG-NEXT: BFE_INT T12.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T7.X, literal.x,
+; EG-NEXT: BFE_INT T13.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T7.X, literal.y,
+; EG-NEXT: 2(2.802597e-45), 12(1.681558e-44)
+; EG-NEXT: BFE_INT T12.X, PS, 0.0, 1,
+; EG-NEXT: BFE_INT T13.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T7.X, 1,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,
+; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T7.X, PS, literal.x,
+; EG-NEXT: BFE_INT * T13.Y, PV.W, 0.0, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <16 x i1>, ptr addrspace(4) %in
%ext = sext <16 x i1> %load to <16 x i32>
store <16 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v32i1_to_v32i32:
define amdgpu_kernel void @constant_zextload_v32i1_to_v32i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v32i1_to_v32i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_bfe_u32 s5, s4, 0x10003
+; GFX6-NEXT: s_bfe_u32 s6, s4, 0x10001
+; GFX6-NEXT: s_bfe_u32 s7, s4, 0x10007
+; GFX6-NEXT: s_bfe_u32 s8, s4, 0x10005
+; GFX6-NEXT: s_bfe_u32 s9, s4, 0x1000b
+; GFX6-NEXT: s_bfe_u32 s10, s4, 0x10009
+; GFX6-NEXT: s_bfe_u32 s11, s4, 0x1000f
+; GFX6-NEXT: s_bfe_u32 s12, s4, 0x1000d
+; GFX6-NEXT: s_bfe_u32 s13, s4, 0x10013
+; GFX6-NEXT: s_bfe_u32 s14, s4, 0x10011
+; GFX6-NEXT: s_bfe_u32 s15, s4, 0x10017
+; GFX6-NEXT: s_bfe_u32 s16, s4, 0x10015
+; GFX6-NEXT: s_bfe_u32 s17, s4, 0x1001b
+; GFX6-NEXT: s_bfe_u32 s18, s4, 0x10019
+; GFX6-NEXT: s_lshr_b32 s19, s4, 31
+; GFX6-NEXT: s_bfe_u32 s20, s4, 0x1001d
+; GFX6-NEXT: s_and_b32 s21, s4, 1
+; GFX6-NEXT: s_bfe_u32 s22, s4, 0x10002
+; GFX6-NEXT: s_bfe_u32 s23, s4, 0x10006
+; GFX6-NEXT: s_bfe_u32 s24, s4, 0x10004
+; GFX6-NEXT: s_bfe_u32 s25, s4, 0x1000a
+; GFX6-NEXT: s_bfe_u32 s26, s4, 0x10008
+; GFX6-NEXT: s_bfe_u32 s27, s4, 0x1000e
+; GFX6-NEXT: s_bfe_u32 s28, s4, 0x1000c
+; GFX6-NEXT: s_bfe_u32 s29, s4, 0x10012
+; GFX6-NEXT: s_bfe_u32 s30, s4, 0x10010
+; GFX6-NEXT: s_bfe_u32 s31, s4, 0x10016
+; GFX6-NEXT: s_bfe_u32 s33, s4, 0x10014
+; GFX6-NEXT: s_bfe_u32 s34, s4, 0x1001a
+; GFX6-NEXT: s_bfe_u32 s35, s4, 0x1001e
+; GFX6-NEXT: s_bfe_u32 s36, s4, 0x1001c
+; GFX6-NEXT: s_bfe_u32 s4, s4, 0x10018
+; GFX6-NEXT: v_mov_b32_e32 v0, s36
+; GFX6-NEXT: v_mov_b32_e32 v1, s20
+; GFX6-NEXT: v_mov_b32_e32 v2, s35
+; GFX6-NEXT: v_mov_b32_e32 v3, s19
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s18
+; GFX6-NEXT: v_mov_b32_e32 v2, s34
+; GFX6-NEXT: v_mov_b32_e32 v3, s17
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s33
+; GFX6-NEXT: v_mov_b32_e32 v1, s16
+; GFX6-NEXT: v_mov_b32_e32 v2, s31
+; GFX6-NEXT: v_mov_b32_e32 v3, s15
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s30
+; GFX6-NEXT: v_mov_b32_e32 v1, s14
+; GFX6-NEXT: v_mov_b32_e32 v2, s29
+; GFX6-NEXT: v_mov_b32_e32 v3, s13
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s28
+; GFX6-NEXT: v_mov_b32_e32 v1, s12
+; GFX6-NEXT: v_mov_b32_e32 v2, s27
+; GFX6-NEXT: v_mov_b32_e32 v3, s11
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s26
+; GFX6-NEXT: v_mov_b32_e32 v1, s10
+; GFX6-NEXT: v_mov_b32_e32 v2, s25
+; GFX6-NEXT: v_mov_b32_e32 v3, s9
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s24
+; GFX6-NEXT: v_mov_b32_e32 v1, s8
+; GFX6-NEXT: v_mov_b32_e32 v2, s23
+; GFX6-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s21
+; GFX6-NEXT: v_mov_b32_e32 v1, s6
+; GFX6-NEXT: v_mov_b32_e32 v2, s22
+; GFX6-NEXT: v_mov_b32_e32 v3, s5
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v32i1_to_v32i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 13, s4
+; GFX8-NEXT: v_and_b32_e32 v24, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 5, s4
+; GFX8-NEXT: v_and_b32_e32 v22, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 7, s4
+; GFX8-NEXT: v_and_b32_e32 v15, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 1, s4
+; GFX8-NEXT: v_and_b32_e32 v23, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 3, s4
+; GFX8-NEXT: s_lshr_b32 s2, s4, 24
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 9, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v3, 11, s4
+; GFX8-NEXT: v_and_b32_e32 v26, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 5, s2
+; GFX8-NEXT: v_and_b32_e32 v17, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v18, 1, v3
+; GFX8-NEXT: v_lshrrev_b16_e64 v4, 4, s2
+; GFX8-NEXT: v_and_b32_e32 v5, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v6, 6, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 1, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 2, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v3, 3, s2
+; GFX8-NEXT: s_bfe_u32 s5, s4, 0x10018
+; GFX8-NEXT: v_lshrrev_b16_e64 v7, 7, s2
+; GFX8-NEXT: s_and_b32 s6, s4, 1
+; GFX8-NEXT: s_bfe_u32 s7, s4, 0x10013
+; GFX8-NEXT: s_bfe_u32 s8, s4, 0x10012
+; GFX8-NEXT: s_bfe_u32 s9, s4, 0x10011
+; GFX8-NEXT: s_bfe_u32 s10, s4, 0x10010
+; GFX8-NEXT: s_bfe_u32 s2, s4, 0x10017
+; GFX8-NEXT: s_bfe_u32 s3, s4, 0x10016
+; GFX8-NEXT: s_bfe_u32 s11, s4, 0x10015
+; GFX8-NEXT: s_bfe_u32 s12, s4, 0x10014
+; GFX8-NEXT: v_mov_b32_e32 v11, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 0x50
+; GFX8-NEXT: v_mov_b32_e32 v10, s3
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v13, s3
+; GFX8-NEXT: v_mov_b32_e32 v12, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 64
+; GFX8-NEXT: v_mov_b32_e32 v8, s12
+; GFX8-NEXT: v_mov_b32_e32 v9, s11
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
+; GFX8-NEXT: v_mov_b32_e32 v13, s3
+; GFX8-NEXT: v_mov_b32_e32 v12, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NEXT: v_lshrrev_b16_e64 v21, 14, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v25, 2, s4
+; GFX8-NEXT: v_mov_b32_e32 v8, s10
+; GFX8-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NEXT: v_mov_b32_e32 v10, s8
+; GFX8-NEXT: v_mov_b32_e32 v11, s7
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
+; GFX8-NEXT: v_and_b32_e32 v13, 0xffff, v22
+; GFX8-NEXT: v_and_b32_e32 v10, 1, v25
+; GFX8-NEXT: v_and_b32_e32 v22, 1, v21
+; GFX8-NEXT: v_and_b32_e32 v21, 0xffff, v24
+; GFX8-NEXT: v_mov_b32_e32 v25, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v20, 12, s4
+; GFX8-NEXT: v_mov_b32_e32 v24, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NEXT: v_and_b32_e32 v9, 0xffff, v23
+; GFX8-NEXT: v_lshrrev_b16_e64 v23, 15, s4
+; GFX8-NEXT: v_and_b32_e32 v20, 1, v20
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[24:25], v[20:23]
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v21, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v16, 10, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v19, 4, s4
+; GFX8-NEXT: v_mov_b32_e32 v8, 1
+; GFX8-NEXT: v_mov_b32_e32 v20, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NEXT: v_and_b32_e32 v12, 1, v19
+; GFX8-NEXT: v_and_b32_e32 v19, 0xffff, v18
+; GFX8-NEXT: v_and_b32_e32 v18, 1, v16
+; GFX8-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; GFX8-NEXT: v_and_b32_sdwa v16, v0, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v14, 6, s4
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; GFX8-NEXT: v_mov_b32_e32 v17, s3
+; GFX8-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX8-NEXT: v_mov_b32_e32 v16, s2
+; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
+; GFX8-NEXT: s_add_u32 s2, s0, 0x70
+; GFX8-NEXT: v_mov_b32_e32 v13, s1
+; GFX8-NEXT: v_and_b32_e32 v11, 0xffff, v26
+; GFX8-NEXT: v_mov_b32_e32 v8, s6
+; GFX8-NEXT: v_mov_b32_e32 v12, s0
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
+; GFX8-NEXT: s_add_u32 s0, s0, 0x60
+; GFX8-NEXT: v_mov_b32_e32 v9, s3
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff, v5
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v4
+; GFX8-NEXT: v_mov_b32_e32 v8, s2
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, s5
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v32i1_to_v32i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @12
+; EG-NEXT: ALU 76, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T26.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T23.XYZW, T25.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T21.XYZW, T24.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T22.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T20.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T18.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T16.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T14.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 12:
+; EG-NEXT: VTX_READ_32 T11.X, T11.X, 0, #1
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: MOV * T11.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 15:
+; EG-NEXT: BFE_UINT * T12.W, T11.X, literal.x, 1,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T12.Z, T11.X, literal.x, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T12.Y, T11.X, 1, 1,
+; EG-NEXT: BFE_UINT * T13.W, T11.X, literal.x, 1,
+; EG-NEXT: 7(9.809089e-45), 0(0.000000e+00)
+; EG-NEXT: AND_INT T12.X, T11.X, 1,
+; EG-NEXT: BFE_UINT T13.Z, T11.X, literal.x, 1,
+; EG-NEXT: LSHR * T14.X, KC0[2].Y, literal.y,
+; EG-NEXT: 6(8.407791e-45), 2(2.802597e-45)
+; EG-NEXT: BFE_UINT T13.Y, T11.X, literal.x, 1,
+; EG-NEXT: BFE_UINT * T15.W, T11.X, literal.y, 1,
+; EG-NEXT: 5(7.006492e-45), 11(1.541428e-44)
+; EG-NEXT: BFE_UINT T13.X, T11.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T15.Z, T11.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 4(5.605194e-45), 10(1.401298e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T16.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T15.Y, T11.X, literal.y, 1,
+; EG-NEXT: BFE_UINT * T17.W, T11.X, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 9(1.261169e-44)
+; EG-NEXT: 15(2.101948e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T15.X, T11.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T17.Z, T11.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 8(1.121039e-44), 14(1.961818e-44)
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T18.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T17.Y, T11.X, literal.y, 1,
+; EG-NEXT: BFE_UINT * T19.W, T11.X, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 13(1.821688e-44)
+; EG-NEXT: 19(2.662467e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T17.X, T11.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T19.Z, T11.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 12(1.681558e-44), 18(2.522337e-44)
+; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T20.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T19.Y, T11.X, literal.y, 1,
+; EG-NEXT: BFE_UINT * T21.W, T11.X, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 17(2.382207e-44)
+; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T19.X, T11.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T21.Z, T11.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 16(2.242078e-44), 22(3.082857e-44)
+; EG-NEXT: 64(8.968310e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T22.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T21.Y, T11.X, literal.y, 1,
+; EG-NEXT: BFE_UINT * T23.W, T11.X, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 21(2.942727e-44)
+; EG-NEXT: 27(3.783506e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T21.X, T11.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T23.Z, T11.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 20(2.802597e-44), 26(3.643376e-44)
+; EG-NEXT: 80(1.121039e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T24.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T23.Y, T11.X, literal.y, 1,
+; EG-NEXT: LSHR * T11.W, T11.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 25(3.503246e-44)
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T23.X, T11.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T11.Z, T11.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 24(3.363116e-44), 30(4.203895e-44)
+; EG-NEXT: 96(1.345247e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T25.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT * T11.Y, T11.X, literal.y, 1,
+; EG-NEXT: 2(2.802597e-45), 29(4.063766e-44)
+; EG-NEXT: BFE_UINT T11.X, T11.X, literal.x, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 28(3.923636e-44), 112(1.569454e-43)
+; EG-NEXT: LSHR * T26.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <32 x i1>, ptr addrspace(4) %in
%ext = zext <32 x i1> %load to <32 x i32>
store <32 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v32i1_to_v32i32:
define amdgpu_kernel void @constant_sextload_v32i1_to_v32i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v32i1_to_v32i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_bfe_i32 s5, s4, 0x10003
+; GFX6-NEXT: s_bfe_i32 s6, s4, 0x10002
+; GFX6-NEXT: s_bfe_i32 s7, s4, 0x10001
+; GFX6-NEXT: s_bfe_i32 s8, s4, 0x10000
+; GFX6-NEXT: s_bfe_i32 s9, s4, 0x10007
+; GFX6-NEXT: s_bfe_i32 s10, s4, 0x10006
+; GFX6-NEXT: s_bfe_i32 s11, s4, 0x10005
+; GFX6-NEXT: s_bfe_i32 s12, s4, 0x10004
+; GFX6-NEXT: s_bfe_i32 s13, s4, 0x1000b
+; GFX6-NEXT: s_bfe_i32 s14, s4, 0x1000a
+; GFX6-NEXT: s_bfe_i32 s15, s4, 0x10009
+; GFX6-NEXT: s_bfe_i32 s16, s4, 0x10008
+; GFX6-NEXT: s_bfe_i32 s17, s4, 0x1000f
+; GFX6-NEXT: s_bfe_i32 s18, s4, 0x1000e
+; GFX6-NEXT: s_bfe_i32 s19, s4, 0x1000d
+; GFX6-NEXT: s_bfe_i32 s20, s4, 0x1000c
+; GFX6-NEXT: s_bfe_i32 s21, s4, 0x10013
+; GFX6-NEXT: s_bfe_i32 s22, s4, 0x10012
+; GFX6-NEXT: s_bfe_i32 s23, s4, 0x10011
+; GFX6-NEXT: s_bfe_i32 s24, s4, 0x10010
+; GFX6-NEXT: s_bfe_i32 s25, s4, 0x10017
+; GFX6-NEXT: s_bfe_i32 s26, s4, 0x10016
+; GFX6-NEXT: s_bfe_i32 s27, s4, 0x10015
+; GFX6-NEXT: s_bfe_i32 s28, s4, 0x10014
+; GFX6-NEXT: s_bfe_i32 s29, s4, 0x1001b
+; GFX6-NEXT: s_bfe_i32 s30, s4, 0x1001a
+; GFX6-NEXT: s_bfe_i32 s31, s4, 0x10019
+; GFX6-NEXT: s_ashr_i32 s33, s4, 31
+; GFX6-NEXT: s_bfe_i32 s34, s4, 0x1001e
+; GFX6-NEXT: s_bfe_i32 s35, s4, 0x1001d
+; GFX6-NEXT: s_bfe_i32 s36, s4, 0x1001c
+; GFX6-NEXT: s_bfe_i32 s4, s4, 0x10018
+; GFX6-NEXT: v_mov_b32_e32 v0, s36
+; GFX6-NEXT: v_mov_b32_e32 v1, s35
+; GFX6-NEXT: v_mov_b32_e32 v2, s34
+; GFX6-NEXT: v_mov_b32_e32 v3, s33
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s31
+; GFX6-NEXT: v_mov_b32_e32 v2, s30
+; GFX6-NEXT: v_mov_b32_e32 v3, s29
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s28
+; GFX6-NEXT: v_mov_b32_e32 v1, s27
+; GFX6-NEXT: v_mov_b32_e32 v2, s26
+; GFX6-NEXT: v_mov_b32_e32 v3, s25
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s24
+; GFX6-NEXT: v_mov_b32_e32 v1, s23
+; GFX6-NEXT: v_mov_b32_e32 v2, s22
+; GFX6-NEXT: v_mov_b32_e32 v3, s21
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s20
+; GFX6-NEXT: v_mov_b32_e32 v1, s19
+; GFX6-NEXT: v_mov_b32_e32 v2, s18
+; GFX6-NEXT: v_mov_b32_e32 v3, s17
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s16
+; GFX6-NEXT: v_mov_b32_e32 v1, s15
+; GFX6-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NEXT: v_mov_b32_e32 v3, s13
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NEXT: v_mov_b32_e32 v1, s11
+; GFX6-NEXT: v_mov_b32_e32 v2, s10
+; GFX6-NEXT: v_mov_b32_e32 v3, s9
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NEXT: v_mov_b32_e32 v1, s7
+; GFX6-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NEXT: v_mov_b32_e32 v3, s5
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v32i1_to_v32i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_lshr_b32 s3, s2, 24
+; GFX8-NEXT: v_lshrrev_b16_e64 v8, 12, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v20, 13, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v21, 14, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v22, 15, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v16, 8, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v17, 9, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v18, 10, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v19, 11, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v12, 4, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v13, 5, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v14, 6, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v15, 7, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 1, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v10, 2, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v11, 3, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v23, 4, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v24, 5, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v6, 6, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v7, 7, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v25, 1, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v26, 2, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v27, 3, s3
+; GFX8-NEXT: s_bfe_i32 s4, s2, 0x10018
+; GFX8-NEXT: s_bfe_i32 s5, s2, 0x10000
+; GFX8-NEXT: s_bfe_i32 s6, s2, 0x10013
+; GFX8-NEXT: s_bfe_i32 s7, s2, 0x10012
+; GFX8-NEXT: s_bfe_i32 s8, s2, 0x10011
+; GFX8-NEXT: s_bfe_i32 s9, s2, 0x10010
+; GFX8-NEXT: s_bfe_i32 s3, s2, 0x10017
+; GFX8-NEXT: s_bfe_i32 s10, s2, 0x10016
+; GFX8-NEXT: s_bfe_i32 s11, s2, 0x10015
+; GFX8-NEXT: s_bfe_i32 s2, s2, 0x10014
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 0x50
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 64
+; GFX8-NEXT: v_mov_b32_e32 v1, s11
+; GFX8-NEXT: v_mov_b32_e32 v2, s10
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NEXT: v_mov_b32_e32 v0, s9
+; GFX8-NEXT: v_mov_b32_e32 v1, s8
+; GFX8-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NEXT: v_mov_b32_e32 v3, s6
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_bfe_i32 v5, v24, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v25, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v25, s3
+; GFX8-NEXT: v_mov_b32_e32 v24, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NEXT: v_bfe_i32 v4, v23, 0, 1
+; GFX8-NEXT: v_bfe_i32 v23, v22, 0, 1
+; GFX8-NEXT: v_bfe_i32 v22, v21, 0, 1
+; GFX8-NEXT: v_bfe_i32 v21, v20, 0, 1
+; GFX8-NEXT: v_bfe_i32 v20, v8, 0, 1
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[24:25], v[20:23]
+; GFX8-NEXT: v_bfe_i32 v19, v19, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v21, s3
+; GFX8-NEXT: v_mov_b32_e32 v20, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NEXT: v_bfe_i32 v18, v18, 0, 1
+; GFX8-NEXT: v_bfe_i32 v17, v17, 0, 1
+; GFX8-NEXT: v_bfe_i32 v16, v16, 0, 1
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
+; GFX8-NEXT: v_bfe_i32 v15, v15, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v17, s3
+; GFX8-NEXT: v_bfe_i32 v14, v14, 0, 1
+; GFX8-NEXT: v_bfe_i32 v13, v13, 0, 1
+; GFX8-NEXT: v_bfe_i32 v12, v12, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v16, s2
+; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
+; GFX8-NEXT: s_add_u32 s2, s0, 0x70
+; GFX8-NEXT: v_mov_b32_e32 v13, s1
+; GFX8-NEXT: v_bfe_i32 v11, v11, 0, 1
+; GFX8-NEXT: v_bfe_i32 v10, v10, 0, 1
+; GFX8-NEXT: v_bfe_i32 v9, v9, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v8, s5
+; GFX8-NEXT: v_mov_b32_e32 v12, s0
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
+; GFX8-NEXT: s_add_u32 s0, s0, 0x60
+; GFX8-NEXT: v_mov_b32_e32 v9, s3
+; GFX8-NEXT: v_bfe_i32 v7, v7, 0, 1
+; GFX8-NEXT: v_bfe_i32 v6, v6, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v8, s2
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NEXT: v_bfe_i32 v3, v27, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: v_bfe_i32 v2, v26, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v32i1_to_v32i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @16, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @14
+; EG-NEXT: ALU 99, @17, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 5, @117, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T24.XYZW, T11.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T22.XYZW, T26.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T23.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T18.XYZW, T21.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T19.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T17.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T15.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T25.XYZW, T13.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 14:
+; EG-NEXT: VTX_READ_32 T11.X, T11.X, 0, #1
+; EG-NEXT: ALU clause starting at 16:
+; EG-NEXT: MOV * T11.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 17:
+; EG-NEXT: LSHR * T0.W, T11.X, literal.x,
+; EG-NEXT: 7(9.809089e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T12.W, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T11.X, literal.x,
+; EG-NEXT: 6(8.407791e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T12.Z, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T11.X, literal.x,
+; EG-NEXT: LSHR * T1.W, T11.X, literal.y,
+; EG-NEXT: 11(1.541428e-44), 5(7.006492e-45)
+; EG-NEXT: LSHR T13.X, KC0[2].Y, literal.x,
+; EG-NEXT: BFE_INT T12.Y, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T11.X, literal.y,
+; EG-NEXT: BFE_INT T14.W, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T11.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 10(1.401298e-44)
+; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T12.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T11.X, literal.x,
+; EG-NEXT: BFE_INT T14.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T11.X, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 15(2.101948e-44), 9(1.261169e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T15.X, PS, literal.x,
+; EG-NEXT: BFE_INT T14.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T11.X, literal.y,
+; EG-NEXT: BFE_INT T16.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T11.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 14(1.961818e-44)
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T14.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T11.X, literal.x,
+; EG-NEXT: BFE_INT T16.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T11.X, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 19(2.662467e-44), 13(1.821688e-44)
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T17.X, PS, literal.x,
+; EG-NEXT: BFE_INT T16.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T11.X, literal.y,
+; EG-NEXT: BFE_INT T18.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T11.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 18(2.522337e-44)
+; EG-NEXT: 12(1.681558e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T16.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T11.X, literal.x,
+; EG-NEXT: BFE_INT T18.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T11.X, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 23(3.222986e-44), 17(2.382207e-44)
+; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T19.X, PS, literal.x,
+; EG-NEXT: BFE_INT T18.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T11.X, literal.y,
+; EG-NEXT: BFE_INT T20.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T11.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 22(3.082857e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T18.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T11.X, literal.x,
+; EG-NEXT: BFE_INT T20.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T11.X, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 27(3.783506e-44), 21(2.942727e-44)
+; EG-NEXT: 64(8.968310e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T21.X, PS, literal.x,
+; EG-NEXT: BFE_INT T20.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T11.X, literal.y,
+; EG-NEXT: BFE_INT T22.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T11.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 26(3.643376e-44)
+; EG-NEXT: 20(2.802597e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T20.X, PS, 0.0, 1,
+; EG-NEXT: BFE_INT T22.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T11.X, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 25(3.503246e-44), 80(1.121039e-43)
+; EG-NEXT: LSHR T23.X, PS, literal.x,
+; EG-NEXT: BFE_INT T22.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T11.X, literal.y,
+; EG-NEXT: 2(2.802597e-45), 24(3.363116e-44)
+; EG-NEXT: BFE_INT T22.X, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T11.X, literal.x,
+; EG-NEXT: ASHR * T24.W, T11.X, literal.y,
+; EG-NEXT: 30(4.203895e-44), 31(4.344025e-44)
+; EG-NEXT: BFE_INT T25.X, T11.X, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T11.X, literal.x,
+; EG-NEXT: BFE_INT T24.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T11.X, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 3(4.203895e-45), 29(4.063766e-44)
+; EG-NEXT: 96(1.345247e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T26.X, PS, literal.x,
+; EG-NEXT: BFE_INT T24.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T11.X, literal.x,
+; EG-NEXT: BFE_INT T25.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T11.X, literal.y,
+; EG-NEXT: 2(2.802597e-45), 28(3.923636e-44)
+; EG-NEXT: BFE_INT T24.X, PS, 0.0, 1,
+; EG-NEXT: BFE_INT * T25.Z, PV.Z, 0.0, 1,
+; EG-NEXT: ALU clause starting at 117:
+; EG-NEXT: LSHR T0.W, T11.X, 1,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,
+; EG-NEXT: 112(1.569454e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T11.X, PS, literal.x,
+; EG-NEXT: BFE_INT * T25.Y, PV.W, 0.0, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <32 x i1>, ptr addrspace(4) %in
%ext = sext <32 x i1> %load to <32 x i32>
store <32 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v64i1_to_v64i32:
define amdgpu_kernel void @constant_zextload_v64i1_to_v64i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v64i1_to_v64i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_bfe_u32 s4, s2, 0x10003
+; GFX6-NEXT: s_bfe_u32 s5, s2, 0x10001
+; GFX6-NEXT: s_bfe_u32 s6, s2, 0x10007
+; GFX6-NEXT: s_bfe_u32 s7, s2, 0x10005
+; GFX6-NEXT: s_bfe_u32 s8, s2, 0x1000b
+; GFX6-NEXT: s_bfe_u32 s9, s2, 0x10009
+; GFX6-NEXT: s_bfe_u32 s10, s2, 0x1000f
+; GFX6-NEXT: s_bfe_u32 s11, s2, 0x1000d
+; GFX6-NEXT: s_bfe_u32 s12, s2, 0x10013
+; GFX6-NEXT: s_bfe_u32 s13, s2, 0x10011
+; GFX6-NEXT: s_bfe_u32 s14, s2, 0x10017
+; GFX6-NEXT: s_bfe_u32 s15, s2, 0x10015
+; GFX6-NEXT: s_bfe_u32 s16, s2, 0x1001b
+; GFX6-NEXT: s_bfe_u32 s17, s2, 0x10019
+; GFX6-NEXT: s_lshr_b32 s18, s2, 31
+; GFX6-NEXT: s_bfe_u32 s19, s2, 0x1001d
+; GFX6-NEXT: s_bfe_u32 s20, s3, 0x10003
+; GFX6-NEXT: s_bfe_u32 s21, s3, 0x10001
+; GFX6-NEXT: s_bfe_u32 s22, s3, 0x10007
+; GFX6-NEXT: s_bfe_u32 s23, s3, 0x10005
+; GFX6-NEXT: s_bfe_u32 s24, s3, 0x1000b
+; GFX6-NEXT: s_bfe_u32 s25, s3, 0x10009
+; GFX6-NEXT: s_bfe_u32 s26, s3, 0x1000f
+; GFX6-NEXT: s_bfe_u32 s27, s3, 0x1000d
+; GFX6-NEXT: s_bfe_u32 s28, s3, 0x10013
+; GFX6-NEXT: s_bfe_u32 s29, s3, 0x10011
+; GFX6-NEXT: s_bfe_u32 s30, s3, 0x10017
+; GFX6-NEXT: s_bfe_u32 s31, s3, 0x10015
+; GFX6-NEXT: s_bfe_u32 s33, s3, 0x1001b
+; GFX6-NEXT: s_bfe_u32 s34, s3, 0x10019
+; GFX6-NEXT: s_lshr_b32 s35, s3, 31
+; GFX6-NEXT: s_bfe_u32 s36, s3, 0x1001d
+; GFX6-NEXT: s_and_b32 s37, s2, 1
+; GFX6-NEXT: s_bfe_u32 s38, s2, 0x10002
+; GFX6-NEXT: s_bfe_u32 s39, s2, 0x10006
+; GFX6-NEXT: s_bfe_u32 s40, s2, 0x10004
+; GFX6-NEXT: s_bfe_u32 s41, s2, 0x1000a
+; GFX6-NEXT: s_bfe_u32 s42, s2, 0x10008
+; GFX6-NEXT: s_bfe_u32 s43, s2, 0x1000e
+; GFX6-NEXT: s_bfe_u32 s44, s2, 0x1000c
+; GFX6-NEXT: s_bfe_u32 s45, s2, 0x10012
+; GFX6-NEXT: s_bfe_u32 s46, s2, 0x10010
+; GFX6-NEXT: s_bfe_u32 s47, s2, 0x10016
+; GFX6-NEXT: s_bfe_u32 s48, s2, 0x10014
+; GFX6-NEXT: s_bfe_u32 s49, s2, 0x1001a
+; GFX6-NEXT: s_bfe_u32 s50, s2, 0x10018
+; GFX6-NEXT: s_bfe_u32 s51, s2, 0x1001e
+; GFX6-NEXT: s_bfe_u32 s52, s2, 0x1001c
+; GFX6-NEXT: s_and_b32 s53, s3, 1
+; GFX6-NEXT: s_bfe_u32 s54, s3, 0x10002
+; GFX6-NEXT: s_bfe_u32 s55, s3, 0x10006
+; GFX6-NEXT: s_bfe_u32 s56, s3, 0x10004
+; GFX6-NEXT: s_bfe_u32 s57, s3, 0x1000a
+; GFX6-NEXT: s_bfe_u32 s58, s3, 0x10008
+; GFX6-NEXT: s_bfe_u32 s59, s3, 0x1000e
+; GFX6-NEXT: s_bfe_u32 s60, s3, 0x10012
+; GFX6-NEXT: s_bfe_u32 s61, s3, 0x10010
+; GFX6-NEXT: s_bfe_u32 s62, s3, 0x10016
+; GFX6-NEXT: s_bfe_u32 s63, s3, 0x1001a
+; GFX6-NEXT: s_bfe_u32 s64, s3, 0x10018
+; GFX6-NEXT: s_bfe_u32 s65, s3, 0x1001e
+; GFX6-NEXT: s_bfe_u32 s66, s3, 0x1001c
+; GFX6-NEXT: s_bfe_u32 s67, s3, 0x10014
+; GFX6-NEXT: s_bfe_u32 s68, s3, 0x1000c
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mov_b32_e32 v0, s66
+; GFX6-NEXT: v_mov_b32_e32 v1, s36
+; GFX6-NEXT: v_mov_b32_e32 v2, s65
+; GFX6-NEXT: v_mov_b32_e32 v3, s35
+; GFX6-NEXT: v_mov_b32_e32 v4, s64
+; GFX6-NEXT: v_mov_b32_e32 v5, s34
+; GFX6-NEXT: v_mov_b32_e32 v6, s63
+; GFX6-NEXT: v_mov_b32_e32 v7, s33
+; GFX6-NEXT: v_mov_b32_e32 v8, s67
+; GFX6-NEXT: v_mov_b32_e32 v9, s31
+; GFX6-NEXT: v_mov_b32_e32 v10, s62
+; GFX6-NEXT: v_mov_b32_e32 v11, s30
+; GFX6-NEXT: v_mov_b32_e32 v12, s61
+; GFX6-NEXT: v_mov_b32_e32 v13, s29
+; GFX6-NEXT: v_mov_b32_e32 v14, s60
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:240
+; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:224
+; GFX6-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:208
+; GFX6-NEXT: v_mov_b32_e32 v15, s28
+; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:192
+; GFX6-NEXT: s_waitcnt expcnt(3)
+; GFX6-NEXT: v_mov_b32_e32 v0, s68
+; GFX6-NEXT: v_mov_b32_e32 v1, s27
+; GFX6-NEXT: v_mov_b32_e32 v2, s59
+; GFX6-NEXT: v_mov_b32_e32 v3, s26
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:176
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s58
+; GFX6-NEXT: v_mov_b32_e32 v1, s25
+; GFX6-NEXT: v_mov_b32_e32 v2, s57
+; GFX6-NEXT: v_mov_b32_e32 v3, s24
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:160
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s56
+; GFX6-NEXT: v_mov_b32_e32 v1, s23
+; GFX6-NEXT: v_mov_b32_e32 v2, s55
+; GFX6-NEXT: v_mov_b32_e32 v3, s22
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s53
+; GFX6-NEXT: v_mov_b32_e32 v1, s21
+; GFX6-NEXT: v_mov_b32_e32 v2, s54
+; GFX6-NEXT: v_mov_b32_e32 v3, s20
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s52
+; GFX6-NEXT: v_mov_b32_e32 v1, s19
+; GFX6-NEXT: v_mov_b32_e32 v2, s51
+; GFX6-NEXT: v_mov_b32_e32 v3, s18
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s50
+; GFX6-NEXT: v_mov_b32_e32 v1, s17
+; GFX6-NEXT: v_mov_b32_e32 v2, s49
+; GFX6-NEXT: v_mov_b32_e32 v3, s16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s48
+; GFX6-NEXT: v_mov_b32_e32 v1, s15
+; GFX6-NEXT: v_mov_b32_e32 v2, s47
+; GFX6-NEXT: v_mov_b32_e32 v3, s14
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s46
+; GFX6-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NEXT: v_mov_b32_e32 v2, s45
+; GFX6-NEXT: v_mov_b32_e32 v3, s12
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s44
+; GFX6-NEXT: v_mov_b32_e32 v1, s11
+; GFX6-NEXT: v_mov_b32_e32 v2, s43
+; GFX6-NEXT: v_mov_b32_e32 v3, s10
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s42
+; GFX6-NEXT: v_mov_b32_e32 v1, s9
+; GFX6-NEXT: v_mov_b32_e32 v2, s41
+; GFX6-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s40
+; GFX6-NEXT: v_mov_b32_e32 v1, s7
+; GFX6-NEXT: v_mov_b32_e32 v2, s39
+; GFX6-NEXT: v_mov_b32_e32 v3, s6
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s37
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: v_mov_b32_e32 v2, s38
+; GFX6-NEXT: v_mov_b32_e32 v3, s4
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v64i1_to_v64i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_lshr_b32 s5, s3, 24
+; GFX8-NEXT: s_lshr_b32 s7, s2, 24
+; GFX8-NEXT: s_bfe_u32 s4, s2, 0x10018
+; GFX8-NEXT: s_bfe_u32 s6, s3, 0x10018
+; GFX8-NEXT: s_and_b32 s10, s3, 1
+; GFX8-NEXT: s_and_b32 s11, s2, 1
+; GFX8-NEXT: s_bfe_u32 s12, s2, 0x10013
+; GFX8-NEXT: s_bfe_u32 s13, s2, 0x10012
+; GFX8-NEXT: s_bfe_u32 s14, s2, 0x10011
+; GFX8-NEXT: s_bfe_u32 s15, s2, 0x10010
+; GFX8-NEXT: s_bfe_u32 s16, s2, 0x10017
+; GFX8-NEXT: s_bfe_u32 s17, s2, 0x10016
+; GFX8-NEXT: s_bfe_u32 s18, s2, 0x10015
+; GFX8-NEXT: s_bfe_u32 s19, s2, 0x10014
+; GFX8-NEXT: s_bfe_u32 s20, s3, 0x10013
+; GFX8-NEXT: s_bfe_u32 s21, s3, 0x10012
+; GFX8-NEXT: s_bfe_u32 s22, s3, 0x10011
+; GFX8-NEXT: s_bfe_u32 s23, s3, 0x10010
+; GFX8-NEXT: s_bfe_u32 s8, s3, 0x10017
+; GFX8-NEXT: s_bfe_u32 s9, s3, 0x10016
+; GFX8-NEXT: s_bfe_u32 s24, s3, 0x10015
+; GFX8-NEXT: s_bfe_u32 s25, s3, 0x10014
+; GFX8-NEXT: v_mov_b32_e32 v25, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 0xd0
+; GFX8-NEXT: v_mov_b32_e32 v24, s9
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v27, s9
+; GFX8-NEXT: v_mov_b32_e32 v26, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 0xc0
+; GFX8-NEXT: v_mov_b32_e32 v22, s25
+; GFX8-NEXT: v_mov_b32_e32 v23, s24
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
+; GFX8-NEXT: v_mov_b32_e32 v27, s9
+; GFX8-NEXT: v_mov_b32_e32 v26, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 0x50
+; GFX8-NEXT: v_mov_b32_e32 v22, s23
+; GFX8-NEXT: v_mov_b32_e32 v23, s22
+; GFX8-NEXT: v_mov_b32_e32 v24, s21
+; GFX8-NEXT: v_mov_b32_e32 v25, s20
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
+; GFX8-NEXT: v_mov_b32_e32 v27, s9
+; GFX8-NEXT: v_mov_b32_e32 v26, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 64
+; GFX8-NEXT: v_mov_b32_e32 v22, s19
+; GFX8-NEXT: v_mov_b32_e32 v23, s18
+; GFX8-NEXT: v_mov_b32_e32 v24, s17
+; GFX8-NEXT: v_mov_b32_e32 v25, s16
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
+; GFX8-NEXT: v_mov_b32_e32 v27, s9
+; GFX8-NEXT: v_mov_b32_e32 v26, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 48
+; GFX8-NEXT: v_mov_b32_e32 v22, s15
+; GFX8-NEXT: v_mov_b32_e32 v23, s14
+; GFX8-NEXT: v_mov_b32_e32 v24, s13
+; GFX8-NEXT: v_mov_b32_e32 v25, s12
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 13, s2
+; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
+; GFX8-NEXT: v_lshrrev_b16_e64 v18, 12, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v22, 7, s3
+; GFX8-NEXT: v_mov_b32_e32 v25, s9
+; GFX8-NEXT: v_lshrrev_b16_e64 v20, 14, s2
+; GFX8-NEXT: v_and_b32_e32 v21, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v27, 1, v22
+; GFX8-NEXT: v_lshrrev_b16_e64 v22, 1, s3
+; GFX8-NEXT: v_mov_b32_e32 v24, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 32
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 9, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 11, s2
+; GFX8-NEXT: v_and_b32_e32 v28, 1, v22
+; GFX8-NEXT: v_and_b32_e32 v22, 1, v20
+; GFX8-NEXT: v_lshrrev_b16_e64 v23, 15, s2
+; GFX8-NEXT: v_and_b32_e32 v21, 0xffff, v21
+; GFX8-NEXT: v_and_b32_e32 v20, 1, v18
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v11, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v16, 10, s2
+; GFX8-NEXT: v_and_b32_e32 v17, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v19, 1, v2
+; GFX8-NEXT: flat_store_dwordx4 v[24:25], v[20:23]
+; GFX8-NEXT: v_lshrrev_b16_e64 v18, 3, s3
+; GFX8-NEXT: v_mov_b32_e32 v25, 1
+; GFX8-NEXT: v_mov_b32_e32 v21, s9
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 5, s2
+; GFX8-NEXT: v_and_b32_e32 v23, 1, v18
+; GFX8-NEXT: v_and_b32_e32 v19, 0xffff, v19
+; GFX8-NEXT: v_and_b32_e32 v18, 1, v16
+; GFX8-NEXT: v_and_b32_e32 v17, 0xffff, v17
+; GFX8-NEXT: v_and_b32_sdwa v16, v11, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v20, s8
+; GFX8-NEXT: v_lshrrev_b16_e64 v11, 5, s5
+; GFX8-NEXT: v_and_b32_e32 v12, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 7, s2
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
+; GFX8-NEXT: v_and_b32_e32 v20, 1, v11
+; GFX8-NEXT: v_lshrrev_b16_e64 v11, 1, s5
+; GFX8-NEXT: s_add_u32 s8, s0, 16
+; GFX8-NEXT: v_and_b32_e32 v15, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 1, s2
+; GFX8-NEXT: v_and_b32_e32 v18, 1, v11
+; GFX8-NEXT: v_lshrrev_b16_e64 v11, 3, s5
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 4, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v14, 6, s2
+; GFX8-NEXT: v_and_b32_e32 v7, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 3, s2
+; GFX8-NEXT: v_and_b32_e32 v17, 0xffff, v15
+; GFX8-NEXT: v_and_b32_e32 v21, 1, v11
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff, v12
+; GFX8-NEXT: v_mov_b32_e32 v12, s9
+; GFX8-NEXT: v_and_b32_e32 v13, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v16, 1, v14
+; GFX8-NEXT: v_and_b32_e32 v14, 1, v9
+; GFX8-NEXT: v_mov_b32_e32 v11, s8
+; GFX8-NEXT: v_lshrrev_b16_e64 v10, 2, s2
+; GFX8-NEXT: flat_store_dwordx4 v[11:12], v[14:17]
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 5, s7
+; GFX8-NEXT: v_and_b32_e32 v12, 0xffff, v13
+; GFX8-NEXT: v_mov_b32_e32 v14, s1
+; GFX8-NEXT: s_add_u32 s8, s0, 0xb0
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 13, s3
+; GFX8-NEXT: v_and_b32_e32 v16, 1, v9
+; GFX8-NEXT: v_and_b32_e32 v11, 1, v10
+; GFX8-NEXT: v_and_b32_e32 v10, 0xffff, v7
+; GFX8-NEXT: v_mov_b32_e32 v9, s11
+; GFX8-NEXT: v_mov_b32_e32 v13, s0
+; GFX8-NEXT: v_lshrrev_b16_e64 v7, 1, s7
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v5, 12, s3
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e64 v8, 14, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 9, s3
+; GFX8-NEXT: flat_store_dwordx4 v[13:14], v[9:12]
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v11, 1, v7
+; GFX8-NEXT: v_lshrrev_b16_e64 v7, 3, s7
+; GFX8-NEXT: v_mov_b32_e32 v10, s9
+; GFX8-NEXT: v_lshrrev_b16_e64 v17, 6, s7
+; GFX8-NEXT: v_and_b32_e32 v13, 1, v7
+; GFX8-NEXT: v_and_b32_e32 v7, 1, v8
+; GFX8-NEXT: v_lshrrev_b16_e64 v8, 15, s3
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX8-NEXT: v_and_b32_e32 v5, 1, v5
+; GFX8-NEXT: v_mov_b32_e32 v9, s8
+; GFX8-NEXT: v_lshrrev_b16_e64 v3, 10, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 11, s3
+; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[5:8]
+; GFX8-NEXT: v_and_b32_e32 v10, 1, v17
+; GFX8-NEXT: v_and_b32_e32 v17, 0xffff, v2
+; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0xa0
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 4, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 5, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v26, 6, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v22, 2, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v19, 2, s5
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff, v13
+; GFX8-NEXT: v_and_b32_e32 v9, 0xffff, v16
+; GFX8-NEXT: v_and_b32_e32 v13, 0xffff, v18
+; GFX8-NEXT: v_and_b32_e32 v18, 1, v3
+; GFX8-NEXT: v_and_b32_sdwa v16, v2, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v15, 4, s7
+; GFX8-NEXT: v_and_b32_e32 v14, 1, v19
+; GFX8-NEXT: v_and_b32_e32 v19, 0xffff, v4
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0x90
+; GFX8-NEXT: v_and_b32_e32 v8, 1, v15
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff, v21
+; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[16:19]
+; GFX8-NEXT: v_and_b32_e32 v21, 0xffff, v1
+; GFX8-NEXT: v_and_b32_e32 v17, 0xffff, v20
+; GFX8-NEXT: v_and_b32_e32 v20, 1, v0
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v4, 6, s5
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0x80
+; GFX8-NEXT: v_and_b32_e32 v18, 1, v4
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v23
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v22
+; GFX8-NEXT: v_and_b32_e32 v23, 0xffff, v27
+; GFX8-NEXT: v_and_b32_e32 v22, 1, v26
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[20:23]
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v28
+; GFX8-NEXT: v_mov_b32_e32 v21, s3
+; GFX8-NEXT: v_mov_b32_e32 v1, s10
+; GFX8-NEXT: v_mov_b32_e32 v20, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 0xf0
+; GFX8-NEXT: v_lshrrev_b16_e64 v24, 4, s5
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[1:4]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v19, 7, s5
+; GFX8-NEXT: v_and_b32_e32 v16, 1, v24
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0xe0
+; GFX8-NEXT: v_lshrrev_b16_e64 v12, 2, s7
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v12
+; GFX8-NEXT: v_mov_b32_e32 v12, s6
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0x70
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff, v11
+; GFX8-NEXT: v_lshrrev_b16_e64 v11, 7, s7
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: s_add_u32 s0, s0, 0x60
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v64i1_to_v64i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @24, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @22
+; EG-NEXT: ALU 96, @25, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 57, @122, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T48.XYZW, T50.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T46.XYZW, T49.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T44.XYZW, T47.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T42.XYZW, T45.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T40.XYZW, T43.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T38.XYZW, T41.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T36.XYZW, T39.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T35.XYZW, T37.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T33.XYZW, T20.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T31.XYZW, T34.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T29.XYZW, T32.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T27.XYZW, T30.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T25.XYZW, T28.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T23.XYZW, T26.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T21.XYZW, T24.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T22.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 22:
+; EG-NEXT: VTX_READ_64 T20.XY, T19.X, 0, #1
+; EG-NEXT: ALU clause starting at 24:
+; EG-NEXT: MOV * T19.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 25:
+; EG-NEXT: BFE_UINT * T19.W, T20.X, literal.x, 1,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T19.Z, T20.X, literal.x, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T19.Y, T20.X, 1, 1,
+; EG-NEXT: BFE_UINT * T21.W, T20.X, literal.x, 1,
+; EG-NEXT: 7(9.809089e-45), 0(0.000000e+00)
+; EG-NEXT: AND_INT T19.X, T20.X, 1,
+; EG-NEXT: BFE_UINT T21.Z, T20.X, literal.x, 1,
+; EG-NEXT: LSHR * T22.X, KC0[2].Y, literal.y,
+; EG-NEXT: 6(8.407791e-45), 2(2.802597e-45)
+; EG-NEXT: BFE_UINT T21.Y, T20.X, literal.x, 1,
+; EG-NEXT: BFE_UINT * T23.W, T20.X, literal.y, 1,
+; EG-NEXT: 5(7.006492e-45), 11(1.541428e-44)
+; EG-NEXT: BFE_UINT T21.X, T20.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T23.Z, T20.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 4(5.605194e-45), 10(1.401298e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T24.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T23.Y, T20.X, literal.y, 1,
+; EG-NEXT: BFE_UINT * T25.W, T20.X, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 9(1.261169e-44)
+; EG-NEXT: 15(2.101948e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T23.X, T20.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T25.Z, T20.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 8(1.121039e-44), 14(1.961818e-44)
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T26.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T25.Y, T20.X, literal.y, 1,
+; EG-NEXT: BFE_UINT * T27.W, T20.X, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 13(1.821688e-44)
+; EG-NEXT: 19(2.662467e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T25.X, T20.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T27.Z, T20.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 12(1.681558e-44), 18(2.522337e-44)
+; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T28.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T27.Y, T20.X, literal.y, 1,
+; EG-NEXT: BFE_UINT * T29.W, T20.X, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 17(2.382207e-44)
+; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T27.X, T20.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T29.Z, T20.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 16(2.242078e-44), 22(3.082857e-44)
+; EG-NEXT: 64(8.968310e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T30.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T29.Y, T20.X, literal.y, 1,
+; EG-NEXT: BFE_UINT * T31.W, T20.X, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 21(2.942727e-44)
+; EG-NEXT: 27(3.783506e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T29.X, T20.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T31.Z, T20.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 20(2.802597e-44), 26(3.643376e-44)
+; EG-NEXT: 80(1.121039e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T32.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T31.Y, T20.X, literal.y, 1,
+; EG-NEXT: LSHR * T33.W, T20.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 25(3.503246e-44)
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T31.X, T20.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T33.Z, T20.X, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 24(3.363116e-44), 30(4.203895e-44)
+; EG-NEXT: 96(1.345247e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T34.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T33.Y, T20.X, literal.y, 1,
+; EG-NEXT: BFE_UINT * T35.W, T20.Y, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 29(4.063766e-44)
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T33.X, T20.X, literal.x, 1,
+; EG-NEXT: BFE_UINT T35.Z, T20.Y, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 28(3.923636e-44), 2(2.802597e-45)
+; EG-NEXT: 112(1.569454e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T20.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T35.Y, T20.Y, 1, 1,
+; EG-NEXT: BFE_UINT T36.W, T20.Y, literal.y, 1,
+; EG-NEXT: AND_INT * T35.X, T20.Y, 1,
+; EG-NEXT: 2(2.802597e-45), 7(9.809089e-45)
+; EG-NEXT: BFE_UINT T36.Z, T20.Y, literal.x, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 6(8.407791e-45), 128(1.793662e-43)
+; EG-NEXT: LSHR T37.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T36.Y, T20.Y, literal.y, 1,
+; EG-NEXT: BFE_UINT * T38.W, T20.Y, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 5(7.006492e-45)
+; EG-NEXT: 11(1.541428e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T36.X, T20.Y, literal.x, 1,
+; EG-NEXT: BFE_UINT T38.Z, T20.Y, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 4(5.605194e-45), 10(1.401298e-44)
+; EG-NEXT: 144(2.017870e-43), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 122:
+; EG-NEXT: LSHR T39.X, T0.W, literal.x,
+; EG-NEXT: BFE_UINT T38.Y, T20.Y, literal.y, 1,
+; EG-NEXT: BFE_UINT * T40.W, T20.Y, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 9(1.261169e-44)
+; EG-NEXT: 15(2.101948e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T38.X, T20.Y, literal.x, 1,
+; EG-NEXT: BFE_UINT T40.Z, T20.Y, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 8(1.121039e-44), 14(1.961818e-44)
+; EG-NEXT: 160(2.242078e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T41.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T40.Y, T20.Y, literal.y, 1,
+; EG-NEXT: BFE_UINT * T42.W, T20.Y, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 13(1.821688e-44)
+; EG-NEXT: 19(2.662467e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T40.X, T20.Y, literal.x, 1,
+; EG-NEXT: BFE_UINT T42.Z, T20.Y, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 12(1.681558e-44), 18(2.522337e-44)
+; EG-NEXT: 176(2.466285e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T43.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T42.Y, T20.Y, literal.y, 1,
+; EG-NEXT: BFE_UINT * T44.W, T20.Y, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 17(2.382207e-44)
+; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T42.X, T20.Y, literal.x, 1,
+; EG-NEXT: BFE_UINT T44.Z, T20.Y, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 16(2.242078e-44), 22(3.082857e-44)
+; EG-NEXT: 192(2.690493e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T45.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T44.Y, T20.Y, literal.y, 1,
+; EG-NEXT: BFE_UINT * T46.W, T20.Y, literal.z, 1,
+; EG-NEXT: 2(2.802597e-45), 21(2.942727e-44)
+; EG-NEXT: 27(3.783506e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T44.X, T20.Y, literal.x, 1,
+; EG-NEXT: BFE_UINT T46.Z, T20.Y, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 20(2.802597e-44), 26(3.643376e-44)
+; EG-NEXT: 208(2.914701e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T47.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T46.Y, T20.Y, literal.y, 1,
+; EG-NEXT: LSHR * T48.W, T20.Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 25(3.503246e-44)
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T46.X, T20.Y, literal.x, 1,
+; EG-NEXT: BFE_UINT T48.Z, T20.Y, literal.y, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 24(3.363116e-44), 30(4.203895e-44)
+; EG-NEXT: 224(3.138909e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T49.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT * T48.Y, T20.Y, literal.y, 1,
+; EG-NEXT: 2(2.802597e-45), 29(4.063766e-44)
+; EG-NEXT: BFE_UINT T48.X, T20.Y, literal.x, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 28(3.923636e-44), 240(3.363116e-43)
+; EG-NEXT: LSHR * T50.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <64 x i1>, ptr addrspace(4) %in
%ext = zext <64 x i1> %load to <64 x i32>
store <64 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v64i1_to_v64i32:
define amdgpu_kernel void @constant_sextload_v64i1_to_v64i32(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v64i1_to_v64i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_bfe_i32 s4, s2, 0x10003
+; GFX6-NEXT: s_bfe_i32 s5, s2, 0x10002
+; GFX6-NEXT: s_bfe_i32 s6, s2, 0x10001
+; GFX6-NEXT: s_bfe_i32 s7, s2, 0x10000
+; GFX6-NEXT: s_bfe_i32 s8, s2, 0x10007
+; GFX6-NEXT: s_bfe_i32 s9, s2, 0x10006
+; GFX6-NEXT: s_bfe_i32 s10, s2, 0x10005
+; GFX6-NEXT: s_bfe_i32 s11, s2, 0x10004
+; GFX6-NEXT: s_bfe_i32 s12, s2, 0x1000b
+; GFX6-NEXT: s_bfe_i32 s13, s2, 0x1000a
+; GFX6-NEXT: s_bfe_i32 s14, s2, 0x10009
+; GFX6-NEXT: s_bfe_i32 s15, s2, 0x10008
+; GFX6-NEXT: s_bfe_i32 s16, s2, 0x1000f
+; GFX6-NEXT: s_bfe_i32 s17, s2, 0x1000e
+; GFX6-NEXT: s_bfe_i32 s18, s2, 0x1000d
+; GFX6-NEXT: s_bfe_i32 s19, s2, 0x1000c
+; GFX6-NEXT: s_bfe_i32 s20, s2, 0x10013
+; GFX6-NEXT: s_bfe_i32 s21, s2, 0x10012
+; GFX6-NEXT: s_bfe_i32 s22, s2, 0x10011
+; GFX6-NEXT: s_bfe_i32 s23, s2, 0x10010
+; GFX6-NEXT: s_bfe_i32 s24, s2, 0x10017
+; GFX6-NEXT: s_bfe_i32 s25, s2, 0x10016
+; GFX6-NEXT: s_bfe_i32 s26, s2, 0x10015
+; GFX6-NEXT: s_bfe_i32 s27, s2, 0x10014
+; GFX6-NEXT: s_bfe_i32 s28, s2, 0x1001b
+; GFX6-NEXT: s_bfe_i32 s29, s2, 0x1001a
+; GFX6-NEXT: s_bfe_i32 s30, s2, 0x10019
+; GFX6-NEXT: s_bfe_i32 s31, s2, 0x10018
+; GFX6-NEXT: s_ashr_i32 s33, s2, 31
+; GFX6-NEXT: s_bfe_i32 s34, s2, 0x1001e
+; GFX6-NEXT: s_bfe_i32 s35, s2, 0x1001d
+; GFX6-NEXT: s_bfe_i32 s36, s2, 0x1001c
+; GFX6-NEXT: s_bfe_i32 s37, s3, 0x10003
+; GFX6-NEXT: s_bfe_i32 s38, s3, 0x10002
+; GFX6-NEXT: s_bfe_i32 s39, s3, 0x10001
+; GFX6-NEXT: s_bfe_i32 s40, s3, 0x10000
+; GFX6-NEXT: s_bfe_i32 s41, s3, 0x10007
+; GFX6-NEXT: s_bfe_i32 s42, s3, 0x10006
+; GFX6-NEXT: s_bfe_i32 s43, s3, 0x10005
+; GFX6-NEXT: s_bfe_i32 s44, s3, 0x10004
+; GFX6-NEXT: s_bfe_i32 s45, s3, 0x1000b
+; GFX6-NEXT: s_bfe_i32 s46, s3, 0x1000a
+; GFX6-NEXT: s_bfe_i32 s47, s3, 0x10009
+; GFX6-NEXT: s_bfe_i32 s48, s3, 0x10008
+; GFX6-NEXT: s_bfe_i32 s49, s3, 0x1000f
+; GFX6-NEXT: s_bfe_i32 s50, s3, 0x1000e
+; GFX6-NEXT: s_bfe_i32 s51, s3, 0x1000d
+; GFX6-NEXT: s_bfe_i32 s52, s3, 0x1000c
+; GFX6-NEXT: s_bfe_i32 s53, s3, 0x10012
+; GFX6-NEXT: s_bfe_i32 s54, s3, 0x10011
+; GFX6-NEXT: s_bfe_i32 s55, s3, 0x10010
+; GFX6-NEXT: s_bfe_i32 s56, s3, 0x10017
+; GFX6-NEXT: s_bfe_i32 s57, s3, 0x10016
+; GFX6-NEXT: s_bfe_i32 s58, s3, 0x10015
+; GFX6-NEXT: s_bfe_i32 s59, s3, 0x1001b
+; GFX6-NEXT: s_bfe_i32 s60, s3, 0x1001a
+; GFX6-NEXT: s_bfe_i32 s61, s3, 0x10019
+; GFX6-NEXT: s_bfe_i32 s62, s3, 0x10018
+; GFX6-NEXT: s_ashr_i32 s63, s3, 31
+; GFX6-NEXT: s_bfe_i32 s64, s3, 0x1001e
+; GFX6-NEXT: s_bfe_i32 s65, s3, 0x1001d
+; GFX6-NEXT: s_bfe_i32 s66, s3, 0x1001c
+; GFX6-NEXT: s_bfe_i32 s67, s3, 0x10014
+; GFX6-NEXT: s_bfe_i32 s68, s3, 0x10013
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mov_b32_e32 v0, s66
+; GFX6-NEXT: v_mov_b32_e32 v1, s65
+; GFX6-NEXT: v_mov_b32_e32 v2, s64
+; GFX6-NEXT: v_mov_b32_e32 v3, s63
+; GFX6-NEXT: v_mov_b32_e32 v4, s62
+; GFX6-NEXT: v_mov_b32_e32 v5, s61
+; GFX6-NEXT: v_mov_b32_e32 v6, s60
+; GFX6-NEXT: v_mov_b32_e32 v7, s59
+; GFX6-NEXT: v_mov_b32_e32 v8, s67
+; GFX6-NEXT: v_mov_b32_e32 v9, s58
+; GFX6-NEXT: v_mov_b32_e32 v10, s57
+; GFX6-NEXT: v_mov_b32_e32 v11, s56
+; GFX6-NEXT: v_mov_b32_e32 v12, s55
+; GFX6-NEXT: v_mov_b32_e32 v13, s54
+; GFX6-NEXT: v_mov_b32_e32 v14, s53
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:240
+; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:224
+; GFX6-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:208
+; GFX6-NEXT: v_mov_b32_e32 v15, s68
+; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:192
+; GFX6-NEXT: s_waitcnt expcnt(3)
+; GFX6-NEXT: v_mov_b32_e32 v0, s52
+; GFX6-NEXT: v_mov_b32_e32 v1, s51
+; GFX6-NEXT: v_mov_b32_e32 v2, s50
+; GFX6-NEXT: v_mov_b32_e32 v3, s49
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:176
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s48
+; GFX6-NEXT: v_mov_b32_e32 v1, s47
+; GFX6-NEXT: v_mov_b32_e32 v2, s46
+; GFX6-NEXT: v_mov_b32_e32 v3, s45
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:160
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s44
+; GFX6-NEXT: v_mov_b32_e32 v1, s43
+; GFX6-NEXT: v_mov_b32_e32 v2, s42
+; GFX6-NEXT: v_mov_b32_e32 v3, s41
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s40
+; GFX6-NEXT: v_mov_b32_e32 v1, s39
+; GFX6-NEXT: v_mov_b32_e32 v2, s38
+; GFX6-NEXT: v_mov_b32_e32 v3, s37
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s36
+; GFX6-NEXT: v_mov_b32_e32 v1, s35
+; GFX6-NEXT: v_mov_b32_e32 v2, s34
+; GFX6-NEXT: v_mov_b32_e32 v3, s33
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s31
+; GFX6-NEXT: v_mov_b32_e32 v1, s30
+; GFX6-NEXT: v_mov_b32_e32 v2, s29
+; GFX6-NEXT: v_mov_b32_e32 v3, s28
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s27
+; GFX6-NEXT: v_mov_b32_e32 v1, s26
+; GFX6-NEXT: v_mov_b32_e32 v2, s25
+; GFX6-NEXT: v_mov_b32_e32 v3, s24
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s23
+; GFX6-NEXT: v_mov_b32_e32 v1, s22
+; GFX6-NEXT: v_mov_b32_e32 v2, s21
+; GFX6-NEXT: v_mov_b32_e32 v3, s20
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s19
+; GFX6-NEXT: v_mov_b32_e32 v1, s18
+; GFX6-NEXT: v_mov_b32_e32 v2, s17
+; GFX6-NEXT: v_mov_b32_e32 v3, s16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s15
+; GFX6-NEXT: v_mov_b32_e32 v1, s14
+; GFX6-NEXT: v_mov_b32_e32 v2, s13
+; GFX6-NEXT: v_mov_b32_e32 v3, s12
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s11
+; GFX6-NEXT: v_mov_b32_e32 v1, s10
+; GFX6-NEXT: v_mov_b32_e32 v2, s9
+; GFX6-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s7
+; GFX6-NEXT: v_mov_b32_e32 v1, s6
+; GFX6-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NEXT: v_mov_b32_e32 v3, s4
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v64i1_to_v64i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e64 v18, 12, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v19, 13, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v20, 14, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v21, 15, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v14, 8, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v15, 9, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v16, 10, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v17, 11, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v10, 4, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v11, 5, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v12, 6, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v13, 7, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v6, 1, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v8, 2, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 3, s2
+; GFX8-NEXT: s_lshr_b32 s6, s3, 24
+; GFX8-NEXT: s_lshr_b32 s7, s2, 24
+; GFX8-NEXT: s_bfe_i32 s4, s2, 0x10018
+; GFX8-NEXT: s_bfe_i32 s5, s3, 0x10018
+; GFX8-NEXT: s_bfe_i32 s10, s3, 0x10000
+; GFX8-NEXT: s_bfe_i32 s11, s2, 0x10000
+; GFX8-NEXT: s_bfe_i32 s12, s2, 0x10013
+; GFX8-NEXT: s_bfe_i32 s13, s2, 0x10012
+; GFX8-NEXT: s_bfe_i32 s14, s2, 0x10011
+; GFX8-NEXT: s_bfe_i32 s15, s2, 0x10010
+; GFX8-NEXT: s_bfe_i32 s16, s2, 0x10017
+; GFX8-NEXT: s_bfe_i32 s17, s2, 0x10016
+; GFX8-NEXT: s_bfe_i32 s18, s2, 0x10015
+; GFX8-NEXT: s_bfe_i32 s2, s2, 0x10014
+; GFX8-NEXT: s_bfe_i32 s19, s3, 0x10013
+; GFX8-NEXT: s_bfe_i32 s20, s3, 0x10012
+; GFX8-NEXT: s_bfe_i32 s21, s3, 0x10011
+; GFX8-NEXT: s_bfe_i32 s22, s3, 0x10010
+; GFX8-NEXT: s_bfe_i32 s8, s3, 0x10017
+; GFX8-NEXT: s_bfe_i32 s9, s3, 0x10016
+; GFX8-NEXT: s_bfe_i32 s23, s3, 0x10015
+; GFX8-NEXT: s_bfe_i32 s24, s3, 0x10014
+; GFX8-NEXT: v_mov_b32_e32 v25, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 0xd0
+; GFX8-NEXT: v_mov_b32_e32 v24, s9
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v27, s9
+; GFX8-NEXT: v_mov_b32_e32 v26, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 0xc0
+; GFX8-NEXT: v_mov_b32_e32 v22, s24
+; GFX8-NEXT: v_mov_b32_e32 v23, s23
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
+; GFX8-NEXT: v_mov_b32_e32 v27, s9
+; GFX8-NEXT: v_mov_b32_e32 v26, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 0x50
+; GFX8-NEXT: v_mov_b32_e32 v22, s22
+; GFX8-NEXT: v_mov_b32_e32 v23, s21
+; GFX8-NEXT: v_mov_b32_e32 v24, s20
+; GFX8-NEXT: v_mov_b32_e32 v25, s19
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
+; GFX8-NEXT: v_mov_b32_e32 v27, s9
+; GFX8-NEXT: v_mov_b32_e32 v26, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 64
+; GFX8-NEXT: v_mov_b32_e32 v22, s2
+; GFX8-NEXT: v_mov_b32_e32 v23, s18
+; GFX8-NEXT: v_mov_b32_e32 v24, s17
+; GFX8-NEXT: v_mov_b32_e32 v25, s16
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
+; GFX8-NEXT: v_mov_b32_e32 v27, s9
+; GFX8-NEXT: v_mov_b32_e32 v26, s8
+; GFX8-NEXT: s_add_u32 s8, s0, 48
+; GFX8-NEXT: v_mov_b32_e32 v22, s15
+; GFX8-NEXT: v_mov_b32_e32 v23, s14
+; GFX8-NEXT: v_mov_b32_e32 v24, s13
+; GFX8-NEXT: v_mov_b32_e32 v25, s12
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[26:27], v[22:25]
+; GFX8-NEXT: v_bfe_i32 v21, v21, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v23, s9
+; GFX8-NEXT: v_bfe_i32 v20, v20, 0, 1
+; GFX8-NEXT: v_bfe_i32 v19, v19, 0, 1
+; GFX8-NEXT: v_bfe_i32 v18, v18, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v22, s8
+; GFX8-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NEXT: v_lshrrev_b16_e64 v3, 12, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v4, 13, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v5, 14, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v7, 15, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 8, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 9, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 10, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v24, 11, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v26, 4, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v27, 5, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v28, 6, s3
+; GFX8-NEXT: flat_store_dwordx4 v[22:23], v[18:21]
+; GFX8-NEXT: v_lshrrev_b16_e64 v22, 7, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v23, 1, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v20, 2, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v21, 3, s3
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v19, s3
+; GFX8-NEXT: v_mov_b32_e32 v18, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NEXT: v_bfe_i32 v17, v17, 0, 1
+; GFX8-NEXT: v_bfe_i32 v16, v16, 0, 1
+; GFX8-NEXT: v_bfe_i32 v15, v15, 0, 1
+; GFX8-NEXT: v_bfe_i32 v14, v14, 0, 1
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[14:17]
+; GFX8-NEXT: v_bfe_i32 v13, v13, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v15, s3
+; GFX8-NEXT: v_bfe_i32 v12, v12, 0, 1
+; GFX8-NEXT: v_bfe_i32 v11, v11, 0, 1
+; GFX8-NEXT: v_bfe_i32 v10, v10, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v14, s2
+; GFX8-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NEXT: s_add_u32 s2, s0, 0xb0
+; GFX8-NEXT: v_mov_b32_e32 v13, s1
+; GFX8-NEXT: v_bfe_i32 v11, v9, 0, 1
+; GFX8-NEXT: v_bfe_i32 v10, v8, 0, 1
+; GFX8-NEXT: v_bfe_i32 v9, v6, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v8, s11
+; GFX8-NEXT: v_mov_b32_e32 v12, s0
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
+; GFX8-NEXT: v_bfe_i32 v6, v7, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v8, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v10, 5, s7
+; GFX8-NEXT: v_lshrrev_b16_e64 v11, 6, s7
+; GFX8-NEXT: v_bfe_i32 v5, v5, 0, 1
+; GFX8-NEXT: v_bfe_i32 v4, v4, 0, 1
+; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v7, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 0xa0
+; GFX8-NEXT: v_lshrrev_b16_e64 v12, 1, s7
+; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[3:6]
+; GFX8-NEXT: v_bfe_i32 v8, v11, 0, 1
+; GFX8-NEXT: v_lshrrev_b16_e64 v3, 2, s7
+; GFX8-NEXT: v_lshrrev_b16_e64 v4, 3, s7
+; GFX8-NEXT: v_bfe_i32 v7, v10, 0, 1
+; GFX8-NEXT: v_bfe_i32 v11, v1, 0, 1
+; GFX8-NEXT: v_bfe_i32 v10, v0, 0, 1
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_bfe_i32 v5, v4, 0, 1
+; GFX8-NEXT: v_bfe_i32 v4, v3, 0, 1
+; GFX8-NEXT: v_bfe_i32 v3, v12, 0, 1
+; GFX8-NEXT: v_bfe_i32 v13, v24, 0, 1
+; GFX8-NEXT: v_bfe_i32 v12, v2, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0x90
+; GFX8-NEXT: v_lshrrev_b16_e64 v19, 5, s6
+; GFX8-NEXT: v_lshrrev_b16_e64 v15, 2, s6
+; GFX8-NEXT: v_lshrrev_b16_e64 v25, 4, s7
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[10:13]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_bfe_i32 v6, v25, 0, 1
+; GFX8-NEXT: v_bfe_i32 v12, v15, 0, 1
+; GFX8-NEXT: v_bfe_i32 v15, v19, 0, 1
+; GFX8-NEXT: v_bfe_i32 v19, v23, 0, 1
+; GFX8-NEXT: v_bfe_i32 v25, v22, 0, 1
+; GFX8-NEXT: v_bfe_i32 v24, v28, 0, 1
+; GFX8-NEXT: v_bfe_i32 v23, v27, 0, 1
+; GFX8-NEXT: v_bfe_i32 v22, v26, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0x80
+; GFX8-NEXT: v_lshrrev_b16_e64 v18, 4, s6
+; GFX8-NEXT: v_lshrrev_b16_e64 v14, 1, s6
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[22:25]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_bfe_i32 v11, v14, 0, 1
+; GFX8-NEXT: v_bfe_i32 v14, v18, 0, 1
+; GFX8-NEXT: v_bfe_i32 v21, v21, 0, 1
+; GFX8-NEXT: v_bfe_i32 v20, v20, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v18, s10
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0xf0
+; GFX8-NEXT: v_lshrrev_b16_e64 v16, 6, s6
+; GFX8-NEXT: v_lshrrev_b16_e64 v17, 7, s6
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[18:21]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_bfe_i32 v17, v17, 0, 1
+; GFX8-NEXT: v_bfe_i32 v16, v16, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0xe0
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 3, s6
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[14:17]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_bfe_i32 v13, v2, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v10, s5
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0x70
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 7, s7
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[10:13]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_bfe_i32 v9, v9, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: s_add_u32 s0, s0, 0x60
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[6:9]
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[2:5]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v64i1_to_v64i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @24, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @22
+; EG-NEXT: ALU 99, @25, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 98, @125, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 13, @224, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T48.XYZW, T50.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T45.XYZW, T49.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T43.XYZW, T46.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T41.XYZW, T44.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T39.XYZW, T42.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T37.XYZW, T40.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T34.XYZW, T38.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T36.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T32.XYZW, T35.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T30.XYZW, T33.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T28.XYZW, T31.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T26.XYZW, T29.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T24.XYZW, T27.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T22.XYZW, T25.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T23.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T47.XYZW, T21.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 22:
+; EG-NEXT: VTX_READ_64 T19.XY, T19.X, 0, #1
+; EG-NEXT: ALU clause starting at 24:
+; EG-NEXT: MOV * T19.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 25:
+; EG-NEXT: LSHR * T0.W, T19.X, literal.x,
+; EG-NEXT: 7(9.809089e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T20.W, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T19.X, literal.x,
+; EG-NEXT: 6(8.407791e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T20.Z, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.X, literal.x,
+; EG-NEXT: LSHR * T1.W, T19.X, literal.y,
+; EG-NEXT: 11(1.541428e-44), 5(7.006492e-45)
+; EG-NEXT: LSHR T21.X, KC0[2].Y, literal.x,
+; EG-NEXT: BFE_INT T20.Y, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.X, literal.y,
+; EG-NEXT: BFE_INT T22.W, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T19.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 10(1.401298e-44)
+; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T20.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T19.X, literal.x,
+; EG-NEXT: BFE_INT T22.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.X, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 15(2.101948e-44), 9(1.261169e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T23.X, PS, literal.x,
+; EG-NEXT: BFE_INT T22.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.X, literal.y,
+; EG-NEXT: BFE_INT T24.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T19.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 14(1.961818e-44)
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T22.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T19.X, literal.x,
+; EG-NEXT: BFE_INT T24.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.X, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 19(2.662467e-44), 13(1.821688e-44)
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T25.X, PS, literal.x,
+; EG-NEXT: BFE_INT T24.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.X, literal.y,
+; EG-NEXT: BFE_INT T26.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T19.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 18(2.522337e-44)
+; EG-NEXT: 12(1.681558e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T24.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T19.X, literal.x,
+; EG-NEXT: BFE_INT T26.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.X, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 23(3.222986e-44), 17(2.382207e-44)
+; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T27.X, PS, literal.x,
+; EG-NEXT: BFE_INT T26.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.X, literal.y,
+; EG-NEXT: BFE_INT T28.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T19.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 22(3.082857e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T26.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T19.X, literal.x,
+; EG-NEXT: BFE_INT T28.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.X, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 27(3.783506e-44), 21(2.942727e-44)
+; EG-NEXT: 64(8.968310e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T29.X, PS, literal.x,
+; EG-NEXT: BFE_INT T28.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.X, literal.y,
+; EG-NEXT: BFE_INT T30.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T19.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 26(3.643376e-44)
+; EG-NEXT: 20(2.802597e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T28.X, PS, 0.0, 1,
+; EG-NEXT: BFE_INT T30.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.X, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 25(3.503246e-44), 80(1.121039e-43)
+; EG-NEXT: LSHR T31.X, PS, literal.x,
+; EG-NEXT: BFE_INT T30.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.X, literal.y,
+; EG-NEXT: LSHR T0.W, T19.X, literal.z,
+; EG-NEXT: ASHR * T32.W, T19.X, literal.w,
+; EG-NEXT: 2(2.802597e-45), 30(4.203895e-44)
+; EG-NEXT: 24(3.363116e-44), 31(4.344025e-44)
+; EG-NEXT: BFE_INT T30.X, PV.W, 0.0, 1,
+; EG-NEXT: BFE_INT T32.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.X, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 29(4.063766e-44), 96(1.345247e-43)
+; EG-NEXT: LSHR T33.X, PS, literal.x,
+; EG-NEXT: BFE_INT T32.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.Y, literal.y,
+; EG-NEXT: LSHR * T1.W, T19.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 7(9.809089e-45)
+; EG-NEXT: 28(3.923636e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T32.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.Y, literal.x,
+; EG-NEXT: BFE_INT T34.W, PV.W, 0.0, 1,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 6(8.407791e-45), 112(1.569454e-43)
+; EG-NEXT: ALU clause starting at 125:
+; EG-NEXT: LSHR T35.X, T0.W, literal.x,
+; EG-NEXT: LSHR T0.Y, T19.Y, literal.y,
+; EG-NEXT: BFE_INT T34.Z, T0.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.Y, literal.z,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 11(1.541428e-44)
+; EG-NEXT: 5(7.006492e-45), 128(1.793662e-43)
+; EG-NEXT: LSHR T36.X, PS, literal.x,
+; EG-NEXT: BFE_INT T34.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.Y, literal.y,
+; EG-NEXT: BFE_INT T37.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T19.Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 10(1.401298e-44)
+; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T34.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T19.Y, literal.x,
+; EG-NEXT: BFE_INT T37.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.Y, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 15(2.101948e-44), 9(1.261169e-44)
+; EG-NEXT: 144(2.017870e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T38.X, PS, literal.x,
+; EG-NEXT: BFE_INT T37.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.Y, literal.y,
+; EG-NEXT: BFE_INT T39.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T19.Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 14(1.961818e-44)
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T37.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T19.Y, literal.x,
+; EG-NEXT: BFE_INT T39.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.Y, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 19(2.662467e-44), 13(1.821688e-44)
+; EG-NEXT: 160(2.242078e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T40.X, PS, literal.x,
+; EG-NEXT: BFE_INT T39.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.Y, literal.y,
+; EG-NEXT: BFE_INT T41.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T19.Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 18(2.522337e-44)
+; EG-NEXT: 12(1.681558e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T39.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T19.Y, literal.x,
+; EG-NEXT: BFE_INT T41.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.Y, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 23(3.222986e-44), 17(2.382207e-44)
+; EG-NEXT: 176(2.466285e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T42.X, PS, literal.x,
+; EG-NEXT: BFE_INT T41.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.Y, literal.y,
+; EG-NEXT: BFE_INT T43.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T19.Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 22(3.082857e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T41.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T19.Y, literal.x,
+; EG-NEXT: BFE_INT T43.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.Y, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 27(3.783506e-44), 21(2.942727e-44)
+; EG-NEXT: 192(2.690493e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T44.X, PS, literal.x,
+; EG-NEXT: BFE_INT T43.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.Y, literal.y,
+; EG-NEXT: BFE_INT T45.W, PV.Y, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T19.Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 26(3.643376e-44)
+; EG-NEXT: 20(2.802597e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T43.X, PS, 0.0, 1,
+; EG-NEXT: BFE_INT T45.Z, PV.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.Y, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 25(3.503246e-44), 208(2.914701e-43)
+; EG-NEXT: LSHR T46.X, PS, literal.x,
+; EG-NEXT: BFE_INT T45.Y, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T19.Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 24(3.363116e-44)
+; EG-NEXT: BFE_INT T45.X, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.Z, T19.Y, literal.x,
+; EG-NEXT: LSHR T0.W, T19.X, 1,
+; EG-NEXT: LSHR * T1.W, T19.Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 3(4.203895e-45)
+; EG-NEXT: BFE_INT T47.X, T19.X, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T19.X, literal.x,
+; EG-NEXT: LSHR T1.Z, T19.X, literal.y,
+; EG-NEXT: LSHR T2.W, T19.Y, literal.z,
+; EG-NEXT: ASHR * T48.W, T19.Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 3(4.203895e-45)
+; EG-NEXT: 30(4.203895e-44), 31(4.344025e-44)
+; EG-NEXT: BFE_INT T19.X, T19.Y, 0.0, 1,
+; EG-NEXT: LSHR T1.Y, T19.Y, literal.x,
+; EG-NEXT: BFE_INT T48.Z, PV.W, 0.0, 1,
+; EG-NEXT: BFE_INT T47.W, PV.Z, 0.0, 1,
+; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y,
+; EG-NEXT: 29(4.063766e-44), 224(3.138909e-43)
+; EG-NEXT: LSHR * T49.X, PS, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 224:
+; EG-NEXT: BFE_INT T48.Y, T1.Y, 0.0, 1,
+; EG-NEXT: BFE_INT T47.Z, T0.Y, 0.0, 1, BS:VEC_120/SCL_212
+; EG-NEXT: BFE_INT T19.W, T1.W, 0.0, 1,
+; EG-NEXT: LSHR * T1.W, T19.Y, literal.x,
+; EG-NEXT: 28(3.923636e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T48.X, PS, 0.0, 1,
+; EG-NEXT: BFE_INT T47.Y, T0.W, 0.0, 1,
+; EG-NEXT: BFE_INT T19.Z, T0.Z, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T19.Y, 1,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,
+; EG-NEXT: 240(3.363116e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T50.X, PS, literal.x,
+; EG-NEXT: BFE_INT * T19.Y, PV.W, 0.0, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <64 x i1>, ptr addrspace(4) %in
%ext = sext <64 x i1> %load to <64 x i32>
store <64 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_i1_to_i64:
-; GCN-DAG: buffer_load_ubyte [[LOAD:v[0-9]+]],
-; GCN-DAG: v_mov_b32_e32 {{v[0-9]+}}, 0{{$}}
-; GCN-DAG: v_and_b32_e32 {{v[0-9]+}}, 1, [[LOAD]]
-; GCN: buffer_store_dwordx2
define amdgpu_kernel void @constant_zextload_i1_to_i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_i1_to_i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_i1_to_i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: v_mov_b32_e32 v3, 0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_i1_to_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV * T0.Y, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%a = load i1, ptr addrspace(4) %in
%ext = zext i1 %a to i64
store i64 %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_i1_to_i64:
-; GCN: buffer_load_ubyte [[LOAD:v[0-9]+]],
-; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}}
-; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]]
-; GCN: buffer_store_dwordx2
define amdgpu_kernel void @constant_sextload_i1_to_i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_i1_to_i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_i1_to_i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_bfe_i32 v3, v0, 0, 1
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: flat_store_dwordx2 v[1:2], v[3:4]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_i1_to_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, 1,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV * T0.Y, PV.X,
%a = load i1, ptr addrspace(4) %in
%ext = sext i1 %a to i64
store i64 %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v1i1_to_v1i64:
define amdgpu_kernel void @constant_zextload_v1i1_to_v1i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v1i1_to_v1i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v1i1_to_v1i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: v_mov_b32_e32 v3, 0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v1i1_to_v1i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV * T0.Y, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <1 x i1>, ptr addrspace(4) %in
%ext = zext <1 x i1> %load to <1 x i64>
store <1 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v1i1_to_v1i64:
define amdgpu_kernel void @constant_sextload_v1i1_to_v1i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v1i1_to_v1i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v1i1_to_v1i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_bfe_i32 v3, v0, 0, 1
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: flat_store_dwordx2 v[1:2], v[3:4]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v1i1_to_v1i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, 1,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV * T0.Y, PV.X,
%load = load <1 x i1>, ptr addrspace(4) %in
%ext = sext <1 x i1> %load to <1 x i64>
store <1 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v2i1_to_v2i64:
define amdgpu_kernel void @constant_zextload_v2i1_to_v2i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v2i1_to_v2i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v0
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX6-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v2i1_to_v2i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v3
+; GFX8-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v2i1_to_v2i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 5, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_UINT * T0.Z, T0.X, 1, 1,
+; EG-NEXT: AND_INT T0.X, T0.X, 1,
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV T0.W, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <2 x i1>, ptr addrspace(4) %in
%ext = zext <2 x i1> %load to <2 x i64>
store <2 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v2i1_to_v2i64:
define amdgpu_kernel void @constant_sextload_v2i1_to_v2i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v2i1_to_v2i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v0
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v2i1_to_v2i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v0
+; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v2i1_to_v2i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 6, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T1.X, T0.X, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T0.X, 1,
+; EG-NEXT: BFE_INT * T1.Z, PV.W, 0.0, 1,
+; EG-NEXT: MOV * T1.Y, T1.X,
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: MOV * T1.W, T1.Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <2 x i1>, ptr addrspace(4) %in
%ext = sext <2 x i1> %load to <2 x i64>
store <2 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v3i1_to_v3i64:
define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v3i1_to_v3i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v4, off, s[8:11], 0
+; GFX6-NEXT: v_mov_b32_e32 v5, 0
+; GFX6-NEXT: v_mov_b32_e32 v1, v5
+; GFX6-NEXT: v_mov_b32_e32 v3, v5
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v0, 1, v4
+; GFX6-NEXT: v_bfe_u32 v2, v4, 1, 1
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 2, v4
+; GFX6-NEXT: buffer_store_dwordx2 v[4:5], off, s[4:7], 0 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v3i1_to_v3i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v3, v5
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v7, s3
+; GFX8-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, v5
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, 2, v0
+; GFX8-NEXT: v_and_b32_e32 v8, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: flat_store_dwordx2 v[6:7], v[4:5]
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v8
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v3i1_to_v3i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_UINT * T1.Z, T0.X, 1, 1,
+; EG-NEXT: AND_INT T1.X, T0.X, 1,
+; EG-NEXT: MOV T1.Y, 0.0,
+; EG-NEXT: LSHR * T0.X, T0.X, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T1.W, 0.0,
+; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR * T3.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <3 x i1>, ptr addrspace(4) %in
%ext = zext <3 x i1> %load to <3 x i64>
store <3 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v3i1_to_v3i64:
define amdgpu_kernel void @constant_sextload_v3i1_to_v3i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v3i1_to_v3i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 2, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v0
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX6-NEXT: v_bfe_i32 v4, v3, 0, 1
+; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX6-NEXT: buffer_store_dwordx2 v[4:5], off, s[4:7], 0 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v3i1_to_v3i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v7, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 2, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v0
+; GFX8-NEXT: v_bfe_i32 v8, v3, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: flat_store_dwordx2 v[6:7], v[8:9]
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v3i1_to_v3i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T1.X, T0.X, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T0.X, 1,
+; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T1.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T0.X, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.X, PV.W, 0.0, 1,
+; EG-NEXT: MOV T1.Y, T1.X,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T3.X, PV.W, literal.x,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: MOV * T1.W, T1.Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <3 x i1>, ptr addrspace(4) %in
%ext = sext <3 x i1> %load to <3 x i64>
store <3 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v4i1_to_v4i64:
define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v4i1_to_v4i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NEXT: v_mov_b32_e32 v5, v1
+; GFX6-NEXT: v_mov_b32_e32 v7, v1
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_and_b32_e32 v4, 1, v0
+; GFX6-NEXT: v_bfe_u32 v6, v0, 1, 1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 3, v0
+; GFX6-NEXT: v_bfe_u32 v0, v0, 2, 1
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v4i1_to_v4i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NEXT: v_mov_b32_e32 v11, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NEXT: v_mov_b32_e32 v9, s1
+; GFX8-NEXT: v_mov_b32_e32 v10, s2
+; GFX8-NEXT: v_mov_b32_e32 v5, v1
+; GFX8-NEXT: v_mov_b32_e32 v7, v1
+; GFX8-NEXT: v_mov_b32_e32 v8, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, 2, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v12, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 3, v0
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v4
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v12
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff, v6
+; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v4i1_to_v4i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 14, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_UINT * T1.Z, T0.X, literal.x, 1,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T1.X, T0.X, literal.x, 1,
+; EG-NEXT: MOV T1.Y, 0.0,
+; EG-NEXT: BFE_UINT T0.Z, T0.X, 1, 1,
+; EG-NEXT: AND_INT * T0.X, T0.X, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV T1.W, 0.0,
+; EG-NEXT: MOV * T0.W, 0.0,
+; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR * T3.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <4 x i1>, ptr addrspace(4) %in
%ext = zext <4 x i1> %load to <4 x i64>
store <4 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v4i1_to_v4i64:
define amdgpu_kernel void @constant_sextload_v4i1_to_v4i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v4i1_to_v4i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 2, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 3, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v0
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX6-NEXT: v_bfe_i32 v6, v4, 0, 1
+; GFX6-NEXT: v_bfe_i32 v4, v3, 0, 1
+; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v4i1_to_v4i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v11, s3
+; GFX8-NEXT: v_mov_b32_e32 v9, s1
+; GFX8-NEXT: v_mov_b32_e32 v10, s2
+; GFX8-NEXT: v_mov_b32_e32 v8, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 2, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, 3, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v0
+; GFX8-NEXT: v_bfe_i32 v6, v4, 0, 1
+; GFX8-NEXT: v_bfe_i32 v4, v3, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
+; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v4i1_to_v4i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 17, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T0.W, T0.X, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T1.X, T0.X, 0.0, 1,
+; EG-NEXT: BFE_INT T2.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T0.X, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T2.X, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T0.X, 1,
+; EG-NEXT: MOV T2.Y, PV.X,
+; EG-NEXT: BFE_INT * T1.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: MOV T1.Y, T1.X,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T3.X, PV.W, literal.x,
+; EG-NEXT: MOV T1.W, T1.Z,
+; EG-NEXT: MOV * T2.W, T2.Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <4 x i1>, ptr addrspace(4) %in
%ext = sext <4 x i1> %load to <4 x i64>
store <4 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v8i1_to_v8i64:
define amdgpu_kernel void @constant_zextload_v8i1_to_v8i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v8i1_to_v8i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NEXT: v_mov_b32_e32 v5, v1
+; GFX6-NEXT: v_mov_b32_e32 v7, v1
+; GFX6-NEXT: v_mov_b32_e32 v9, v1
+; GFX6-NEXT: v_mov_b32_e32 v11, v1
+; GFX6-NEXT: v_mov_b32_e32 v13, v1
+; GFX6-NEXT: v_mov_b32_e32 v15, v1
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_u32 v14, v0, 1, 1
+; GFX6-NEXT: v_bfe_u32 v10, v0, 3, 1
+; GFX6-NEXT: v_bfe_u32 v6, v0, 5, 1
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 7, v0
+; GFX6-NEXT: v_and_b32_e32 v12, 1, v0
+; GFX6-NEXT: v_bfe_u32 v8, v0, 2, 1
+; GFX6-NEXT: v_bfe_u32 v4, v0, 4, 1
+; GFX6-NEXT: v_bfe_u32 v0, v0, 6, 1
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 offset:48
+; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[4:7], 0 offset:32
+; GFX6-NEXT: buffer_store_dwordx4 v[8:11], off, s[4:7], 0 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v8i1_to_v8i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: v_mov_b32_e32 v13, 0
+; GFX8-NEXT: v_mov_b32_e32 v15, v13
+; GFX8-NEXT: v_mov_b32_e32 v3, 0
+; GFX8-NEXT: v_mov_b32_e32 v7, 0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v19, s3
+; GFX8-NEXT: v_mov_b32_e32 v18, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NEXT: v_mov_b32_e32 v17, s1
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v16, s0
+; GFX8-NEXT: s_add_u32 s0, s0, 16
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v21, s3
+; GFX8-NEXT: v_mov_b32_e32 v23, s1
+; GFX8-NEXT: v_mov_b32_e32 v11, 0
+; GFX8-NEXT: v_mov_b32_e32 v9, v13
+; GFX8-NEXT: v_mov_b32_e32 v5, v13
+; GFX8-NEXT: v_mov_b32_e32 v1, v13
+; GFX8-NEXT: v_mov_b32_e32 v20, s2
+; GFX8-NEXT: v_mov_b32_e32 v22, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v0, 2, v2
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v0, 4, v2
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 6, v2
+; GFX8-NEXT: v_lshrrev_b16_e32 v10, 5, v2
+; GFX8-NEXT: v_and_b32_e32 v8, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v12, 3, v2
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v2
+; GFX8-NEXT: v_lshrrev_b16_e32 v14, 7, v2
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX8-NEXT: v_and_b32_e32 v24, 1, v12
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v12, 1, v6
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff, v24
+; GFX8-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[12:15]
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[8:11]
+; GFX8-NEXT: flat_store_dwordx4 v[22:23], v[4:7]
+; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v8i1_to_v8i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 30, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T12.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T11.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T10.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T9.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_8 T5.X, T5.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T5.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: BFE_UINT * T6.Z, T5.X, literal.x, 1,
+; EG-NEXT: 7(9.809089e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T6.X, T5.X, literal.x, 1,
+; EG-NEXT: MOV T6.Y, 0.0,
+; EG-NEXT: BFE_UINT * T7.Z, T5.X, literal.y, 1,
+; EG-NEXT: 6(8.407791e-45), 5(7.006492e-45)
+; EG-NEXT: BFE_UINT T7.X, T5.X, literal.x, 1,
+; EG-NEXT: MOV T7.Y, 0.0,
+; EG-NEXT: BFE_UINT * T8.Z, T5.X, literal.y, 1,
+; EG-NEXT: 4(5.605194e-45), 3(4.203895e-45)
+; EG-NEXT: BFE_UINT T8.X, T5.X, literal.x, 1,
+; EG-NEXT: MOV T8.Y, 0.0,
+; EG-NEXT: BFE_UINT T5.Z, T5.X, 1, 1,
+; EG-NEXT: AND_INT * T5.X, T5.X, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T5.Y, 0.0,
+; EG-NEXT: MOV T6.W, 0.0,
+; EG-NEXT: MOV * T7.W, 0.0,
+; EG-NEXT: MOV T8.W, 0.0,
+; EG-NEXT: MOV * T5.W, 0.0,
+; EG-NEXT: LSHR T9.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T10.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T11.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR * T12.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <8 x i1>, ptr addrspace(4) %in
%ext = zext <8 x i1> %load to <8 x i64>
store <8 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v8i1_to_v8i64:
define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v8i1_to_v8i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_mov_b32 s10, s2
+; GFX6-NEXT: s_mov_b32 s11, s3
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s6
+; GFX6-NEXT: s_mov_b32 s9, s7
+; GFX6-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v3, 6, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v5, 7, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v7, 4, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v8, 5, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 2, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v6, 3, v0
+; GFX6-NEXT: v_lshrrev_b32_e32 v2, 1, v0
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 1
+; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 1
+; GFX6-NEXT: v_bfe_i32 v10, v8, 0, 1
+; GFX6-NEXT: v_bfe_i32 v8, v7, 0, 1
+; GFX6-NEXT: v_bfe_i32 v14, v5, 0, 1
+; GFX6-NEXT: v_bfe_i32 v12, v3, 0, 1
+; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; GFX6-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX6-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:48
+; GFX6-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:32
+; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v8i1_to_v8i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v19, s3
+; GFX8-NEXT: v_mov_b32_e32 v18, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NEXT: v_mov_b32_e32 v17, s1
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v16, s0
+; GFX8-NEXT: s_add_u32 s0, s0, 16
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v21, s3
+; GFX8-NEXT: v_mov_b32_e32 v23, s1
+; GFX8-NEXT: v_mov_b32_e32 v20, s2
+; GFX8-NEXT: v_mov_b32_e32 v22, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 6, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v5, 7, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, 4, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v8, 5, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, 2, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 3, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v0
+; GFX8-NEXT: v_bfe_i32 v14, v5, 0, 1
+; GFX8-NEXT: v_bfe_i32 v12, v3, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT: v_bfe_i32 v6, v6, 0, 1
+; GFX8-NEXT: v_bfe_i32 v4, v4, 0, 1
+; GFX8-NEXT: v_bfe_i32 v10, v8, 0, 1
+; GFX8-NEXT: v_bfe_i32 v8, v7, 0, 1
+; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[12:15]
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[8:11]
+; GFX8-NEXT: flat_store_dwordx4 v[22:23], v[4:7]
+; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v8i1_to_v8i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 37, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T12.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T11.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T10.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T6.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_8 T5.X, T5.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T5.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: LSHR T6.X, KC0[2].Y, literal.x,
+; EG-NEXT: LSHR * T0.W, T5.X, literal.y,
+; EG-NEXT: 2(2.802597e-45), 7(9.809089e-45)
+; EG-NEXT: BFE_INT T7.X, T5.X, 0.0, 1,
+; EG-NEXT: BFE_INT T8.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T5.X, literal.x,
+; EG-NEXT: LSHR * T1.W, T5.X, literal.y,
+; EG-NEXT: 3(4.203895e-45), 6(8.407791e-45)
+; EG-NEXT: BFE_INT T8.X, PS, 0.0, 1,
+; EG-NEXT: BFE_INT T9.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T5.X, 1,
+; EG-NEXT: LSHR * T1.W, T5.X, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T9.X, PS, 0.0, 1,
+; EG-NEXT: MOV T8.Y, PV.X,
+; EG-NEXT: BFE_INT T7.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T5.X, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 5(7.006492e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T10.X, PS, literal.x,
+; EG-NEXT: MOV T9.Y, PV.X,
+; EG-NEXT: BFE_INT T5.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T0.W, T5.X, literal.y,
+; EG-NEXT: 2(2.802597e-45), 4(5.605194e-45)
+; EG-NEXT: BFE_INT T5.X, PV.W, 0.0, 1,
+; EG-NEXT: MOV T7.Y, T7.X,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T11.X, PV.W, literal.x,
+; EG-NEXT: MOV T5.Y, PV.X,
+; EG-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.y,
+; EG-NEXT: MOV T7.W, T7.Z,
+; EG-NEXT: MOV * T9.W, T9.Z,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T12.X, PV.Z, literal.x,
+; EG-NEXT: MOV T5.W, T5.Z,
+; EG-NEXT: MOV * T8.W, T8.Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <8 x i1>, ptr addrspace(4) %in
%ext = sext <8 x i1> %load to <8 x i64>
store <8 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v16i1_to_v16i64:
define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v16i1_to_v16i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_mov_b32 s10, s2
+; GFX6-NEXT: s_mov_b32 s11, s3
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s6
+; GFX6-NEXT: s_mov_b32 s9, s7
+; GFX6-NEXT: buffer_load_ushort v29, off, s[8:11], 0
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NEXT: v_mov_b32_e32 v4, v1
+; GFX6-NEXT: v_mov_b32_e32 v6, v1
+; GFX6-NEXT: v_mov_b32_e32 v7, v1
+; GFX6-NEXT: v_mov_b32_e32 v9, v1
+; GFX6-NEXT: v_mov_b32_e32 v10, v1
+; GFX6-NEXT: v_mov_b32_e32 v12, v1
+; GFX6-NEXT: v_mov_b32_e32 v14, v1
+; GFX6-NEXT: v_mov_b32_e32 v16, v1
+; GFX6-NEXT: v_mov_b32_e32 v18, v1
+; GFX6-NEXT: v_mov_b32_e32 v20, v1
+; GFX6-NEXT: v_mov_b32_e32 v22, v1
+; GFX6-NEXT: v_mov_b32_e32 v24, v1
+; GFX6-NEXT: v_mov_b32_e32 v26, v1
+; GFX6-NEXT: v_mov_b32_e32 v28, v1
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_bfe_u32 v2, v29, 11, 1
+; GFX6-NEXT: v_bfe_u32 v0, v29, 10, 1
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NEXT: v_bfe_u32 v5, v29, 9, 1
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_bfe_u32 v3, v29, 8, 1
+; GFX6-NEXT: buffer_store_dwordx4 v[3:6], off, s[0:3], 0 offset:64
+; GFX6-NEXT: v_lshrrev_b32_e32 v8, 15, v29
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_bfe_u32 v6, v29, 14, 1
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], off, s[0:3], 0 offset:112
+; GFX6-NEXT: v_bfe_u32 v27, v29, 5, 1
+; GFX6-NEXT: v_bfe_u32 v23, v29, 7, 1
+; GFX6-NEXT: v_bfe_u32 v19, v29, 1, 1
+; GFX6-NEXT: v_bfe_u32 v15, v29, 3, 1
+; GFX6-NEXT: v_bfe_u32 v11, v29, 13, 1
+; GFX6-NEXT: v_bfe_u32 v25, v29, 4, 1
+; GFX6-NEXT: v_bfe_u32 v21, v29, 6, 1
+; GFX6-NEXT: v_and_b32_e32 v17, 1, v29
+; GFX6-NEXT: v_bfe_u32 v13, v29, 2, 1
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_bfe_u32 v9, v29, 12, 1
+; GFX6-NEXT: buffer_store_dwordx4 v[9:12], off, s[0:3], 0 offset:96
+; GFX6-NEXT: buffer_store_dwordx4 v[13:16], off, s[0:3], 0 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[17:20], off, s[0:3], 0
+; GFX6-NEXT: buffer_store_dwordx4 v[21:24], off, s[0:3], 0 offset:48
+; GFX6-NEXT: buffer_store_dwordx4 v[25:28], off, s[0:3], 0 offset:32
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v16i1_to_v16i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: v_mov_b32_e32 v2, 0
+; GFX8-NEXT: v_mov_b32_e32 v6, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, v2
+; GFX8-NEXT: v_mov_b32_e32 v23, 0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ushort v0, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 0x70
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: s_add_u32 s4, s0, 0x50
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v9, s5
+; GFX8-NEXT: v_mov_b32_e32 v25, s3
+; GFX8-NEXT: v_mov_b32_e32 v8, s4
+; GFX8-NEXT: v_mov_b32_e32 v24, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 64
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v21, v2
+; GFX8-NEXT: v_mov_b32_e32 v17, v2
+; GFX8-NEXT: v_mov_b32_e32 v13, v2
+; GFX8-NEXT: v_mov_b32_e32 v19, 0
+; GFX8-NEXT: v_mov_b32_e32 v7, 0
+; GFX8-NEXT: v_mov_b32_e32 v11, 0
+; GFX8-NEXT: v_mov_b32_e32 v15, 0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 10, v0
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 11, v0
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v5, 0xffff, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 14, v0
+; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[3:6]
+; GFX8-NEXT: v_and_b32_e32 v1, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 15, v0
+; GFX8-NEXT: flat_store_dwordx4 v[24:25], v[1:4]
+; GFX8-NEXT: v_mov_b32_e32 v25, s3
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 9, v0
+; GFX8-NEXT: v_mov_b32_e32 v6, 1
+; GFX8-NEXT: v_mov_b32_e32 v24, s2
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX8-NEXT: s_add_u32 s2, s0, 0x60
+; GFX8-NEXT: v_mov_b32_e32 v4, 0
+; GFX8-NEXT: v_and_b32_sdwa v1, v0, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_e32 v3, 0xffff, v3
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[24:25], v[1:4]
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 12, v0
+; GFX8-NEXT: v_mov_b32_e32 v4, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v25, s3
+; GFX8-NEXT: v_and_b32_e32 v20, 1, v6
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 13, v0
+; GFX8-NEXT: v_mov_b32_e32 v24, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v6
+; GFX8-NEXT: v_mov_b32_e32 v9, v2
+; GFX8-NEXT: v_mov_b32_e32 v5, v2
+; GFX8-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v22, 0xffff, v6
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 2, v0
+; GFX8-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NEXT: flat_store_dwordx4 v[3:4], v[20:23]
+; GFX8-NEXT: s_add_u32 s0, s0, 16
+; GFX8-NEXT: v_lshrrev_b16_e32 v3, 7, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v4, 6, v0
+; GFX8-NEXT: v_and_b32_e32 v8, 1, v6
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 4, v0
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v12, 1, v6
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 5, v0
+; GFX8-NEXT: v_and_b32_e32 v16, 1, v4
+; GFX8-NEXT: v_lshrrev_b16_e32 v10, 3, v0
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v0, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v3, 1, v3
+; GFX8-NEXT: v_mov_b32_e32 v21, s3
+; GFX8-NEXT: v_mov_b32_e32 v23, s1
+; GFX8-NEXT: v_and_b32_e32 v14, 1, v6
+; GFX8-NEXT: v_and_b32_e32 v10, 1, v10
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: v_and_b32_e32 v18, 0xffff, v3
+; GFX8-NEXT: v_mov_b32_e32 v20, s2
+; GFX8-NEXT: v_mov_b32_e32 v22, s0
+; GFX8-NEXT: v_and_b32_e32 v6, 0xffff, v0
+; GFX8-NEXT: v_and_b32_e32 v10, 0xffff, v10
+; GFX8-NEXT: v_and_b32_e32 v14, 0xffff, v14
+; GFX8-NEXT: flat_store_dwordx4 v[24:25], v[16:19]
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[12:15]
+; GFX8-NEXT: flat_store_dwordx4 v[22:23], v[8:11]
+; GFX8-NEXT: flat_store_dwordx4 v[1:2], v[4:7]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v16i1_to_v16i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @12
+; EG-NEXT: ALU 62, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T22.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T21.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XYZW, T20.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T19.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T18.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T17.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T16.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T15.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 12:
+; EG-NEXT: VTX_READ_16 T7.X, T7.X, 0, #1
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: MOV * T7.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 15:
+; EG-NEXT: LSHR * T8.Z, T7.X, literal.x,
+; EG-NEXT: 15(2.101948e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T8.X, T7.X, literal.x, 1,
+; EG-NEXT: MOV T8.Y, 0.0,
+; EG-NEXT: BFE_UINT * T9.Z, T7.X, literal.y, 1,
+; EG-NEXT: 14(1.961818e-44), 13(1.821688e-44)
+; EG-NEXT: BFE_UINT T9.X, T7.X, literal.x, 1,
+; EG-NEXT: MOV T9.Y, 0.0,
+; EG-NEXT: BFE_UINT * T10.Z, T7.X, literal.y, 1,
+; EG-NEXT: 12(1.681558e-44), 11(1.541428e-44)
+; EG-NEXT: BFE_UINT T10.X, T7.X, literal.x, 1,
+; EG-NEXT: MOV T10.Y, 0.0,
+; EG-NEXT: BFE_UINT * T11.Z, T7.X, literal.y, 1,
+; EG-NEXT: 10(1.401298e-44), 9(1.261169e-44)
+; EG-NEXT: BFE_UINT T11.X, T7.X, literal.x, 1,
+; EG-NEXT: MOV T11.Y, 0.0,
+; EG-NEXT: BFE_UINT * T12.Z, T7.X, literal.y, 1,
+; EG-NEXT: 8(1.121039e-44), 7(9.809089e-45)
+; EG-NEXT: BFE_UINT T12.X, T7.X, literal.x, 1,
+; EG-NEXT: MOV T12.Y, 0.0,
+; EG-NEXT: BFE_UINT * T13.Z, T7.X, literal.y, 1,
+; EG-NEXT: 6(8.407791e-45), 5(7.006492e-45)
+; EG-NEXT: BFE_UINT T13.X, T7.X, literal.x, 1,
+; EG-NEXT: MOV T13.Y, 0.0,
+; EG-NEXT: BFE_UINT * T14.Z, T7.X, literal.y, 1,
+; EG-NEXT: 4(5.605194e-45), 3(4.203895e-45)
+; EG-NEXT: BFE_UINT T14.X, T7.X, literal.x, 1,
+; EG-NEXT: MOV T14.Y, 0.0,
+; EG-NEXT: BFE_UINT T7.Z, T7.X, 1, 1,
+; EG-NEXT: AND_INT * T7.X, T7.X, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T7.Y, 0.0,
+; EG-NEXT: MOV T8.W, 0.0,
+; EG-NEXT: MOV * T9.W, 0.0,
+; EG-NEXT: MOV T10.W, 0.0,
+; EG-NEXT: MOV * T11.W, 0.0,
+; EG-NEXT: MOV T12.W, 0.0,
+; EG-NEXT: MOV * T13.W, 0.0,
+; EG-NEXT: MOV T14.W, 0.0,
+; EG-NEXT: MOV * T7.W, 0.0,
+; EG-NEXT: LSHR T15.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T16.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T17.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T18.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T19.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T20.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: LSHR T21.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43)
+; EG-NEXT: LSHR * T22.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <16 x i1>, ptr addrspace(4) %in
%ext = zext <16 x i1> %load to <16 x i64>
store <16 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v16i1_to_v16i64:
define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v16i1_to_v16i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_mov_b32 s10, s2
+; GFX6-NEXT: s_mov_b32 s11, s3
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s6
+; GFX6-NEXT: s_mov_b32 s9, s7
+; GFX6-NEXT: buffer_load_ushort v5, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v0, 14, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 15, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v7, 12, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v9, 10, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v11, 11, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v12, 8, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v13, 9, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v8, 6, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v10, 7, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v4, 4, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v6, 5, v5
+; GFX6-NEXT: v_lshrrev_b32_e32 v14, 2, v5
+; GFX6-NEXT: v_bfe_i32 v2, v1, 0, 1
+; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX6-NEXT: v_lshrrev_b32_e32 v15, 3, v5
+; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 1, v5
+; GFX6-NEXT: v_bfe_i32 v2, v15, 0, 1
+; GFX6-NEXT: v_bfe_i32 v0, v14, 0, 1
+; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 1
+; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 1
+; GFX6-NEXT: v_bfe_i32 v10, v10, 0, 1
+; GFX6-NEXT: v_bfe_i32 v8, v8, 0, 1
+; GFX6-NEXT: v_bfe_i32 v14, v13, 0, 1
+; GFX6-NEXT: v_bfe_i32 v12, v12, 0, 1
+; GFX6-NEXT: v_bfe_i32 v18, v11, 0, 1
+; GFX6-NEXT: v_bfe_i32 v16, v9, 0, 1
+; GFX6-NEXT: v_bfe_i32 v22, v1, 0, 1
+; GFX6-NEXT: v_bfe_i32 v20, v5, 0, 1
+; GFX6-NEXT: v_lshrrev_b32_e32 v1, 13, v5
+; GFX6-NEXT: v_bfe_i32 v26, v1, 0, 1
+; GFX6-NEXT: v_bfe_i32 v24, v7, 0, 1
+; GFX6-NEXT: v_ashrrev_i32_e32 v21, 31, v20
+; GFX6-NEXT: v_ashrrev_i32_e32 v23, 31, v22
+; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; GFX6-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX6-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX6-NEXT: v_ashrrev_i32_e32 v19, 31, v18
+; GFX6-NEXT: v_ashrrev_i32_e32 v17, 31, v16
+; GFX6-NEXT: v_ashrrev_i32_e32 v27, 31, v26
+; GFX6-NEXT: v_ashrrev_i32_e32 v25, 31, v24
+; GFX6-NEXT: buffer_store_dwordx4 v[24:27], off, s[0:3], 0 offset:96
+; GFX6-NEXT: buffer_store_dwordx4 v[16:19], off, s[0:3], 0 offset:80
+; GFX6-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:64
+; GFX6-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:48
+; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:32
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NEXT: buffer_store_dwordx4 v[20:23], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v16i1_to_v16i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: flat_load_ushort v0, v[0:1]
+; GFX8-NEXT: s_add_u32 s2, s0, 0x70
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v6, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 0x60
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v8, s3
+; GFX8-NEXT: v_mov_b32_e32 v7, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 0x50
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v10, s3
+; GFX8-NEXT: v_mov_b32_e32 v9, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 64
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v12, s3
+; GFX8-NEXT: v_mov_b32_e32 v11, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v19, s3
+; GFX8-NEXT: v_mov_b32_e32 v18, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NEXT: v_mov_b32_e32 v17, s1
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v16, s0
+; GFX8-NEXT: s_add_u32 s0, s0, 16
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v21, s3
+; GFX8-NEXT: v_mov_b32_e32 v23, s1
+; GFX8-NEXT: v_mov_b32_e32 v20, s2
+; GFX8-NEXT: v_mov_b32_e32 v22, s0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e32 v1, 14, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 15, v0
+; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1
+; GFX8-NEXT: v_lshrrev_b16_e32 v13, 12, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v14, 13, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX8-NEXT: flat_store_dwordx4 v[5:6], v[1:4]
+; GFX8-NEXT: v_lshrrev_b16_e32 v15, 10, v0
+; GFX8-NEXT: v_bfe_i32 v3, v14, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v13, 0, 1
+; GFX8-NEXT: v_lshrrev_b16_e32 v5, 11, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[1:4]
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 8, v0
+; GFX8-NEXT: v_bfe_i32 v3, v5, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v15, 0, 1
+; GFX8-NEXT: v_lshrrev_b16_e32 v13, 9, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[1:4]
+; GFX8-NEXT: v_lshrrev_b16_e32 v7, 6, v0
+; GFX8-NEXT: v_bfe_i32 v3, v13, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v6, 0, 1
+; GFX8-NEXT: v_lshrrev_b16_e32 v14, 7, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX8-NEXT: v_lshrrev_b16_e32 v5, 4, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v8, 5, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v9, 2, v0
+; GFX8-NEXT: v_lshrrev_b16_e32 v6, 3, v0
+; GFX8-NEXT: flat_store_dwordx4 v[11:12], v[1:4]
+; GFX8-NEXT: v_bfe_i32 v14, v14, 0, 1
+; GFX8-NEXT: v_lshrrev_b16_e32 v2, 1, v0
+; GFX8-NEXT: v_bfe_i32 v12, v7, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 1
+; GFX8-NEXT: v_bfe_i32 v6, v6, 0, 1
+; GFX8-NEXT: v_bfe_i32 v4, v9, 0, 1
+; GFX8-NEXT: v_bfe_i32 v10, v8, 0, 1
+; GFX8-NEXT: v_bfe_i32 v8, v5, 0, 1
+; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[12:15]
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[8:11]
+; GFX8-NEXT: flat_store_dwordx4 v[22:23], v[4:7]
+; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v16i1_to_v16i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @12
+; EG-NEXT: ALU 78, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T22.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T21.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T18.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T12.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T11.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T10.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T9.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T8.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 12:
+; EG-NEXT: VTX_READ_16 T7.X, T7.X, 0, #1
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: MOV * T7.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 15:
+; EG-NEXT: LSHR T8.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T9.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T10.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T11.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T12.X, PV.W, literal.x,
+; EG-NEXT: LSHR * T0.W, T7.X, literal.y,
+; EG-NEXT: 2(2.802597e-45), 15(2.101948e-44)
+; EG-NEXT: BFE_INT T13.X, T7.X, 0.0, 1,
+; EG-NEXT: BFE_INT T14.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T7.X, literal.x,
+; EG-NEXT: LSHR * T1.W, T7.X, literal.y,
+; EG-NEXT: 11(1.541428e-44), 14(1.961818e-44)
+; EG-NEXT: BFE_INT T14.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T0.Y, T7.X, literal.x,
+; EG-NEXT: BFE_INT T15.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T7.X, literal.y,
+; EG-NEXT: LSHR * T1.W, T7.X, literal.z,
+; EG-NEXT: 12(1.681558e-44), 7(9.809089e-45)
+; EG-NEXT: 10(1.401298e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T15.X, PS, 0.0, 1,
+; EG-NEXT: MOV T14.Y, PV.X,
+; EG-NEXT: BFE_INT T16.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T7.X, literal.x,
+; EG-NEXT: LSHR * T1.W, T7.X, literal.y,
+; EG-NEXT: 3(4.203895e-45), 6(8.407791e-45)
+; EG-NEXT: BFE_INT T16.X, PS, 0.0, 1,
+; EG-NEXT: MOV T15.Y, PV.X,
+; EG-NEXT: BFE_INT T17.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T7.X, 1,
+; EG-NEXT: LSHR * T1.W, T7.X, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T17.X, PS, 0.0, 1,
+; EG-NEXT: MOV T16.Y, PV.X,
+; EG-NEXT: BFE_INT T13.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T7.X, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 5(7.006492e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T18.X, PS, literal.x,
+; EG-NEXT: MOV T17.Y, PV.X,
+; EG-NEXT: BFE_INT T19.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T7.X, literal.y,
+; EG-NEXT: LSHR * T1.W, T7.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 9(1.261169e-44)
+; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T19.X, PS, 0.0, 1,
+; EG-NEXT: MOV T13.Y, T13.X,
+; EG-NEXT: BFE_INT T7.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T0.W, T7.X, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: LSHR * T1.W, T7.X, literal.y,
+; EG-NEXT: 13(1.821688e-44), 8(1.121039e-44)
+; EG-NEXT: BFE_INT T7.X, PS, 0.0, 1,
+; EG-NEXT: MOV T19.Y, PV.X,
+; EG-NEXT: BFE_INT T20.Z, PV.W, 0.0, 1,
+; EG-NEXT: MOV T13.W, T13.Z,
+; EG-NEXT: MOV * T17.W, T17.Z,
+; EG-NEXT: BFE_INT T20.X, T0.Y, 0.0, 1,
+; EG-NEXT: MOV T7.Y, PV.X,
+; EG-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.x,
+; EG-NEXT: MOV T19.W, T19.Z,
+; EG-NEXT: MOV * T16.W, T16.Z,
+; EG-NEXT: 96(1.345247e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T21.X, PV.Z, literal.x,
+; EG-NEXT: MOV T20.Y, PV.X,
+; EG-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.y,
+; EG-NEXT: MOV T7.W, T7.Z,
+; EG-NEXT: MOV * T15.W, T15.Z,
+; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43)
+; EG-NEXT: LSHR T22.X, PV.Z, literal.x,
+; EG-NEXT: MOV T20.W, T20.Z,
+; EG-NEXT: MOV * T14.W, T14.Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <16 x i1>, ptr addrspace(4) %in
%ext = sext <16 x i1> %load to <16 x i64>
store <16 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v32i1_to_v32i64:
define amdgpu_kernel void @constant_zextload_v32i1_to_v32i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v32i1_to_v32i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_bfe_u32 s5, s4, 0x10001
+; GFX6-NEXT: s_bfe_u32 s6, s4, 0x10003
+; GFX6-NEXT: s_bfe_u32 s7, s4, 0x10005
+; GFX6-NEXT: s_bfe_u32 s8, s4, 0x10007
+; GFX6-NEXT: s_bfe_u32 s9, s4, 0x10009
+; GFX6-NEXT: s_bfe_u32 s10, s4, 0x1000b
+; GFX6-NEXT: s_bfe_u32 s11, s4, 0x1000d
+; GFX6-NEXT: s_bfe_u32 s12, s4, 0x1000f
+; GFX6-NEXT: s_bfe_u32 s13, s4, 0x10011
+; GFX6-NEXT: s_bfe_u32 s14, s4, 0x10013
+; GFX6-NEXT: s_bfe_u32 s15, s4, 0x10015
+; GFX6-NEXT: s_bfe_u32 s16, s4, 0x10017
+; GFX6-NEXT: s_bfe_u32 s17, s4, 0x10019
+; GFX6-NEXT: s_bfe_u32 s18, s4, 0x1001b
+; GFX6-NEXT: s_bfe_u32 s19, s4, 0x1001d
+; GFX6-NEXT: s_lshr_b32 s20, s4, 31
+; GFX6-NEXT: s_and_b32 s21, s4, 1
+; GFX6-NEXT: s_bfe_u32 s22, s4, 0x10002
+; GFX6-NEXT: s_bfe_u32 s23, s4, 0x10004
+; GFX6-NEXT: s_bfe_u32 s24, s4, 0x10006
+; GFX6-NEXT: s_bfe_u32 s25, s4, 0x10008
+; GFX6-NEXT: s_bfe_u32 s26, s4, 0x1000a
+; GFX6-NEXT: s_bfe_u32 s27, s4, 0x1000c
+; GFX6-NEXT: s_bfe_u32 s28, s4, 0x1000e
+; GFX6-NEXT: s_bfe_u32 s29, s4, 0x10010
+; GFX6-NEXT: s_bfe_u32 s30, s4, 0x10012
+; GFX6-NEXT: s_bfe_u32 s31, s4, 0x10014
+; GFX6-NEXT: s_bfe_u32 s33, s4, 0x10016
+; GFX6-NEXT: s_bfe_u32 s34, s4, 0x10018
+; GFX6-NEXT: s_bfe_u32 s35, s4, 0x1001a
+; GFX6-NEXT: s_bfe_u32 s36, s4, 0x1001e
+; GFX6-NEXT: s_bfe_u32 s4, s4, 0x1001c
+; GFX6-NEXT: v_mov_b32_e32 v0, s36
+; GFX6-NEXT: v_mov_b32_e32 v2, s20
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:240
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v2, s19
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:224
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s35
+; GFX6-NEXT: v_mov_b32_e32 v2, s18
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:208
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s34
+; GFX6-NEXT: v_mov_b32_e32 v2, s17
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:192
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s33
+; GFX6-NEXT: v_mov_b32_e32 v2, s16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:176
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s31
+; GFX6-NEXT: v_mov_b32_e32 v2, s15
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:160
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s30
+; GFX6-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s29
+; GFX6-NEXT: v_mov_b32_e32 v2, s13
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s28
+; GFX6-NEXT: v_mov_b32_e32 v2, s12
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s27
+; GFX6-NEXT: v_mov_b32_e32 v2, s11
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s26
+; GFX6-NEXT: v_mov_b32_e32 v2, s10
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s25
+; GFX6-NEXT: v_mov_b32_e32 v2, s9
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s24
+; GFX6-NEXT: v_mov_b32_e32 v2, s8
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s23
+; GFX6-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s22
+; GFX6-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s21
+; GFX6-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v32i1_to_v32i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: v_mov_b32_e32 v26, 0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 13, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 11, s2
+; GFX8-NEXT: v_and_b32_e32 v15, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 9, s2
+; GFX8-NEXT: s_lshr_b32 s7, s2, 24
+; GFX8-NEXT: v_and_b32_e32 v10, 1, v1
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 7, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 3, s2
+; GFX8-NEXT: s_bfe_u32 s6, s2, 0x10018
+; GFX8-NEXT: s_and_b32 s14, s2, 1
+; GFX8-NEXT: s_bfe_u32 s15, s2, 0x10011
+; GFX8-NEXT: s_bfe_u32 s16, s2, 0x10010
+; GFX8-NEXT: s_bfe_u32 s17, s2, 0x10012
+; GFX8-NEXT: s_bfe_u32 s18, s2, 0x10013
+; GFX8-NEXT: s_bfe_u32 s19, s2, 0x10014
+; GFX8-NEXT: s_bfe_u32 s20, s2, 0x10015
+; GFX8-NEXT: s_bfe_u32 s21, s2, 0x10016
+; GFX8-NEXT: s_bfe_u32 s22, s2, 0x10017
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v16, 14, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v14, 12, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 10, s2
+; GFX8-NEXT: v_and_b32_e32 v4, 1, v0
+; GFX8-NEXT: v_lshrrev_b16_e64 v5, 6, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 5, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v3, 4, s2
+; GFX8-NEXT: v_and_b32_e32 v7, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v8, 2, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 1, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v18, 15, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 0xb0
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: s_add_u32 s4, s0, 0xa0
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: s_add_u32 s8, s0, 0x90
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: s_add_u32 s10, s0, 0x80
+; GFX8-NEXT: s_addc_u32 s11, s1, 0
+; GFX8-NEXT: s_add_u32 s12, s0, 0x70
+; GFX8-NEXT: v_and_b32_e32 v11, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 5, s7
+; GFX8-NEXT: s_addc_u32 s13, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v12, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 3, s7
+; GFX8-NEXT: v_mov_b32_e32 v21, s13
+; GFX8-NEXT: v_and_b32_e32 v23, 1, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NEXT: v_mov_b32_e32 v20, s12
+; GFX8-NEXT: s_add_u32 s12, s0, 0xf0
+; GFX8-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX8-NEXT: v_mov_b32_e32 v17, v1
+; GFX8-NEXT: v_mov_b32_e32 v19, v1
+; GFX8-NEXT: s_addc_u32 s13, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
+; GFX8-NEXT: v_mov_b32_e32 v21, s13
+; GFX8-NEXT: v_lshrrev_b16_e64 v16, 1, s7
+; GFX8-NEXT: v_lshrrev_b16_e64 v22, 6, s7
+; GFX8-NEXT: v_and_b32_e32 v16, 1, v16
+; GFX8-NEXT: v_mov_b32_e32 v20, s12
+; GFX8-NEXT: s_add_u32 s12, s0, 0x60
+; GFX8-NEXT: v_and_b32_e32 v25, 0xffff, v16
+; GFX8-NEXT: v_and_b32_e32 v16, 1, v22
+; GFX8-NEXT: v_lshrrev_b16_e64 v18, 7, s7
+; GFX8-NEXT: s_addc_u32 s13, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[16:19]
+; GFX8-NEXT: v_and_b32_e32 v14, 1, v14
+; GFX8-NEXT: v_mov_b32_e32 v19, s13
+; GFX8-NEXT: v_and_b32_e32 v16, 0xffff, v15
+; GFX8-NEXT: v_mov_b32_e32 v17, 0
+; GFX8-NEXT: v_mov_b32_e32 v15, v1
+; GFX8-NEXT: v_mov_b32_e32 v18, s12
+; GFX8-NEXT: s_add_u32 s12, s0, 0x50
+; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[14:17]
+; GFX8-NEXT: v_and_b32_e32 v18, 1, v9
+; GFX8-NEXT: v_and_b32_e32 v20, 0xffff, v10
+; GFX8-NEXT: s_addc_u32 s13, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v9, s12
+; GFX8-NEXT: v_mov_b32_e32 v10, s13
+; GFX8-NEXT: s_add_u32 s12, s0, 64
+; GFX8-NEXT: v_mov_b32_e32 v21, 0
+; GFX8-NEXT: v_mov_b32_e32 v19, v1
+; GFX8-NEXT: s_addc_u32 s13, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v16, 0xffff, v23
+; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[18:21]
+; GFX8-NEXT: v_mov_b32_e32 v9, 1
+; GFX8-NEXT: v_mov_b32_e32 v23, s13
+; GFX8-NEXT: v_and_b32_sdwa v18, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_e32 v20, 0xffff, v6
+; GFX8-NEXT: v_mov_b32_e32 v21, 0
+; GFX8-NEXT: v_mov_b32_e32 v19, v1
+; GFX8-NEXT: v_mov_b32_e32 v22, s12
+; GFX8-NEXT: s_add_u32 s12, s0, 48
+; GFX8-NEXT: flat_store_dwordx4 v[22:23], v[18:21]
+; GFX8-NEXT: s_addc_u32 s13, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v18, 1, v5
+; GFX8-NEXT: v_and_b32_e32 v20, 0xffff, v4
+; GFX8-NEXT: v_mov_b32_e32 v4, s12
+; GFX8-NEXT: v_mov_b32_e32 v21, 0
+; GFX8-NEXT: v_mov_b32_e32 v5, s13
+; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[18:21]
+; GFX8-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NEXT: v_and_b32_e32 v18, 1, v3
+; GFX8-NEXT: v_and_b32_e32 v20, 0xffff, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s21
+; GFX8-NEXT: v_mov_b32_e32 v2, s22
+; GFX8-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v0, s19
+; GFX8-NEXT: v_mov_b32_e32 v2, s20
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NEXT: v_mov_b32_e32 v0, s17
+; GFX8-NEXT: v_mov_b32_e32 v2, s18
+; GFX8-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v4, s10
+; GFX8-NEXT: v_mov_b32_e32 v0, s16
+; GFX8-NEXT: v_mov_b32_e32 v2, s15
+; GFX8-NEXT: v_mov_b32_e32 v5, s11
+; GFX8-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v21, 0
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[18:21]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_and_b32_e32 v11, 0xffff, v11
+; GFX8-NEXT: v_mov_b32_e32 v15, 0
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v8
+; GFX8-NEXT: v_and_b32_e32 v8, 0xffff, v7
+; GFX8-NEXT: v_mov_b32_e32 v9, 0
+; GFX8-NEXT: v_mov_b32_e32 v7, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[6:9]
+; GFX8-NEXT: v_mov_b32_e32 v0, s14
+; GFX8-NEXT: v_mov_b32_e32 v2, v11
+; GFX8-NEXT: v_mov_b32_e32 v3, v15
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: s_add_u32 s2, s0, 0xe0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0xd0
+; GFX8-NEXT: v_lshrrev_b16_e64 v13, 4, s7
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v10, 1, v13
+; GFX8-NEXT: v_and_b32_e32 v12, 0xffff, v12
+; GFX8-NEXT: v_mov_b32_e32 v13, 0
+; GFX8-NEXT: v_mov_b32_e32 v11, v1
+; GFX8-NEXT: s_add_u32 s0, s0, 0xc0
+; GFX8-NEXT: v_lshrrev_b16_e64 v24, 2, s7
+; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[10:13]
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v14, 1, v24
+; GFX8-NEXT: v_mov_b32_e32 v17, 0
+; GFX8-NEXT: v_mov_b32_e32 v15, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[14:17]
+; GFX8-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NEXT: v_mov_b32_e32 v2, v25
+; GFX8-NEXT: v_mov_b32_e32 v3, v26
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v32i1_to_v32i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @24, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @22
+; EG-NEXT: ALU 96, @25, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 30, @122, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T42.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T41.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T40.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T39.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T38.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T37.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T18.XYZW, T36.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T35.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T34.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T21.XYZW, T33.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T22.XYZW, T32.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T23.XYZW, T31.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T24.XYZW, T30.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T25.XYZW, T29.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T26.XYZW, T28.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T27.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 22:
+; EG-NEXT: VTX_READ_32 T11.X, T11.X, 0, #1
+; EG-NEXT: ALU clause starting at 24:
+; EG-NEXT: MOV * T11.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 25:
+; EG-NEXT: LSHR * T12.Z, T11.X, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T12.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T12.Y, 0.0,
+; EG-NEXT: BFE_UINT * T13.Z, T11.X, literal.y, 1,
+; EG-NEXT: 30(4.203895e-44), 29(4.063766e-44)
+; EG-NEXT: BFE_UINT T13.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T13.Y, 0.0,
+; EG-NEXT: BFE_UINT * T14.Z, T11.X, literal.y, 1,
+; EG-NEXT: 28(3.923636e-44), 27(3.783506e-44)
+; EG-NEXT: BFE_UINT T14.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T14.Y, 0.0,
+; EG-NEXT: BFE_UINT * T15.Z, T11.X, literal.y, 1,
+; EG-NEXT: 26(3.643376e-44), 25(3.503246e-44)
+; EG-NEXT: BFE_UINT T15.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T15.Y, 0.0,
+; EG-NEXT: BFE_UINT * T16.Z, T11.X, literal.y, 1,
+; EG-NEXT: 24(3.363116e-44), 23(3.222986e-44)
+; EG-NEXT: BFE_UINT T16.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T16.Y, 0.0,
+; EG-NEXT: BFE_UINT * T17.Z, T11.X, literal.y, 1,
+; EG-NEXT: 22(3.082857e-44), 21(2.942727e-44)
+; EG-NEXT: BFE_UINT T17.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T17.Y, 0.0,
+; EG-NEXT: BFE_UINT * T18.Z, T11.X, literal.y, 1,
+; EG-NEXT: 20(2.802597e-44), 19(2.662467e-44)
+; EG-NEXT: BFE_UINT T18.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T18.Y, 0.0,
+; EG-NEXT: BFE_UINT * T19.Z, T11.X, literal.y, 1,
+; EG-NEXT: 18(2.522337e-44), 17(2.382207e-44)
+; EG-NEXT: BFE_UINT T19.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T19.Y, 0.0,
+; EG-NEXT: BFE_UINT * T20.Z, T11.X, literal.y, 1,
+; EG-NEXT: 16(2.242078e-44), 15(2.101948e-44)
+; EG-NEXT: BFE_UINT T20.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T20.Y, 0.0,
+; EG-NEXT: BFE_UINT * T21.Z, T11.X, literal.y, 1,
+; EG-NEXT: 14(1.961818e-44), 13(1.821688e-44)
+; EG-NEXT: BFE_UINT T21.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T21.Y, 0.0,
+; EG-NEXT: BFE_UINT * T22.Z, T11.X, literal.y, 1,
+; EG-NEXT: 12(1.681558e-44), 11(1.541428e-44)
+; EG-NEXT: BFE_UINT T22.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T22.Y, 0.0,
+; EG-NEXT: BFE_UINT * T23.Z, T11.X, literal.y, 1,
+; EG-NEXT: 10(1.401298e-44), 9(1.261169e-44)
+; EG-NEXT: BFE_UINT T23.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T23.Y, 0.0,
+; EG-NEXT: BFE_UINT * T24.Z, T11.X, literal.y, 1,
+; EG-NEXT: 8(1.121039e-44), 7(9.809089e-45)
+; EG-NEXT: BFE_UINT T24.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T24.Y, 0.0,
+; EG-NEXT: BFE_UINT * T25.Z, T11.X, literal.y, 1,
+; EG-NEXT: 6(8.407791e-45), 5(7.006492e-45)
+; EG-NEXT: BFE_UINT T25.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T25.Y, 0.0,
+; EG-NEXT: BFE_UINT * T26.Z, T11.X, literal.y, 1,
+; EG-NEXT: 4(5.605194e-45), 3(4.203895e-45)
+; EG-NEXT: BFE_UINT T26.X, T11.X, literal.x, 1,
+; EG-NEXT: MOV T26.Y, 0.0,
+; EG-NEXT: BFE_UINT T11.Z, T11.X, 1, 1,
+; EG-NEXT: AND_INT * T11.X, T11.X, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T11.Y, 0.0,
+; EG-NEXT: MOV T12.W, 0.0,
+; EG-NEXT: MOV * T13.W, 0.0,
+; EG-NEXT: MOV T14.W, 0.0,
+; EG-NEXT: MOV * T15.W, 0.0,
+; EG-NEXT: MOV T16.W, 0.0,
+; EG-NEXT: MOV * T17.W, 0.0,
+; EG-NEXT: MOV T18.W, 0.0,
+; EG-NEXT: MOV * T19.W, 0.0,
+; EG-NEXT: MOV T20.W, 0.0,
+; EG-NEXT: MOV * T21.W, 0.0,
+; EG-NEXT: MOV T22.W, 0.0,
+; EG-NEXT: MOV * T23.W, 0.0,
+; EG-NEXT: MOV T24.W, 0.0,
+; EG-NEXT: MOV * T25.W, 0.0,
+; EG-NEXT: MOV T26.W, 0.0,
+; EG-NEXT: MOV * T11.W, 0.0,
+; EG-NEXT: LSHR T27.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T28.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T29.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T30.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T31.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR * T32.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 122:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 96(1.345247e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T33.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43)
+; EG-NEXT: LSHR T34.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 128(1.793662e-43)
+; EG-NEXT: LSHR T35.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 144(2.017870e-43)
+; EG-NEXT: LSHR T36.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 160(2.242078e-43)
+; EG-NEXT: LSHR T37.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 176(2.466285e-43)
+; EG-NEXT: LSHR T38.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 192(2.690493e-43)
+; EG-NEXT: LSHR T39.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 208(2.914701e-43)
+; EG-NEXT: LSHR T40.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 224(3.138909e-43)
+; EG-NEXT: LSHR T41.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 240(3.363116e-43)
+; EG-NEXT: LSHR * T42.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <32 x i1>, ptr addrspace(4) %in
%ext = zext <32 x i1> %load to <32 x i64>
store <32 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v32i1_to_v32i64:
define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v32i1_to_v32i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshr_b32 s52, s4, 30
+; GFX6-NEXT: s_lshr_b32 s40, s4, 31
+; GFX6-NEXT: s_lshr_b32 s42, s4, 28
+; GFX6-NEXT: s_lshr_b32 s20, s4, 29
+; GFX6-NEXT: s_lshr_b32 s24, s4, 26
+; GFX6-NEXT: s_lshr_b32 s16, s4, 27
+; GFX6-NEXT: s_lshr_b32 s22, s4, 24
+; GFX6-NEXT: s_lshr_b32 s6, s4, 25
+; GFX6-NEXT: s_lshr_b32 s8, s4, 22
+; GFX6-NEXT: s_lshr_b32 s10, s4, 23
+; GFX6-NEXT: s_lshr_b32 s12, s4, 20
+; GFX6-NEXT: s_lshr_b32 s14, s4, 21
+; GFX6-NEXT: s_lshr_b32 s18, s4, 18
+; GFX6-NEXT: s_lshr_b32 s26, s4, 19
+; GFX6-NEXT: s_lshr_b32 s28, s4, 16
+; GFX6-NEXT: s_lshr_b32 s30, s4, 17
+; GFX6-NEXT: s_lshr_b32 s34, s4, 14
+; GFX6-NEXT: s_lshr_b32 s36, s4, 15
+; GFX6-NEXT: s_lshr_b32 s38, s4, 12
+; GFX6-NEXT: s_lshr_b32 s44, s4, 13
+; GFX6-NEXT: s_lshr_b32 s46, s4, 10
+; GFX6-NEXT: s_lshr_b32 s48, s4, 11
+; GFX6-NEXT: s_bfe_i64 s[50:51], s[4:5], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x10000
+; GFX6-NEXT: v_mov_b32_e32 v0, s50
+; GFX6-NEXT: v_mov_b32_e32 v1, s51
+; GFX6-NEXT: s_lshr_b32 s50, s4, 8
+; GFX6-NEXT: v_mov_b32_e32 v2, s52
+; GFX6-NEXT: v_mov_b32_e32 v3, s53
+; GFX6-NEXT: s_lshr_b32 s52, s4, 9
+; GFX6-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX6-NEXT: v_mov_b32_e32 v4, s40
+; GFX6-NEXT: v_mov_b32_e32 v5, s41
+; GFX6-NEXT: s_lshr_b32 s40, s4, 6
+; GFX6-NEXT: v_mov_b32_e32 v6, s42
+; GFX6-NEXT: v_mov_b32_e32 v7, s43
+; GFX6-NEXT: s_lshr_b32 s42, s4, 7
+; GFX6-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX6-NEXT: v_mov_b32_e32 v8, s20
+; GFX6-NEXT: v_mov_b32_e32 v9, s21
+; GFX6-NEXT: s_lshr_b32 s20, s4, 4
+; GFX6-NEXT: v_mov_b32_e32 v10, s24
+; GFX6-NEXT: v_mov_b32_e32 v11, s25
+; GFX6-NEXT: s_lshr_b32 s24, s4, 5
+; GFX6-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX6-NEXT: v_mov_b32_e32 v12, s16
+; GFX6-NEXT: v_mov_b32_e32 v13, s17
+; GFX6-NEXT: s_lshr_b32 s16, s4, 2
+; GFX6-NEXT: v_mov_b32_e32 v14, s22
+; GFX6-NEXT: v_mov_b32_e32 v15, s23
+; GFX6-NEXT: s_lshr_b32 s22, s4, 3
+; GFX6-NEXT: s_lshr_b32 s4, s4, 1
+; GFX6-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:240
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], off, s[0:3], 0 offset:224
+; GFX6-NEXT: buffer_store_dwordx4 v[10:13], off, s[0:3], 0 offset:208
+; GFX6-NEXT: v_mov_b32_e32 v16, s6
+; GFX6-NEXT: v_mov_b32_e32 v17, s7
+; GFX6-NEXT: buffer_store_dwordx4 v[14:17], off, s[0:3], 0 offset:192
+; GFX6-NEXT: s_waitcnt expcnt(3)
+; GFX6-NEXT: v_mov_b32_e32 v2, s8
+; GFX6-NEXT: v_mov_b32_e32 v3, s9
+; GFX6-NEXT: v_mov_b32_e32 v4, s10
+; GFX6-NEXT: v_mov_b32_e32 v5, s11
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:176
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, s12
+; GFX6-NEXT: v_mov_b32_e32 v3, s13
+; GFX6-NEXT: v_mov_b32_e32 v4, s14
+; GFX6-NEXT: v_mov_b32_e32 v5, s15
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:160
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, s18
+; GFX6-NEXT: v_mov_b32_e32 v3, s19
+; GFX6-NEXT: v_mov_b32_e32 v4, s26
+; GFX6-NEXT: v_mov_b32_e32 v5, s27
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:144
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, s28
+; GFX6-NEXT: v_mov_b32_e32 v3, s29
+; GFX6-NEXT: v_mov_b32_e32 v4, s30
+; GFX6-NEXT: v_mov_b32_e32 v5, s31
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:128
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, s34
+; GFX6-NEXT: v_mov_b32_e32 v3, s35
+; GFX6-NEXT: v_mov_b32_e32 v4, s36
+; GFX6-NEXT: v_mov_b32_e32 v5, s37
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:112
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, s38
+; GFX6-NEXT: v_mov_b32_e32 v3, s39
+; GFX6-NEXT: v_mov_b32_e32 v4, s44
+; GFX6-NEXT: v_mov_b32_e32 v5, s45
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:96
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, s46
+; GFX6-NEXT: v_mov_b32_e32 v3, s47
+; GFX6-NEXT: v_mov_b32_e32 v4, s48
+; GFX6-NEXT: v_mov_b32_e32 v5, s49
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:80
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, s50
+; GFX6-NEXT: v_mov_b32_e32 v3, s51
+; GFX6-NEXT: v_mov_b32_e32 v4, s52
+; GFX6-NEXT: v_mov_b32_e32 v5, s53
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:64
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, s40
+; GFX6-NEXT: v_mov_b32_e32 v3, s41
+; GFX6-NEXT: v_mov_b32_e32 v4, s42
+; GFX6-NEXT: v_mov_b32_e32 v5, s43
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:48
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, s20
+; GFX6-NEXT: v_mov_b32_e32 v3, s21
+; GFX6-NEXT: v_mov_b32_e32 v4, s24
+; GFX6-NEXT: v_mov_b32_e32 v5, s25
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:32
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, s16
+; GFX6-NEXT: v_mov_b32_e32 v3, s17
+; GFX6-NEXT: v_mov_b32_e32 v4, s22
+; GFX6-NEXT: v_mov_b32_e32 v5, s23
+; GFX6-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NEXT: v_mov_b32_e32 v3, s5
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v32i1_to_v32i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_lshr_b32 s10, s4, 22
+; GFX8-NEXT: s_lshr_b32 s12, s4, 23
+; GFX8-NEXT: s_lshr_b32 s14, s4, 20
+; GFX8-NEXT: s_lshr_b32 s16, s4, 21
+; GFX8-NEXT: s_lshr_b32 s18, s4, 18
+; GFX8-NEXT: s_lshr_b32 s20, s4, 19
+; GFX8-NEXT: s_lshr_b32 s22, s4, 16
+; GFX8-NEXT: s_lshr_b32 s24, s4, 17
+; GFX8-NEXT: s_lshr_b32 s6, s4, 24
+; GFX8-NEXT: s_bfe_i64 s[2:3], s[6:7], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[8:9], s[4:5], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX8-NEXT: v_mov_b32_e32 v11, s10
+; GFX8-NEXT: s_add_u32 s10, s0, 0xb0
+; GFX8-NEXT: v_mov_b32_e32 v12, s11
+; GFX8-NEXT: s_addc_u32 s11, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v16, s11
+; GFX8-NEXT: v_mov_b32_e32 v15, s10
+; GFX8-NEXT: s_add_u32 s10, s0, 0xa0
+; GFX8-NEXT: v_mov_b32_e32 v13, s12
+; GFX8-NEXT: v_mov_b32_e32 v14, s13
+; GFX8-NEXT: s_addc_u32 s11, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NEXT: v_mov_b32_e32 v16, s11
+; GFX8-NEXT: v_mov_b32_e32 v15, s10
+; GFX8-NEXT: s_add_u32 s10, s0, 0x90
+; GFX8-NEXT: v_mov_b32_e32 v11, s14
+; GFX8-NEXT: v_mov_b32_e32 v12, s15
+; GFX8-NEXT: v_mov_b32_e32 v13, s16
+; GFX8-NEXT: v_mov_b32_e32 v14, s17
+; GFX8-NEXT: s_addc_u32 s11, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NEXT: v_mov_b32_e32 v16, s11
+; GFX8-NEXT: v_mov_b32_e32 v15, s10
+; GFX8-NEXT: s_add_u32 s10, s0, 0x80
+; GFX8-NEXT: v_mov_b32_e32 v11, s18
+; GFX8-NEXT: v_mov_b32_e32 v12, s19
+; GFX8-NEXT: v_mov_b32_e32 v13, s20
+; GFX8-NEXT: v_mov_b32_e32 v14, s21
+; GFX8-NEXT: s_addc_u32 s11, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NEXT: v_mov_b32_e32 v16, s11
+; GFX8-NEXT: v_mov_b32_e32 v15, s10
+; GFX8-NEXT: s_add_u32 s10, s0, 0x70
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 14, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v10, 15, s4
+; GFX8-NEXT: v_mov_b32_e32 v11, s22
+; GFX8-NEXT: v_mov_b32_e32 v12, s23
+; GFX8-NEXT: v_mov_b32_e32 v13, s24
+; GFX8-NEXT: v_mov_b32_e32 v14, s25
+; GFX8-NEXT: s_addc_u32 s11, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v7, 12, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v8, 13, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v5, 10, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v6, 11, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v3, 8, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v4, 9, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 6, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 7, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 4, s4
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NEXT: v_lshrrev_b16_e64 v16, 5, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v20, 2, s4
+; GFX8-NEXT: v_bfe_i32 v11, v10, 0, 1
+; GFX8-NEXT: v_bfe_i32 v9, v9, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v14, s11
+; GFX8-NEXT: v_lshrrev_b16_e64 v21, 3, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v22, 1, s4
+; GFX8-NEXT: s_add_u32 s4, s0, 0x60
+; GFX8-NEXT: v_ashrrev_i32_e32 v12, 31, v11
+; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; GFX8-NEXT: v_mov_b32_e32 v13, s10
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[13:14], v[9:12]
+; GFX8-NEXT: v_bfe_i32 v7, v7, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v12, s5
+; GFX8-NEXT: v_bfe_i32 v9, v8, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v11, s4
+; GFX8-NEXT: s_add_u32 s4, s0, 0x50
+; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[11:12], v[7:10]
+; GFX8-NEXT: v_bfe_i32 v5, v5, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v10, s5
+; GFX8-NEXT: v_bfe_i32 v7, v6, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v9, s4
+; GFX8-NEXT: s_add_u32 s4, s0, 64
+; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7
+; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[5:8]
+; GFX8-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NEXT: v_bfe_i32 v5, v4, 0, 1
+; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NEXT: s_add_u32 s4, s0, 48
+; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[3:6]
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1
+; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX8-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[1:4]
+; GFX8-NEXT: s_add_u32 s4, s0, 32
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 1, s6
+; GFX8-NEXT: v_bfe_i32 v2, v1, 0, 1
+; GFX8-NEXT: v_bfe_i32 v18, v16, 0, 1
+; GFX8-NEXT: v_bfe_i32 v16, v0, 0, 1
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18
+; GFX8-NEXT: v_ashrrev_i32_e32 v17, 31, v16
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 16
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
+; GFX8-NEXT: v_bfe_i32 v20, v20, 0, 1
+; GFX8-NEXT: v_bfe_i32 v18, v22, 0, 1
+; GFX8-NEXT: v_bfe_i32 v22, v21, 0, 1
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_ashrrev_i32_e32 v23, 31, v22
+; GFX8-NEXT: v_ashrrev_i32_e32 v21, 31, v20
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[20:23]
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_lshrrev_b16_e64 v12, 6, s6
+; GFX8-NEXT: v_lshrrev_b16_e64 v13, 7, s6
+; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18
+; GFX8-NEXT: v_mov_b32_e32 v16, s8
+; GFX8-NEXT: v_mov_b32_e32 v17, s9
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_add_u32 s4, s0, 0xf0
+; GFX8-NEXT: v_bfe_i32 v14, v13, 0, 1
+; GFX8-NEXT: v_bfe_i32 v12, v12, 0, 1
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0xe0
+; GFX8-NEXT: v_lshrrev_b16_e64 v8, 4, s6
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 5, s6
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_bfe_i32 v10, v9, 0, 1
+; GFX8-NEXT: v_bfe_i32 v8, v8, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0xd0
+; GFX8-NEXT: v_lshrrev_b16_e64 v5, 2, s6
+; GFX8-NEXT: v_lshrrev_b16_e64 v6, 3, s6
+; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_bfe_i32 v6, v6, 0, 1
+; GFX8-NEXT: v_bfe_i32 v4, v5, 0, 1
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: s_add_u32 s0, s0, 0xc0
+; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v32i1_to_v32i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @24, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @22
+; EG-NEXT: ALU 92, @25, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 65, @118, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T26.XYZW, T42.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T40.XYZW, T41.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T27.XYZW, T34.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T39.XYZW, T24.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T28.XYZW, T23.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T38.XYZW, T22.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T29.XYZW, T21.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T37.XYZW, T20.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T30.XYZW, T19.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T36.XYZW, T18.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T31.XYZW, T17.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T16.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T32.XYZW, T15.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T35.XYZW, T14.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T33.XYZW, T13.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T25.XYZW, T12.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 22:
+; EG-NEXT: VTX_READ_32 T11.X, T11.X, 0, #1
+; EG-NEXT: ALU clause starting at 24:
+; EG-NEXT: MOV * T11.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 25:
+; EG-NEXT: LSHR T12.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T13.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T14.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T15.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T16.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T17.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: LSHR T18.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43)
+; EG-NEXT: LSHR T19.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 128(1.793662e-43)
+; EG-NEXT: LSHR T20.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 144(2.017870e-43)
+; EG-NEXT: LSHR T21.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 160(2.242078e-43)
+; EG-NEXT: LSHR T22.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 176(2.466285e-43)
+; EG-NEXT: LSHR T23.X, PV.W, literal.x,
+; EG-NEXT: LSHR T0.Y, T11.X, literal.y,
+; EG-NEXT: LSHR T0.Z, T11.X, literal.z,
+; EG-NEXT: LSHR * T0.W, T11.X, literal.w,
+; EG-NEXT: 2(2.802597e-45), 28(3.923636e-44)
+; EG-NEXT: 29(4.063766e-44), 24(3.363116e-44)
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,
+; EG-NEXT: 192(2.690493e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T24.X, PV.W, literal.x,
+; EG-NEXT: LSHR T1.Y, T11.X, literal.y,
+; EG-NEXT: LSHR T1.Z, T11.X, literal.z,
+; EG-NEXT: LSHR * T1.W, T11.X, literal.w,
+; EG-NEXT: 2(2.802597e-45), 25(3.503246e-44)
+; EG-NEXT: 20(2.802597e-44), 21(2.942727e-44)
+; EG-NEXT: LSHR * T2.W, T11.X, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T25.X, T11.X, 0.0, 1,
+; EG-NEXT: LSHR T2.Y, T11.X, literal.x,
+; EG-NEXT: ASHR T26.Z, T11.X, literal.y,
+; EG-NEXT: LSHR T3.W, T11.X, literal.z,
+; EG-NEXT: LSHR * T4.W, T11.X, literal.w,
+; EG-NEXT: 17(2.382207e-44), 31(4.344025e-44)
+; EG-NEXT: 27(3.783506e-44), 30(4.203895e-44)
+; EG-NEXT: BFE_INT T26.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T3.Y, T11.X, literal.x,
+; EG-NEXT: BFE_INT T27.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T3.W, T11.X, literal.y,
+; EG-NEXT: LSHR * T4.W, T11.X, literal.z,
+; EG-NEXT: 12(1.681558e-44), 23(3.222986e-44)
+; EG-NEXT: 26(3.643376e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T27.X, PS, 0.0, 1,
+; EG-NEXT: MOV T26.Y, PV.X,
+; EG-NEXT: BFE_INT T28.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T3.W, T11.X, literal.x,
+; EG-NEXT: LSHR * T4.W, T11.X, literal.y,
+; EG-NEXT: 19(2.662467e-44), 22(3.082857e-44)
+; EG-NEXT: BFE_INT T28.X, PS, 0.0, 1,
+; EG-NEXT: MOV T27.Y, PV.X,
+; EG-NEXT: BFE_INT T29.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T3.W, T11.X, literal.x,
+; EG-NEXT: LSHR * T4.W, T11.X, literal.y,
+; EG-NEXT: 15(2.101948e-44), 18(2.522337e-44)
+; EG-NEXT: BFE_INT T29.X, PS, 0.0, 1,
+; EG-NEXT: MOV T28.Y, PV.X,
+; EG-NEXT: BFE_INT T30.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T3.W, T11.X, literal.x,
+; EG-NEXT: LSHR * T4.W, T11.X, literal.y,
+; EG-NEXT: 11(1.541428e-44), 14(1.961818e-44)
+; EG-NEXT: BFE_INT T30.X, PS, 0.0, 1,
+; EG-NEXT: MOV T29.Y, PV.X,
+; EG-NEXT: BFE_INT T31.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T3.W, T11.X, literal.x,
+; EG-NEXT: LSHR * T4.W, T11.X, literal.y,
+; EG-NEXT: 7(9.809089e-45), 10(1.401298e-44)
+; EG-NEXT: BFE_INT T31.X, PS, 0.0, 1,
+; EG-NEXT: MOV T30.Y, PV.X,
+; EG-NEXT: BFE_INT T32.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T3.W, T11.X, literal.x,
+; EG-NEXT: LSHR * T4.W, T11.X, literal.y,
+; EG-NEXT: 3(4.203895e-45), 6(8.407791e-45)
+; EG-NEXT: ALU clause starting at 118:
+; EG-NEXT: BFE_INT T32.X, T4.W, 0.0, 1,
+; EG-NEXT: MOV T31.Y, T31.X,
+; EG-NEXT: BFE_INT T33.Z, T3.W, 0.0, 1, BS:VEC_120/SCL_212
+; EG-NEXT: LSHR T3.W, T11.X, 1, BS:VEC_120/SCL_212
+; EG-NEXT: LSHR * T4.W, T11.X, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T33.X, PS, 0.0, 1,
+; EG-NEXT: MOV T32.Y, PV.X,
+; EG-NEXT: BFE_INT T25.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T3.W, T11.X, literal.x,
+; EG-NEXT: ADD_INT * T4.W, KC0[2].Y, literal.y,
+; EG-NEXT: 5(7.006492e-45), 208(2.914701e-43)
+; EG-NEXT: LSHR T34.X, PS, literal.x,
+; EG-NEXT: MOV T33.Y, PV.X,
+; EG-NEXT: BFE_INT T35.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T3.W, T11.X, literal.y,
+; EG-NEXT: LSHR * T4.W, T11.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 9(1.261169e-44)
+; EG-NEXT: 4(5.605194e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T35.X, PS, 0.0, 1,
+; EG-NEXT: MOV T25.Y, T25.X,
+; EG-NEXT: BFE_INT T11.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T3.W, T11.X, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: LSHR * T4.W, T11.X, literal.y,
+; EG-NEXT: 13(1.821688e-44), 8(1.121039e-44)
+; EG-NEXT: BFE_INT T11.X, PS, 0.0, 1,
+; EG-NEXT: MOV T35.Y, PV.X,
+; EG-NEXT: BFE_INT T36.Z, PV.W, 0.0, 1,
+; EG-NEXT: MOV T25.W, T25.Z,
+; EG-NEXT: MOV * T33.W, T33.Z,
+; EG-NEXT: BFE_INT T36.X, T3.Y, 0.0, 1,
+; EG-NEXT: MOV T11.Y, PV.X,
+; EG-NEXT: BFE_INT T37.Z, T2.Y, 0.0, 1, BS:VEC_120/SCL_212
+; EG-NEXT: MOV T35.W, T35.Z,
+; EG-NEXT: MOV * T32.W, T32.Z,
+; EG-NEXT: BFE_INT T37.X, T2.W, 0.0, 1,
+; EG-NEXT: MOV T36.Y, PV.X,
+; EG-NEXT: BFE_INT T38.Z, T1.W, 0.0, 1, BS:VEC_120/SCL_212
+; EG-NEXT: MOV T11.W, T11.Z,
+; EG-NEXT: MOV * T31.W, T31.Z,
+; EG-NEXT: BFE_INT T38.X, T1.Z, 0.0, 1,
+; EG-NEXT: MOV T37.Y, PV.X,
+; EG-NEXT: BFE_INT T39.Z, T1.Y, 0.0, 1,
+; EG-NEXT: MOV T36.W, T36.Z, BS:VEC_120/SCL_212
+; EG-NEXT: MOV * T30.W, T30.Z,
+; EG-NEXT: BFE_INT T39.X, T0.W, 0.0, 1,
+; EG-NEXT: MOV T38.Y, PV.X,
+; EG-NEXT: BFE_INT T40.Z, T0.Z, 0.0, 1,
+; EG-NEXT: MOV T37.W, T37.Z, BS:VEC_120/SCL_212
+; EG-NEXT: MOV * T29.W, T29.Z,
+; EG-NEXT: BFE_INT T40.X, T0.Y, 0.0, 1,
+; EG-NEXT: MOV T39.Y, PV.X,
+; EG-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.x,
+; EG-NEXT: MOV T38.W, T38.Z,
+; EG-NEXT: MOV * T28.W, T28.Z,
+; EG-NEXT: 224(3.138909e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T41.X, PV.Z, literal.x,
+; EG-NEXT: MOV T40.Y, PV.X,
+; EG-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.y,
+; EG-NEXT: MOV T39.W, T39.Z,
+; EG-NEXT: MOV * T27.W, T27.Z,
+; EG-NEXT: 2(2.802597e-45), 240(3.363116e-43)
+; EG-NEXT: LSHR T42.X, PV.Z, literal.x,
+; EG-NEXT: MOV T40.W, T40.Z,
+; EG-NEXT: MOV * T26.W, T26.Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <32 x i1>, ptr addrspace(4) %in
%ext = sext <32 x i1> %load to <32 x i64>
store <32 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v64i1_to_v64i64:
define amdgpu_kernel void @constant_zextload_v64i1_to_v64i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_zextload_v64i1_to_v64i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_bfe_u32 s4, s2, 0x10003
+; GFX6-NEXT: s_bfe_u32 s5, s2, 0x10005
+; GFX6-NEXT: s_bfe_u32 s6, s2, 0x10007
+; GFX6-NEXT: s_bfe_u32 s10, s2, 0x10009
+; GFX6-NEXT: s_bfe_u32 s12, s2, 0x1000b
+; GFX6-NEXT: s_bfe_u32 s14, s2, 0x1000d
+; GFX6-NEXT: s_bfe_u32 s16, s2, 0x1000f
+; GFX6-NEXT: s_bfe_u32 s18, s2, 0x10011
+; GFX6-NEXT: s_bfe_u32 s20, s2, 0x10013
+; GFX6-NEXT: s_bfe_u32 s22, s2, 0x10015
+; GFX6-NEXT: s_bfe_u32 s24, s2, 0x10017
+; GFX6-NEXT: s_bfe_u32 s25, s2, 0x10019
+; GFX6-NEXT: s_bfe_u32 s26, s2, 0x1001b
+; GFX6-NEXT: s_bfe_u32 s27, s2, 0x1001d
+; GFX6-NEXT: s_lshr_b32 s28, s2, 31
+; GFX6-NEXT: s_bfe_u32 s29, s3, 0x10003
+; GFX6-NEXT: s_bfe_u32 s30, s3, 0x10005
+; GFX6-NEXT: s_bfe_u32 s31, s3, 0x10007
+; GFX6-NEXT: s_bfe_u32 s33, s3, 0x10009
+; GFX6-NEXT: s_bfe_u32 s34, s3, 0x1000b
+; GFX6-NEXT: s_bfe_u32 s35, s3, 0x1000d
+; GFX6-NEXT: s_bfe_u32 s36, s3, 0x1000f
+; GFX6-NEXT: s_bfe_u32 s37, s3, 0x10011
+; GFX6-NEXT: s_bfe_u32 s38, s3, 0x10013
+; GFX6-NEXT: s_bfe_u32 s39, s3, 0x10015
+; GFX6-NEXT: s_bfe_u32 s40, s3, 0x10017
+; GFX6-NEXT: s_bfe_u32 s41, s3, 0x10019
+; GFX6-NEXT: s_bfe_u32 s42, s3, 0x1001b
+; GFX6-NEXT: s_bfe_u32 s43, s3, 0x1001d
+; GFX6-NEXT: s_lshr_b32 s44, s3, 31
+; GFX6-NEXT: s_bfe_u32 s9, s3, 0x10001
+; GFX6-NEXT: s_bfe_u32 s7, s2, 0x10001
+; GFX6-NEXT: s_and_b32 s8, s2, 1
+; GFX6-NEXT: s_and_b32 s11, s3, 1
+; GFX6-NEXT: s_bfe_u32 s13, s2, 0x10002
+; GFX6-NEXT: s_bfe_u32 s15, s2, 0x10004
+; GFX6-NEXT: s_bfe_u32 s17, s2, 0x10006
+; GFX6-NEXT: s_bfe_u32 s19, s2, 0x10008
+; GFX6-NEXT: s_bfe_u32 s21, s2, 0x1000a
+; GFX6-NEXT: s_bfe_u32 s23, s2, 0x1000c
+; GFX6-NEXT: s_bfe_u32 s45, s2, 0x1000e
+; GFX6-NEXT: s_bfe_u32 s46, s2, 0x10010
+; GFX6-NEXT: s_bfe_u32 s47, s2, 0x10012
+; GFX6-NEXT: s_bfe_u32 s48, s2, 0x10014
+; GFX6-NEXT: s_bfe_u32 s49, s2, 0x10016
+; GFX6-NEXT: s_bfe_u32 s50, s2, 0x10018
+; GFX6-NEXT: s_bfe_u32 s51, s2, 0x1001a
+; GFX6-NEXT: s_bfe_u32 s52, s2, 0x1001c
+; GFX6-NEXT: s_bfe_u32 s53, s2, 0x1001e
+; GFX6-NEXT: s_bfe_u32 s54, s3, 0x10002
+; GFX6-NEXT: s_bfe_u32 s55, s3, 0x10004
+; GFX6-NEXT: s_bfe_u32 s56, s3, 0x10006
+; GFX6-NEXT: s_bfe_u32 s57, s3, 0x10008
+; GFX6-NEXT: s_bfe_u32 s58, s3, 0x1000a
+; GFX6-NEXT: s_bfe_u32 s59, s3, 0x1000c
+; GFX6-NEXT: s_bfe_u32 s60, s3, 0x1000e
+; GFX6-NEXT: s_bfe_u32 s61, s3, 0x10010
+; GFX6-NEXT: s_bfe_u32 s62, s3, 0x10012
+; GFX6-NEXT: s_bfe_u32 s63, s3, 0x10014
+; GFX6-NEXT: s_bfe_u32 s64, s3, 0x10016
+; GFX6-NEXT: s_bfe_u32 s65, s3, 0x10018
+; GFX6-NEXT: s_bfe_u32 s66, s3, 0x1001a
+; GFX6-NEXT: s_bfe_u32 s67, s3, 0x1001e
+; GFX6-NEXT: s_bfe_u32 s68, s3, 0x1001c
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NEXT: v_mov_b32_e32 v0, s67
+; GFX6-NEXT: v_mov_b32_e32 v2, s44
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:496
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s68
+; GFX6-NEXT: v_mov_b32_e32 v2, s43
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:480
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s66
+; GFX6-NEXT: v_mov_b32_e32 v2, s42
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:464
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s65
+; GFX6-NEXT: v_mov_b32_e32 v2, s41
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:448
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s64
+; GFX6-NEXT: v_mov_b32_e32 v2, s40
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:432
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s63
+; GFX6-NEXT: v_mov_b32_e32 v2, s39
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:416
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s62
+; GFX6-NEXT: v_mov_b32_e32 v2, s38
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:400
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s61
+; GFX6-NEXT: v_mov_b32_e32 v2, s37
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:384
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s60
+; GFX6-NEXT: v_mov_b32_e32 v2, s36
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:368
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s59
+; GFX6-NEXT: v_mov_b32_e32 v2, s35
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:352
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s58
+; GFX6-NEXT: v_mov_b32_e32 v2, s34
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:336
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s57
+; GFX6-NEXT: v_mov_b32_e32 v2, s33
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:320
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s56
+; GFX6-NEXT: v_mov_b32_e32 v2, s31
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:304
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s55
+; GFX6-NEXT: v_mov_b32_e32 v2, s30
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:288
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s54
+; GFX6-NEXT: v_mov_b32_e32 v2, s29
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:272
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s53
+; GFX6-NEXT: v_mov_b32_e32 v2, s28
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:240
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s52
+; GFX6-NEXT: v_mov_b32_e32 v2, s27
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:224
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s51
+; GFX6-NEXT: v_mov_b32_e32 v2, s26
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:208
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s50
+; GFX6-NEXT: v_mov_b32_e32 v2, s25
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:192
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s49
+; GFX6-NEXT: v_mov_b32_e32 v2, s24
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:176
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s48
+; GFX6-NEXT: v_mov_b32_e32 v2, s22
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:160
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s47
+; GFX6-NEXT: v_mov_b32_e32 v2, s20
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s46
+; GFX6-NEXT: v_mov_b32_e32 v2, s18
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s45
+; GFX6-NEXT: v_mov_b32_e32 v2, s16
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s23
+; GFX6-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s21
+; GFX6-NEXT: v_mov_b32_e32 v2, s12
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s19
+; GFX6-NEXT: v_mov_b32_e32 v2, s10
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s17
+; GFX6-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s15
+; GFX6-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s13
+; GFX6-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s11
+; GFX6-NEXT: v_mov_b32_e32 v2, s9
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:256
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_zextload_v64i1_to_v64i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: v_mov_b32_e32 v25, 1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 13, s2
+; GFX8-NEXT: v_and_b32_e32 v18, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 11, s2
+; GFX8-NEXT: v_and_b32_e32 v16, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 9, s2
+; GFX8-NEXT: v_and_b32_e32 v15, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 7, s2
+; GFX8-NEXT: v_and_b32_e32 v13, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 5, s2
+; GFX8-NEXT: v_and_b32_e32 v10, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 3, s2
+; GFX8-NEXT: v_mov_b32_e32 v11, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 14, s2
+; GFX8-NEXT: s_lshr_b32 s24, s3, 24
+; GFX8-NEXT: s_lshr_b32 s22, s2, 24
+; GFX8-NEXT: v_lshrrev_b16_e64 v19, 12, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v17, 10, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v14, 6, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v12, 4, s2
+; GFX8-NEXT: v_and_b32_e32 v8, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 2, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 1, s2
+; GFX8-NEXT: s_bfe_u32 s20, s2, 0x10018
+; GFX8-NEXT: s_bfe_u32 s21, s3, 0x10018
+; GFX8-NEXT: s_and_b32 s23, s3, 1
+; GFX8-NEXT: s_and_b32 s25, s2, 1
+; GFX8-NEXT: v_lshrrev_b16_e64 v4, 15, s2
+; GFX8-NEXT: s_bfe_u32 s26, s2, 0x10011
+; GFX8-NEXT: s_bfe_u32 s27, s2, 0x10010
+; GFX8-NEXT: s_bfe_u32 s28, s2, 0x10012
+; GFX8-NEXT: s_bfe_u32 s29, s2, 0x10013
+; GFX8-NEXT: s_bfe_u32 s30, s2, 0x10014
+; GFX8-NEXT: s_bfe_u32 s31, s2, 0x10015
+; GFX8-NEXT: s_bfe_u32 s33, s2, 0x10016
+; GFX8-NEXT: s_bfe_u32 s2, s2, 0x10017
+; GFX8-NEXT: s_bfe_u32 s34, s3, 0x10011
+; GFX8-NEXT: s_bfe_u32 s35, s3, 0x10010
+; GFX8-NEXT: s_bfe_u32 s36, s3, 0x10012
+; GFX8-NEXT: s_bfe_u32 s37, s3, 0x10013
+; GFX8-NEXT: s_bfe_u32 s38, s3, 0x10016
+; GFX8-NEXT: s_bfe_u32 s39, s3, 0x10017
+; GFX8-NEXT: s_bfe_u32 s40, s3, 0x10015
+; GFX8-NEXT: s_bfe_u32 s41, s3, 0x10014
+; GFX8-NEXT: s_add_u32 s4, s0, 0x1a0
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: s_add_u32 s6, s0, 0x1b0
+; GFX8-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NEXT: s_add_u32 s8, s0, 0x190
+; GFX8-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NEXT: s_add_u32 s10, s0, 0x180
+; GFX8-NEXT: s_addc_u32 s11, s1, 0
+; GFX8-NEXT: s_add_u32 s12, s0, 0xb0
+; GFX8-NEXT: s_addc_u32 s13, s1, 0
+; GFX8-NEXT: s_add_u32 s14, s0, 0xa0
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: s_add_u32 s16, s0, 0x90
+; GFX8-NEXT: s_addc_u32 s17, s1, 0
+; GFX8-NEXT: s_add_u32 s18, s0, 0x80
+; GFX8-NEXT: s_addc_u32 s19, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v6, 1, v1
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 13, s3
+; GFX8-NEXT: s_add_u32 s42, s0, 0x70
+; GFX8-NEXT: v_and_b32_e32 v7, 1, v1
+; GFX8-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v23, s42
+; GFX8-NEXT: v_lshrrev_b16_e64 v22, 14, s3
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NEXT: v_mov_b32_e32 v5, v1
+; GFX8-NEXT: v_mov_b32_e32 v24, s43
+; GFX8-NEXT: s_add_u32 s42, s0, 0x170
+; GFX8-NEXT: flat_store_dwordx4 v[23:24], v[2:5]
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v22
+; GFX8-NEXT: v_mov_b32_e32 v22, s42
+; GFX8-NEXT: v_lshrrev_b16_e64 v4, 15, s3
+; GFX8-NEXT: v_mov_b32_e32 v23, s43
+; GFX8-NEXT: v_lshrrev_b16_e64 v21, 6, s24
+; GFX8-NEXT: flat_store_dwordx4 v[22:23], v[2:5]
+; GFX8-NEXT: s_add_u32 s42, s0, 0x1f0
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 11, s3
+; GFX8-NEXT: v_and_b32_e32 v23, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v21
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v21, s42
+; GFX8-NEXT: v_lshrrev_b16_e64 v20, 6, s22
+; GFX8-NEXT: v_lshrrev_b16_e64 v4, 7, s24
+; GFX8-NEXT: v_mov_b32_e32 v22, s43
+; GFX8-NEXT: s_add_u32 s42, s0, 0xf0
+; GFX8-NEXT: flat_store_dwordx4 v[21:22], v[2:5]
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v20
+; GFX8-NEXT: v_mov_b32_e32 v20, s42
+; GFX8-NEXT: v_lshrrev_b16_e64 v4, 7, s22
+; GFX8-NEXT: v_mov_b32_e32 v21, s43
+; GFX8-NEXT: flat_store_dwordx4 v[20:21], v[2:5]
+; GFX8-NEXT: s_add_u32 s42, s0, 0x60
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 9, s3
+; GFX8-NEXT: v_and_b32_e32 v20, 1, v2
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 7, s3
+; GFX8-NEXT: v_and_b32_e32 v21, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v19
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v18
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v18, s42
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v19, s43
+; GFX8-NEXT: flat_store_dwordx4 v[18:19], v[2:5]
+; GFX8-NEXT: s_add_u32 s42, s0, 0x50
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 5, s3
+; GFX8-NEXT: v_and_b32_e32 v19, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v17
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v16
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v16, s42
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v17, s43
+; GFX8-NEXT: s_add_u32 s42, s0, 64
+; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[2:5]
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v15
+; GFX8-NEXT: v_mov_b32_e32 v15, s42
+; GFX8-NEXT: v_and_b32_sdwa v2, v11, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v16, s43
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[2:5]
+; GFX8-NEXT: s_add_u32 s42, s0, 48
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 3, s3
+; GFX8-NEXT: v_and_b32_e32 v15, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v14
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v13
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v13, s42
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v14, s43
+; GFX8-NEXT: flat_store_dwordx4 v[13:14], v[2:5]
+; GFX8-NEXT: s_add_u32 s42, s0, 32
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 1, s3
+; GFX8-NEXT: v_and_b32_e32 v26, 1, v2
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 5, s24
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v10
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v10, s42
+; GFX8-NEXT: v_and_b32_e32 v27, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v12
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v11, s43
+; GFX8-NEXT: flat_store_dwordx4 v[10:11], v[2:5]
+; GFX8-NEXT: s_add_u32 s42, s0, 16
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 3, s24
+; GFX8-NEXT: v_and_b32_e32 v29, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v9
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v8
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v8, s42
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v9, s43
+; GFX8-NEXT: s_add_u32 s42, s0, 0x160
+; GFX8-NEXT: v_lshrrev_b16_e64 v24, 12, s3
+; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[2:5]
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 1, s24
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v7
+; GFX8-NEXT: v_mov_b32_e32 v7, s42
+; GFX8-NEXT: v_and_b32_e32 v13, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v24
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v8, s43
+; GFX8-NEXT: s_add_u32 s42, s0, 0x150
+; GFX8-NEXT: v_lshrrev_b16_e64 v22, 10, s3
+; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[2:5]
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 5, s22
+; GFX8-NEXT: v_mov_b32_e32 v7, s42
+; GFX8-NEXT: v_and_b32_e32 v14, 1, v2
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v22
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v23
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v8, s43
+; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[2:5]
+; GFX8-NEXT: s_add_u32 s42, s0, 0x140
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 3, s22
+; GFX8-NEXT: v_and_b32_e32 v9, 1, v2
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 1, s22
+; GFX8-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v2
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v7, s42
+; GFX8-NEXT: v_and_b32_e32 v23, 0xffff, v2
+; GFX8-NEXT: v_and_b32_sdwa v2, v0, v25 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v20
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v8, s43
+; GFX8-NEXT: s_add_u32 s42, s0, 0x130
+; GFX8-NEXT: v_lshrrev_b16_e64 v18, 6, s3
+; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[2:5]
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v7, s42
+; GFX8-NEXT: v_and_b32_e32 v2, 1, v18
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v21
+; GFX8-NEXT: v_mov_b32_e32 v5, 0
+; GFX8-NEXT: v_mov_b32_e32 v8, s43
+; GFX8-NEXT: s_add_u32 s42, s0, 0x120
+; GFX8-NEXT: v_lshrrev_b16_e64 v17, 4, s3
+; GFX8-NEXT: v_lshrrev_b16_e64 v10, 2, s22
+; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[2:5]
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s42
+; GFX8-NEXT: v_and_b32_e32 v5, 1, v10
+; GFX8-NEXT: v_and_b32_e32 v7, 0xffff, v9
+; GFX8-NEXT: v_and_b32_e32 v9, 1, v17
+; GFX8-NEXT: v_and_b32_e32 v11, 0xffff, v19
+; GFX8-NEXT: v_mov_b32_e32 v12, 0
+; GFX8-NEXT: v_mov_b32_e32 v10, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, s43
+; GFX8-NEXT: s_add_u32 s42, s0, 0x110
+; GFX8-NEXT: v_lshrrev_b16_e64 v16, 2, s3
+; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[9:12]
+; GFX8-NEXT: s_addc_u32 s43, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s42
+; GFX8-NEXT: v_and_b32_e32 v11, 0xffff, v14
+; GFX8-NEXT: v_and_b32_e32 v4, 0xffff, v13
+; GFX8-NEXT: v_and_b32_e32 v13, 1, v16
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff, v15
+; GFX8-NEXT: v_mov_b32_e32 v16, 0
+; GFX8-NEXT: v_mov_b32_e32 v14, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, s43
+; GFX8-NEXT: v_mov_b32_e32 v22, s5
+; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[13:16]
+; GFX8-NEXT: v_mov_b32_e32 v0, s41
+; GFX8-NEXT: v_mov_b32_e32 v2, s40
+; GFX8-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NEXT: v_mov_b32_e32 v21, s4
+; GFX8-NEXT: flat_store_dwordx4 v[21:22], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v22, s7
+; GFX8-NEXT: v_mov_b32_e32 v0, s38
+; GFX8-NEXT: v_mov_b32_e32 v2, s39
+; GFX8-NEXT: v_mov_b32_e32 v21, s6
+; GFX8-NEXT: flat_store_dwordx4 v[21:22], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v22, s9
+; GFX8-NEXT: v_mov_b32_e32 v0, s36
+; GFX8-NEXT: v_mov_b32_e32 v2, s37
+; GFX8-NEXT: v_mov_b32_e32 v21, s8
+; GFX8-NEXT: flat_store_dwordx4 v[21:22], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v22, s11
+; GFX8-NEXT: v_mov_b32_e32 v0, s35
+; GFX8-NEXT: v_mov_b32_e32 v2, s34
+; GFX8-NEXT: v_mov_b32_e32 v21, s10
+; GFX8-NEXT: flat_store_dwordx4 v[21:22], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v22, s13
+; GFX8-NEXT: v_mov_b32_e32 v0, s33
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v21, s12
+; GFX8-NEXT: flat_store_dwordx4 v[21:22], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v22, s15
+; GFX8-NEXT: v_mov_b32_e32 v0, s30
+; GFX8-NEXT: v_mov_b32_e32 v2, s31
+; GFX8-NEXT: v_mov_b32_e32 v21, s14
+; GFX8-NEXT: flat_store_dwordx4 v[21:22], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v22, s17
+; GFX8-NEXT: v_mov_b32_e32 v0, s28
+; GFX8-NEXT: v_mov_b32_e32 v2, s29
+; GFX8-NEXT: v_mov_b32_e32 v21, s16
+; GFX8-NEXT: flat_store_dwordx4 v[21:22], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v22, s19
+; GFX8-NEXT: v_mov_b32_e32 v0, s27
+; GFX8-NEXT: v_mov_b32_e32 v2, s26
+; GFX8-NEXT: v_mov_b32_e32 v21, s18
+; GFX8-NEXT: flat_store_dwordx4 v[21:22], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v22, s1
+; GFX8-NEXT: s_add_u32 s2, s0, 0x100
+; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v6
+; GFX8-NEXT: v_mov_b32_e32 v3, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s25
+; GFX8-NEXT: v_mov_b32_e32 v21, s0
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_and_b32_e32 v14, 0xffff, v26
+; GFX8-NEXT: v_mov_b32_e32 v18, 0
+; GFX8-NEXT: flat_store_dwordx4 v[21:22], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v22, s3
+; GFX8-NEXT: v_mov_b32_e32 v0, s23
+; GFX8-NEXT: v_mov_b32_e32 v2, v14
+; GFX8-NEXT: v_mov_b32_e32 v3, v18
+; GFX8-NEXT: v_mov_b32_e32 v21, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 0x1e0
+; GFX8-NEXT: v_lshrrev_b16_e64 v28, 4, s24
+; GFX8-NEXT: flat_store_dwordx4 v[21:22], v[0:3]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_and_b32_e32 v17, 1, v28
+; GFX8-NEXT: v_and_b32_e32 v19, 0xffff, v27
+; GFX8-NEXT: v_mov_b32_e32 v20, 0
+; GFX8-NEXT: v_mov_b32_e32 v18, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0x1d0
+; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[17:20]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v30, 2, s24
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0x1c0
+; GFX8-NEXT: v_and_b32_e32 v13, 1, v30
+; GFX8-NEXT: v_and_b32_e32 v15, 0xffff, v29
+; GFX8-NEXT: v_mov_b32_e32 v16, 0
+; GFX8-NEXT: v_mov_b32_e32 v14, v1
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v10, 0
+; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[13:16]
+; GFX8-NEXT: v_mov_b32_e32 v0, s21
+; GFX8-NEXT: v_mov_b32_e32 v14, s3
+; GFX8-NEXT: v_mov_b32_e32 v2, v4
+; GFX8-NEXT: v_mov_b32_e32 v3, v10
+; GFX8-NEXT: v_mov_b32_e32 v13, s2
+; GFX8-NEXT: s_add_u32 s2, s0, 0xe0
+; GFX8-NEXT: flat_store_dwordx4 v[13:14], v[0:3]
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_lshrrev_b16_e64 v24, 4, s22
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: s_add_u32 s2, s0, 0xd0
+; GFX8-NEXT: v_and_b32_e32 v9, 1, v24
+; GFX8-NEXT: v_mov_b32_e32 v12, 0
+; GFX8-NEXT: v_mov_b32_e32 v10, v1
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[9:12]
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: s_add_u32 s0, s0, 0xc0
+; GFX8-NEXT: v_mov_b32_e32 v8, 0
+; GFX8-NEXT: v_mov_b32_e32 v6, v1
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v25, 0
+; GFX8-NEXT: flat_store_dwordx4 v[2:3], v[5:8]
+; GFX8-NEXT: v_mov_b32_e32 v0, s20
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, v23
+; GFX8-NEXT: v_mov_b32_e32 v3, v25
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v64i1_to_v64i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @40, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @38
+; EG-NEXT: ALU 95, @41, KC0[], KC1[]
+; EG-NEXT: ALU 99, @137, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 60, @237, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T82.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T21.XYZW, T81.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T22.XYZW, T80.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T23.XYZW, T79.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T24.XYZW, T78.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T25.XYZW, T77.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T26.XYZW, T76.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T27.XYZW, T75.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T28.XYZW, T74.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T29.XYZW, T73.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T30.XYZW, T72.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T31.XYZW, T71.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T32.XYZW, T70.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T33.XYZW, T69.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T34.XYZW, T68.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T35.XYZW, T67.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T36.XYZW, T66.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T37.XYZW, T65.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T38.XYZW, T64.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T39.XYZW, T63.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T40.XYZW, T62.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T41.XYZW, T61.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T42.XYZW, T60.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T43.XYZW, T59.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T44.XYZW, T58.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T45.XYZW, T57.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T46.XYZW, T56.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T47.XYZW, T55.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T48.XYZW, T54.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T49.XYZW, T53.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T50.XYZW, T52.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T51.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 38:
+; EG-NEXT: VTX_READ_64 T19.XY, T19.X, 0, #1
+; EG-NEXT: ALU clause starting at 40:
+; EG-NEXT: MOV * T19.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 41:
+; EG-NEXT: LSHR * T20.Z, T19.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T20.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T20.Y, 0.0,
+; EG-NEXT: BFE_UINT * T21.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 30(4.203895e-44), 29(4.063766e-44)
+; EG-NEXT: BFE_UINT T21.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T21.Y, 0.0,
+; EG-NEXT: BFE_UINT * T22.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 28(3.923636e-44), 27(3.783506e-44)
+; EG-NEXT: BFE_UINT T22.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T22.Y, 0.0,
+; EG-NEXT: BFE_UINT * T23.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 26(3.643376e-44), 25(3.503246e-44)
+; EG-NEXT: BFE_UINT T23.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T23.Y, 0.0,
+; EG-NEXT: BFE_UINT * T24.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 24(3.363116e-44), 23(3.222986e-44)
+; EG-NEXT: BFE_UINT T24.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T24.Y, 0.0,
+; EG-NEXT: BFE_UINT * T25.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 22(3.082857e-44), 21(2.942727e-44)
+; EG-NEXT: BFE_UINT T25.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T25.Y, 0.0,
+; EG-NEXT: BFE_UINT * T26.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 20(2.802597e-44), 19(2.662467e-44)
+; EG-NEXT: BFE_UINT T26.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T26.Y, 0.0,
+; EG-NEXT: BFE_UINT * T27.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 18(2.522337e-44), 17(2.382207e-44)
+; EG-NEXT: BFE_UINT T27.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T27.Y, 0.0,
+; EG-NEXT: BFE_UINT * T28.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 16(2.242078e-44), 15(2.101948e-44)
+; EG-NEXT: BFE_UINT T28.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T28.Y, 0.0,
+; EG-NEXT: BFE_UINT * T29.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 14(1.961818e-44), 13(1.821688e-44)
+; EG-NEXT: BFE_UINT T29.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T29.Y, 0.0,
+; EG-NEXT: BFE_UINT * T30.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 12(1.681558e-44), 11(1.541428e-44)
+; EG-NEXT: BFE_UINT T30.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T30.Y, 0.0,
+; EG-NEXT: BFE_UINT * T31.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 10(1.401298e-44), 9(1.261169e-44)
+; EG-NEXT: BFE_UINT T31.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T31.Y, 0.0,
+; EG-NEXT: BFE_UINT * T32.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 8(1.121039e-44), 7(9.809089e-45)
+; EG-NEXT: BFE_UINT T32.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T32.Y, 0.0,
+; EG-NEXT: BFE_UINT * T33.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 6(8.407791e-45), 5(7.006492e-45)
+; EG-NEXT: BFE_UINT T33.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T33.Y, 0.0,
+; EG-NEXT: BFE_UINT * T34.Z, T19.Y, literal.y, 1,
+; EG-NEXT: 4(5.605194e-45), 3(4.203895e-45)
+; EG-NEXT: BFE_UINT T34.X, T19.Y, literal.x, 1,
+; EG-NEXT: MOV T34.Y, 0.0,
+; EG-NEXT: BFE_UINT T35.Z, T19.Y, 1, 1,
+; EG-NEXT: AND_INT * T35.X, T19.Y, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T35.Y, 0.0,
+; EG-NEXT: LSHR * T36.Z, T19.X, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T36.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T36.Y, 0.0,
+; EG-NEXT: BFE_UINT * T37.Z, T19.X, literal.y, 1,
+; EG-NEXT: 30(4.203895e-44), 29(4.063766e-44)
+; EG-NEXT: BFE_UINT T37.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T37.Y, 0.0,
+; EG-NEXT: BFE_UINT * T38.Z, T19.X, literal.y, 1,
+; EG-NEXT: 28(3.923636e-44), 27(3.783506e-44)
+; EG-NEXT: BFE_UINT T38.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T38.Y, 0.0,
+; EG-NEXT: BFE_UINT * T39.Z, T19.X, literal.y, 1,
+; EG-NEXT: 26(3.643376e-44), 25(3.503246e-44)
+; EG-NEXT: BFE_UINT T39.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T39.Y, 0.0,
+; EG-NEXT: BFE_UINT * T40.Z, T19.X, literal.y, 1,
+; EG-NEXT: 24(3.363116e-44), 23(3.222986e-44)
+; EG-NEXT: BFE_UINT T40.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T40.Y, 0.0,
+; EG-NEXT: BFE_UINT * T41.Z, T19.X, literal.y, 1,
+; EG-NEXT: 22(3.082857e-44), 21(2.942727e-44)
+; EG-NEXT: BFE_UINT T41.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T41.Y, 0.0,
+; EG-NEXT: BFE_UINT * T42.Z, T19.X, literal.y, 1,
+; EG-NEXT: 20(2.802597e-44), 19(2.662467e-44)
+; EG-NEXT: BFE_UINT T42.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T42.Y, 0.0,
+; EG-NEXT: BFE_UINT * T43.Z, T19.X, literal.y, 1,
+; EG-NEXT: 18(2.522337e-44), 17(2.382207e-44)
+; EG-NEXT: BFE_UINT * T43.X, T19.X, literal.x, 1,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 137:
+; EG-NEXT: MOV T43.Y, 0.0,
+; EG-NEXT: BFE_UINT * T44.Z, T19.X, literal.x, 1,
+; EG-NEXT: 15(2.101948e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T44.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T44.Y, 0.0,
+; EG-NEXT: BFE_UINT * T45.Z, T19.X, literal.y, 1,
+; EG-NEXT: 14(1.961818e-44), 13(1.821688e-44)
+; EG-NEXT: BFE_UINT T45.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T45.Y, 0.0,
+; EG-NEXT: BFE_UINT * T46.Z, T19.X, literal.y, 1,
+; EG-NEXT: 12(1.681558e-44), 11(1.541428e-44)
+; EG-NEXT: BFE_UINT T46.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T46.Y, 0.0,
+; EG-NEXT: BFE_UINT * T47.Z, T19.X, literal.y, 1,
+; EG-NEXT: 10(1.401298e-44), 9(1.261169e-44)
+; EG-NEXT: BFE_UINT T47.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T47.Y, 0.0,
+; EG-NEXT: BFE_UINT * T48.Z, T19.X, literal.y, 1,
+; EG-NEXT: 8(1.121039e-44), 7(9.809089e-45)
+; EG-NEXT: BFE_UINT T48.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T48.Y, 0.0,
+; EG-NEXT: BFE_UINT * T49.Z, T19.X, literal.y, 1,
+; EG-NEXT: 6(8.407791e-45), 5(7.006492e-45)
+; EG-NEXT: BFE_UINT T49.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T49.Y, 0.0,
+; EG-NEXT: BFE_UINT * T50.Z, T19.X, literal.y, 1,
+; EG-NEXT: 4(5.605194e-45), 3(4.203895e-45)
+; EG-NEXT: BFE_UINT T50.X, T19.X, literal.x, 1,
+; EG-NEXT: MOV T50.Y, 0.0,
+; EG-NEXT: BFE_UINT T19.Z, T19.X, 1, 1,
+; EG-NEXT: AND_INT * T19.X, T19.X, 1,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T19.Y, 0.0,
+; EG-NEXT: MOV T20.W, 0.0,
+; EG-NEXT: MOV * T21.W, 0.0,
+; EG-NEXT: MOV T22.W, 0.0,
+; EG-NEXT: MOV * T23.W, 0.0,
+; EG-NEXT: MOV T24.W, 0.0,
+; EG-NEXT: MOV * T25.W, 0.0,
+; EG-NEXT: MOV T26.W, 0.0,
+; EG-NEXT: MOV * T27.W, 0.0,
+; EG-NEXT: MOV T28.W, 0.0,
+; EG-NEXT: MOV * T29.W, 0.0,
+; EG-NEXT: MOV T30.W, 0.0,
+; EG-NEXT: MOV * T31.W, 0.0,
+; EG-NEXT: MOV T32.W, 0.0,
+; EG-NEXT: MOV * T33.W, 0.0,
+; EG-NEXT: MOV T34.W, 0.0,
+; EG-NEXT: MOV * T35.W, 0.0,
+; EG-NEXT: MOV T36.W, 0.0,
+; EG-NEXT: MOV * T37.W, 0.0,
+; EG-NEXT: MOV T38.W, 0.0,
+; EG-NEXT: MOV * T39.W, 0.0,
+; EG-NEXT: MOV T40.W, 0.0,
+; EG-NEXT: MOV * T41.W, 0.0,
+; EG-NEXT: MOV T42.W, 0.0,
+; EG-NEXT: MOV * T43.W, 0.0,
+; EG-NEXT: MOV T44.W, 0.0,
+; EG-NEXT: MOV * T45.W, 0.0,
+; EG-NEXT: MOV T46.W, 0.0,
+; EG-NEXT: MOV * T47.W, 0.0,
+; EG-NEXT: MOV T48.W, 0.0,
+; EG-NEXT: MOV * T49.W, 0.0,
+; EG-NEXT: MOV T50.W, 0.0,
+; EG-NEXT: MOV * T19.W, 0.0,
+; EG-NEXT: LSHR T51.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T52.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T53.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T54.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T55.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T56.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: LSHR T57.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43)
+; EG-NEXT: LSHR T58.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 128(1.793662e-43)
+; EG-NEXT: LSHR T59.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 144(2.017870e-43)
+; EG-NEXT: LSHR T60.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 160(2.242078e-43)
+; EG-NEXT: LSHR T61.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 176(2.466285e-43)
+; EG-NEXT: LSHR * T62.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 237:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 192(2.690493e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T63.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 208(2.914701e-43)
+; EG-NEXT: LSHR T64.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 224(3.138909e-43)
+; EG-NEXT: LSHR T65.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 240(3.363116e-43)
+; EG-NEXT: LSHR T66.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 256(3.587324e-43)
+; EG-NEXT: LSHR T67.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 272(3.811532e-43)
+; EG-NEXT: LSHR T68.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 288(4.035740e-43)
+; EG-NEXT: LSHR T69.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 304(4.259947e-43)
+; EG-NEXT: LSHR T70.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 320(4.484155e-43)
+; EG-NEXT: LSHR T71.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 336(4.708363e-43)
+; EG-NEXT: LSHR T72.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 352(4.932571e-43)
+; EG-NEXT: LSHR T73.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 368(5.156778e-43)
+; EG-NEXT: LSHR T74.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 384(5.380986e-43)
+; EG-NEXT: LSHR T75.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 400(5.605194e-43)
+; EG-NEXT: LSHR T76.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 416(5.829402e-43)
+; EG-NEXT: LSHR T77.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 432(6.053609e-43)
+; EG-NEXT: LSHR T78.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 448(6.277817e-43)
+; EG-NEXT: LSHR T79.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 464(6.502025e-43)
+; EG-NEXT: LSHR T80.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 480(6.726233e-43)
+; EG-NEXT: LSHR T81.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 496(6.950440e-43)
+; EG-NEXT: LSHR * T82.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <64 x i1>, ptr addrspace(4) %in
%ext = zext <64 x i1> %load to <64 x i64>
store <64 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v64i1_to_v64i64:
define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(ptr addrspace(1) %out, ptr addrspace(4) nocapture %in) #0 {
+; GFX6-LABEL: constant_sextload_v64i1_to_v64i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_lshr_b32 s48, s5, 30
+; GFX6-NEXT: s_lshr_b32 s46, s5, 28
+; GFX6-NEXT: s_lshr_b32 s42, s5, 29
+; GFX6-NEXT: s_lshr_b32 s38, s5, 26
+; GFX6-NEXT: s_lshr_b32 s44, s5, 27
+; GFX6-NEXT: s_lshr_b32 s36, s5, 24
+; GFX6-NEXT: s_lshr_b32 s40, s5, 25
+; GFX6-NEXT: s_lshr_b32 s30, s5, 22
+; GFX6-NEXT: s_lshr_b32 s34, s5, 23
+; GFX6-NEXT: s_lshr_b32 s26, s5, 20
+; GFX6-NEXT: s_lshr_b32 s28, s5, 21
+; GFX6-NEXT: s_lshr_b32 s22, s5, 18
+; GFX6-NEXT: s_lshr_b32 s24, s5, 19
+; GFX6-NEXT: s_lshr_b32 s18, s5, 16
+; GFX6-NEXT: s_lshr_b32 s20, s5, 17
+; GFX6-NEXT: s_lshr_b32 s14, s5, 14
+; GFX6-NEXT: s_lshr_b32 s16, s5, 15
+; GFX6-NEXT: s_lshr_b32 s10, s5, 12
+; GFX6-NEXT: s_lshr_b32 s12, s5, 13
+; GFX6-NEXT: s_lshr_b32 s6, s5, 10
+; GFX6-NEXT: s_lshr_b32 s8, s5, 11
+; GFX6-NEXT: s_mov_b32 s50, s5
+; GFX6-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[52:53], s[4:5], 0x10000
+; GFX6-NEXT: v_mov_b32_e32 v0, s50
+; GFX6-NEXT: v_mov_b32_e32 v1, s51
+; GFX6-NEXT: s_lshr_b32 s50, s5, 8
+; GFX6-NEXT: v_mov_b32_e32 v4, s52
+; GFX6-NEXT: v_mov_b32_e32 v5, s53
+; GFX6-NEXT: s_lshr_b32 s52, s5, 9
+; GFX6-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
+; GFX6-NEXT: v_mov_b32_e32 v6, s48
+; GFX6-NEXT: v_mov_b32_e32 v7, s49
+; GFX6-NEXT: s_lshr_b32 s48, s5, 6
+; GFX6-NEXT: v_mov_b32_e32 v10, s46
+; GFX6-NEXT: v_mov_b32_e32 v11, s47
+; GFX6-NEXT: s_lshr_b32 s46, s5, 7
+; GFX6-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX6-NEXT: s_ashr_i32 s7, s5, 31
+; GFX6-NEXT: v_mov_b32_e32 v12, s42
+; GFX6-NEXT: v_mov_b32_e32 v13, s43
+; GFX6-NEXT: s_lshr_b32 s42, s5, 4
+; GFX6-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
+; GFX6-NEXT: v_mov_b32_e32 v14, s38
+; GFX6-NEXT: v_mov_b32_e32 v15, s39
+; GFX6-NEXT: s_lshr_b32 s54, s5, 5
+; GFX6-NEXT: v_mov_b32_e32 v16, s44
+; GFX6-NEXT: v_mov_b32_e32 v17, s45
+; GFX6-NEXT: s_lshr_b32 s38, s5, 2
+; GFX6-NEXT: v_mov_b32_e32 v8, s7
+; GFX6-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
+; GFX6-NEXT: v_mov_b32_e32 v9, s7
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], off, s[0:3], 0 offset:496
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v6, s36
+; GFX6-NEXT: v_mov_b32_e32 v7, s37
+; GFX6-NEXT: s_lshr_b32 s36, s5, 3
+; GFX6-NEXT: v_mov_b32_e32 v8, s40
+; GFX6-NEXT: v_mov_b32_e32 v9, s41
+; GFX6-NEXT: s_lshr_b32 s40, s5, 1
+; GFX6-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[10:13], off, s[0:3], 0 offset:480
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v10, s30
+; GFX6-NEXT: v_mov_b32_e32 v11, s31
+; GFX6-NEXT: s_lshr_b32 s30, s4, 30
+; GFX6-NEXT: v_mov_b32_e32 v12, s34
+; GFX6-NEXT: v_mov_b32_e32 v13, s35
+; GFX6-NEXT: s_lshr_b32 s34, s4, 31
+; GFX6-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[14:17], off, s[0:3], 0 offset:464
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v14, s26
+; GFX6-NEXT: v_mov_b32_e32 v15, s27
+; GFX6-NEXT: s_lshr_b32 s26, s4, 28
+; GFX6-NEXT: v_mov_b32_e32 v16, s28
+; GFX6-NEXT: v_mov_b32_e32 v17, s29
+; GFX6-NEXT: s_lshr_b32 s28, s4, 29
+; GFX6-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], off, s[0:3], 0 offset:448
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v6, s22
+; GFX6-NEXT: v_mov_b32_e32 v7, s23
+; GFX6-NEXT: s_lshr_b32 s22, s4, 26
+; GFX6-NEXT: v_mov_b32_e32 v8, s24
+; GFX6-NEXT: v_mov_b32_e32 v9, s25
+; GFX6-NEXT: s_lshr_b32 s24, s4, 27
+; GFX6-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[10:13], off, s[0:3], 0 offset:432
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v10, s18
+; GFX6-NEXT: v_mov_b32_e32 v11, s19
+; GFX6-NEXT: s_lshr_b32 s44, s4, 24
+; GFX6-NEXT: v_mov_b32_e32 v12, s20
+; GFX6-NEXT: v_mov_b32_e32 v13, s21
+; GFX6-NEXT: s_lshr_b32 s18, s4, 25
+; GFX6-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[14:17], off, s[0:3], 0 offset:416
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v14, s14
+; GFX6-NEXT: v_mov_b32_e32 v15, s15
+; GFX6-NEXT: s_lshr_b32 s14, s4, 22
+; GFX6-NEXT: v_mov_b32_e32 v16, s16
+; GFX6-NEXT: v_mov_b32_e32 v17, s17
+; GFX6-NEXT: s_lshr_b32 s16, s4, 23
+; GFX6-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], off, s[0:3], 0 offset:400
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v6, s10
+; GFX6-NEXT: v_mov_b32_e32 v7, s11
+; GFX6-NEXT: s_lshr_b32 s10, s4, 20
+; GFX6-NEXT: v_mov_b32_e32 v8, s12
+; GFX6-NEXT: v_mov_b32_e32 v9, s13
+; GFX6-NEXT: s_lshr_b32 s12, s4, 21
+; GFX6-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[10:13], off, s[0:3], 0 offset:384
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v10, s6
+; GFX6-NEXT: v_mov_b32_e32 v11, s7
+; GFX6-NEXT: s_lshr_b32 s6, s4, 18
+; GFX6-NEXT: v_mov_b32_e32 v12, s8
+; GFX6-NEXT: v_mov_b32_e32 v13, s9
+; GFX6-NEXT: s_lshr_b32 s8, s4, 19
+; GFX6-NEXT: s_bfe_i64 s[20:21], s[52:53], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[14:17], off, s[0:3], 0 offset:368
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v14, s50
+; GFX6-NEXT: v_mov_b32_e32 v15, s51
+; GFX6-NEXT: s_lshr_b32 s50, s4, 16
+; GFX6-NEXT: v_mov_b32_e32 v16, s20
+; GFX6-NEXT: v_mov_b32_e32 v17, s21
+; GFX6-NEXT: s_lshr_b32 s20, s4, 17
+; GFX6-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], off, s[0:3], 0 offset:352
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v6, s48
+; GFX6-NEXT: v_mov_b32_e32 v7, s49
+; GFX6-NEXT: s_lshr_b32 s48, s4, 14
+; GFX6-NEXT: v_mov_b32_e32 v8, s46
+; GFX6-NEXT: v_mov_b32_e32 v9, s47
+; GFX6-NEXT: s_lshr_b32 s46, s4, 15
+; GFX6-NEXT: s_bfe_i64 s[52:53], s[54:55], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[10:13], off, s[0:3], 0 offset:336
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v10, s42
+; GFX6-NEXT: v_mov_b32_e32 v11, s43
+; GFX6-NEXT: s_lshr_b32 s42, s4, 12
+; GFX6-NEXT: v_mov_b32_e32 v12, s52
+; GFX6-NEXT: v_mov_b32_e32 v13, s53
+; GFX6-NEXT: s_lshr_b32 s52, s4, 13
+; GFX6-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[14:17], off, s[0:3], 0 offset:320
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v14, s38
+; GFX6-NEXT: v_mov_b32_e32 v15, s39
+; GFX6-NEXT: s_lshr_b32 s38, s4, 10
+; GFX6-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
+; GFX6-NEXT: v_mov_b32_e32 v16, s36
+; GFX6-NEXT: v_mov_b32_e32 v17, s37
+; GFX6-NEXT: s_lshr_b32 s36, s4, 11
+; GFX6-NEXT: v_mov_b32_e32 v2, s40
+; GFX6-NEXT: v_mov_b32_e32 v3, s41
+; GFX6-NEXT: s_lshr_b32 s40, s4, 8
+; GFX6-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], off, s[0:3], 0 offset:304
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v6, s30
+; GFX6-NEXT: v_mov_b32_e32 v7, s31
+; GFX6-NEXT: s_lshr_b32 s30, s4, 9
+; GFX6-NEXT: v_mov_b32_e32 v8, s34
+; GFX6-NEXT: v_mov_b32_e32 v9, s35
+; GFX6-NEXT: s_lshr_b32 s34, s4, 6
+; GFX6-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[10:13], off, s[0:3], 0 offset:288
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v10, s26
+; GFX6-NEXT: v_mov_b32_e32 v11, s27
+; GFX6-NEXT: s_lshr_b32 s26, s4, 7
+; GFX6-NEXT: v_mov_b32_e32 v12, s28
+; GFX6-NEXT: v_mov_b32_e32 v13, s29
+; GFX6-NEXT: s_lshr_b32 s28, s4, 4
+; GFX6-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[14:17], off, s[0:3], 0 offset:272
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v14, s22
+; GFX6-NEXT: v_mov_b32_e32 v15, s23
+; GFX6-NEXT: s_lshr_b32 s22, s4, 5
+; GFX6-NEXT: v_mov_b32_e32 v16, s24
+; GFX6-NEXT: v_mov_b32_e32 v17, s25
+; GFX6-NEXT: s_lshr_b32 s24, s4, 2
+; GFX6-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:256
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s44
+; GFX6-NEXT: v_mov_b32_e32 v1, s45
+; GFX6-NEXT: s_lshr_b32 s44, s4, 3
+; GFX6-NEXT: s_lshr_b32 s4, s4, 1
+; GFX6-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX6-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x10000
+; GFX6-NEXT: buffer_store_dwordx4 v[6:9], off, s[0:3], 0 offset:240
+; GFX6-NEXT: buffer_store_dwordx4 v[10:13], off, s[0:3], 0 offset:224
+; GFX6-NEXT: buffer_store_dwordx4 v[14:17], off, s[0:3], 0 offset:208
+; GFX6-NEXT: v_mov_b32_e32 v2, s18
+; GFX6-NEXT: v_mov_b32_e32 v3, s19
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:192
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s14
+; GFX6-NEXT: v_mov_b32_e32 v1, s15
+; GFX6-NEXT: v_mov_b32_e32 v2, s16
+; GFX6-NEXT: v_mov_b32_e32 v3, s17
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:176
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s10
+; GFX6-NEXT: v_mov_b32_e32 v1, s11
+; GFX6-NEXT: v_mov_b32_e32 v2, s12
+; GFX6-NEXT: v_mov_b32_e32 v3, s13
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:160
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NEXT: v_mov_b32_e32 v1, s7
+; GFX6-NEXT: v_mov_b32_e32 v2, s8
+; GFX6-NEXT: v_mov_b32_e32 v3, s9
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s50
+; GFX6-NEXT: v_mov_b32_e32 v1, s51
+; GFX6-NEXT: v_mov_b32_e32 v2, s20
+; GFX6-NEXT: v_mov_b32_e32 v3, s21
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s48
+; GFX6-NEXT: v_mov_b32_e32 v1, s49
+; GFX6-NEXT: v_mov_b32_e32 v2, s46
+; GFX6-NEXT: v_mov_b32_e32 v3, s47
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s42
+; GFX6-NEXT: v_mov_b32_e32 v1, s43
+; GFX6-NEXT: v_mov_b32_e32 v2, s52
+; GFX6-NEXT: v_mov_b32_e32 v3, s53
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s38
+; GFX6-NEXT: v_mov_b32_e32 v1, s39
+; GFX6-NEXT: v_mov_b32_e32 v2, s36
+; GFX6-NEXT: v_mov_b32_e32 v3, s37
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s40
+; GFX6-NEXT: v_mov_b32_e32 v1, s41
+; GFX6-NEXT: v_mov_b32_e32 v2, s30
+; GFX6-NEXT: v_mov_b32_e32 v3, s31
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s34
+; GFX6-NEXT: v_mov_b32_e32 v1, s35
+; GFX6-NEXT: v_mov_b32_e32 v2, s26
+; GFX6-NEXT: v_mov_b32_e32 v3, s27
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s28
+; GFX6-NEXT: v_mov_b32_e32 v1, s29
+; GFX6-NEXT: v_mov_b32_e32 v2, s22
+; GFX6-NEXT: v_mov_b32_e32 v3, s23
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s24
+; GFX6-NEXT: v_mov_b32_e32 v1, s25
+; GFX6-NEXT: v_mov_b32_e32 v2, s44
+; GFX6-NEXT: v_mov_b32_e32 v3, s45
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NEXT: v_mov_b32_e32 v6, s4
+; GFX6-NEXT: v_mov_b32_e32 v7, s5
+; GFX6-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_sextload_v64i1_to_v64i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s13, 0
+; GFX8-NEXT: s_mov_b32 s11, s13
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_lshr_b32 s14, s5, 22
+; GFX8-NEXT: s_lshr_b32 s16, s5, 23
+; GFX8-NEXT: s_lshr_b32 s20, s5, 20
+; GFX8-NEXT: s_lshr_b32 s22, s5, 21
+; GFX8-NEXT: s_lshr_b32 s24, s5, 18
+; GFX8-NEXT: s_lshr_b32 s26, s5, 19
+; GFX8-NEXT: s_lshr_b32 s28, s5, 16
+; GFX8-NEXT: s_lshr_b32 s30, s5, 17
+; GFX8-NEXT: s_lshr_b32 s34, s4, 22
+; GFX8-NEXT: s_lshr_b32 s36, s4, 23
+; GFX8-NEXT: s_lshr_b32 s38, s4, 20
+; GFX8-NEXT: s_lshr_b32 s40, s4, 21
+; GFX8-NEXT: s_lshr_b32 s42, s4, 18
+; GFX8-NEXT: s_lshr_b32 s44, s4, 19
+; GFX8-NEXT: s_lshr_b32 s46, s4, 16
+; GFX8-NEXT: s_lshr_b32 s48, s4, 17
+; GFX8-NEXT: s_mov_b32 s12, s5
+; GFX8-NEXT: s_lshr_b32 s10, s5, 24
+; GFX8-NEXT: s_lshr_b32 s6, s4, 24
+; GFX8-NEXT: s_bfe_i64 s[2:3], s[6:7], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[8:9], s[10:11], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[18:19], s[4:5], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x10000
+; GFX8-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x10000
+; GFX8-NEXT: v_mov_b32_e32 v11, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 0x1b0
+; GFX8-NEXT: v_mov_b32_e32 v12, s15
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 0x1a0
+; GFX8-NEXT: v_mov_b32_e32 v13, s16
+; GFX8-NEXT: v_mov_b32_e32 v14, s17
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 0x190
+; GFX8-NEXT: v_mov_b32_e32 v11, s20
+; GFX8-NEXT: v_mov_b32_e32 v12, s21
+; GFX8-NEXT: v_mov_b32_e32 v13, s22
+; GFX8-NEXT: v_mov_b32_e32 v14, s23
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 0x180
+; GFX8-NEXT: v_mov_b32_e32 v11, s24
+; GFX8-NEXT: v_mov_b32_e32 v12, s25
+; GFX8-NEXT: v_mov_b32_e32 v13, s26
+; GFX8-NEXT: v_mov_b32_e32 v14, s27
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 0xb0
+; GFX8-NEXT: v_mov_b32_e32 v11, s28
+; GFX8-NEXT: v_mov_b32_e32 v12, s29
+; GFX8-NEXT: v_mov_b32_e32 v13, s30
+; GFX8-NEXT: v_mov_b32_e32 v14, s31
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 0xa0
+; GFX8-NEXT: v_mov_b32_e32 v11, s34
+; GFX8-NEXT: v_mov_b32_e32 v12, s35
+; GFX8-NEXT: v_mov_b32_e32 v13, s36
+; GFX8-NEXT: v_mov_b32_e32 v14, s37
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 0x90
+; GFX8-NEXT: v_mov_b32_e32 v11, s38
+; GFX8-NEXT: v_mov_b32_e32 v12, s39
+; GFX8-NEXT: v_mov_b32_e32 v13, s40
+; GFX8-NEXT: v_mov_b32_e32 v14, s41
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 0x80
+; GFX8-NEXT: v_mov_b32_e32 v11, s42
+; GFX8-NEXT: v_mov_b32_e32 v12, s43
+; GFX8-NEXT: v_mov_b32_e32 v13, s44
+; GFX8-NEXT: v_mov_b32_e32 v14, s45
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 0x70
+; GFX8-NEXT: v_mov_b32_e32 v11, s46
+; GFX8-NEXT: v_mov_b32_e32 v12, s47
+; GFX8-NEXT: v_mov_b32_e32 v13, s48
+; GFX8-NEXT: v_mov_b32_e32 v14, s49
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 14, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v10, 15, s4
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_bfe_i32 v11, v10, 0, 1
+; GFX8-NEXT: v_bfe_i32 v9, v9, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 0x60
+; GFX8-NEXT: v_ashrrev_i32_e32 v12, 31, v11
+; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v7, 12, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v8, 13, s4
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[9:12]
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_bfe_i32 v9, v8, 0, 1
+; GFX8-NEXT: v_bfe_i32 v7, v7, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 0x50
+; GFX8-NEXT: v_ashrrev_i32_e32 v10, 31, v9
+; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v5, 10, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v6, 11, s4
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[7:10]
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_bfe_i32 v7, v6, 0, 1
+; GFX8-NEXT: v_bfe_i32 v5, v5, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 64
+; GFX8-NEXT: v_ashrrev_i32_e32 v8, 31, v7
+; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v3, 8, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v4, 9, s4
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[5:8]
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_bfe_i32 v5, v4, 0, 1
+; GFX8-NEXT: v_bfe_i32 v3, v3, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 48
+; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v5
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v1, 6, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v2, 7, s4
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[3:6]
+; GFX8-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 1
+; GFX8-NEXT: v_bfe_i32 v1, v1, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 32
+; GFX8-NEXT: v_ashrrev_i32_e32 v4, 31, v3
+; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v1
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 4, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v13, 5, s4
+; GFX8-NEXT: flat_store_dwordx4 v[15:16], v[1:4]
+; GFX8-NEXT: v_mov_b32_e32 v17, s15
+; GFX8-NEXT: v_bfe_i32 v2, v13, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v16, s14
+; GFX8-NEXT: s_add_u32 s14, s0, 16
+; GFX8-NEXT: v_lshrrev_b16_e64 v14, 2, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v11, 3, s4
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[16:17], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v18, s15
+; GFX8-NEXT: v_bfe_i32 v2, v11, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v14, 0, 1
+; GFX8-NEXT: v_lshrrev_b16_e64 v12, 1, s4
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_mov_b32_e32 v17, s14
+; GFX8-NEXT: flat_store_dwordx4 v[17:18], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v18, s1
+; GFX8-NEXT: v_bfe_i32 v2, v12, 0, 1
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 14, s5
+; GFX8-NEXT: v_lshrrev_b16_e64 v10, 15, s5
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_mov_b32_e32 v0, s18
+; GFX8-NEXT: v_mov_b32_e32 v1, s19
+; GFX8-NEXT: v_mov_b32_e32 v17, s0
+; GFX8-NEXT: s_add_u32 s14, s0, 0x170
+; GFX8-NEXT: flat_store_dwordx4 v[17:18], v[0:3]
+; GFX8-NEXT: s_addc_u32 s15, s1, 0
+; GFX8-NEXT: v_bfe_i32 v2, v10, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v9, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v9, s14
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_mov_b32_e32 v10, s15
+; GFX8-NEXT: s_add_u32 s4, s0, 0x160
+; GFX8-NEXT: v_lshrrev_b16_e64 v7, 12, s5
+; GFX8-NEXT: v_lshrrev_b16_e64 v8, 13, s5
+; GFX8-NEXT: v_lshrrev_b16_e64 v5, 10, s5
+; GFX8-NEXT: v_lshrrev_b16_e64 v6, 11, s5
+; GFX8-NEXT: v_lshrrev_b16_e64 v4, 8, s5
+; GFX8-NEXT: v_lshrrev_b16_e64 v15, 9, s5
+; GFX8-NEXT: v_lshrrev_b16_e64 v13, 6, s5
+; GFX8-NEXT: v_lshrrev_b16_e64 v16, 7, s5
+; GFX8-NEXT: v_lshrrev_b16_e64 v11, 4, s5
+; GFX8-NEXT: v_lshrrev_b16_e64 v12, 5, s5
+; GFX8-NEXT: v_lshrrev_b16_e64 v14, 2, s5
+; GFX8-NEXT: flat_store_dwordx4 v[9:10], v[0:3]
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 3, s5
+; GFX8-NEXT: v_lshrrev_b16_e64 v10, 1, s5
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_bfe_i32 v2, v8, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v7, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v8, s5
+; GFX8-NEXT: v_mov_b32_e32 v7, s4
+; GFX8-NEXT: s_add_u32 s4, s0, 0x150
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[7:8], v[0:3]
+; GFX8-NEXT: v_lshrrev_b16_e64 v7, 6, s10
+; GFX8-NEXT: v_bfe_i32 v2, v6, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v5, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v6, s5
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_mov_b32_e32 v5, s4
+; GFX8-NEXT: s_add_u32 s4, s0, 0x140
+; GFX8-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_bfe_i32 v2, v15, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v4, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x130
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_bfe_i32 v2, v16, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v13, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x120
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_bfe_i32 v2, v12, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v11, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x110
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_bfe_i32 v2, v9, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v14, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x100
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_bfe_i32 v2, v10, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x1f0
+; GFX8-NEXT: v_lshrrev_b16_e64 v8, 7, s10
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NEXT: v_mov_b32_e32 v1, s13
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_lshrrev_b16_e64 v17, 4, s10
+; GFX8-NEXT: v_bfe_i32 v2, v8, 0, 1
+; GFX8-NEXT: v_bfe_i32 v0, v7, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v7, s5
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NEXT: v_mov_b32_e32 v6, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v18, 5, s10
+; GFX8-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX8-NEXT: s_add_u32 s4, s0, 0x1e0
+; GFX8-NEXT: v_lshrrev_b16_e64 v0, 1, s6
+; GFX8-NEXT: v_bfe_i32 v2, v0, 0, 1
+; GFX8-NEXT: v_bfe_i32 v18, v18, 0, 1
+; GFX8-NEXT: v_bfe_i32 v16, v17, 0, 1
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v20, 2, s10
+; GFX8-NEXT: v_lshrrev_b16_e64 v21, 3, s10
+; GFX8-NEXT: v_lshrrev_b16_e64 v22, 1, s10
+; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18
+; GFX8-NEXT: v_ashrrev_i32_e32 v17, 31, v16
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x1d0
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
+; GFX8-NEXT: v_bfe_i32 v20, v20, 0, 1
+; GFX8-NEXT: v_bfe_i32 v18, v22, 0, 1
+; GFX8-NEXT: v_bfe_i32 v22, v21, 0, 1
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_ashrrev_i32_e32 v23, 31, v22
+; GFX8-NEXT: v_ashrrev_i32_e32 v21, 31, v20
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0x1c0
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[20:23]
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_lshrrev_b16_e64 v13, 6, s6
+; GFX8-NEXT: v_lshrrev_b16_e64 v12, 7, s6
+; GFX8-NEXT: v_ashrrev_i32_e32 v19, 31, v18
+; GFX8-NEXT: v_mov_b32_e32 v16, s8
+; GFX8-NEXT: v_mov_b32_e32 v17, s9
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0xf0
+; GFX8-NEXT: v_lshrrev_b16_e64 v15, 4, s6
+; GFX8-NEXT: v_bfe_i32 v14, v12, 0, 1
+; GFX8-NEXT: v_bfe_i32 v12, v13, 0, 1
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_bfe_i32 v8, v15, 0, 1
+; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX8-NEXT: v_ashrrev_i32_e32 v13, 31, v12
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0xe0
+; GFX8-NEXT: v_lshrrev_b16_e64 v9, 5, s6
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_bfe_i32 v10, v9, 0, 1
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_add_u32 s4, s0, 0xd0
+; GFX8-NEXT: v_lshrrev_b16_e64 v4, 2, s6
+; GFX8-NEXT: v_lshrrev_b16_e64 v5, 3, s6
+; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; GFX8-NEXT: v_ashrrev_i32_e32 v9, 31, v8
+; GFX8-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NEXT: v_bfe_i32 v6, v5, 0, 1
+; GFX8-NEXT: v_bfe_i32 v4, v4, 0, 1
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: s_add_u32 s0, s0, 0xc0
+; GFX8-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v64i1_to_v64i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 22, @40, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @38
+; EG-NEXT: ALU 89, @63, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 99, @153, KC0[], KC1[]
+; EG-NEXT: ALU 107, @253, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T50.XYZW, T82.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T80.XYZW, T81.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T51.XYZW, T73.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T79.XYZW, T48.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T52.XYZW, T47.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T78.XYZW, T46.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T53.XYZW, T45.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T77.XYZW, T44.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T54.XYZW, T43.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T76.XYZW, T42.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T55.XYZW, T41.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T75.XYZW, T40.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T56.XYZW, T39.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T74.XYZW, T38.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T57.XYZW, T37.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T66.XYZW, T36.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T58.XYZW, T35.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T72.XYZW, T34.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T59.XYZW, T33.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T71.XYZW, T32.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T60.XYZW, T31.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T70.XYZW, T30.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T61.XYZW, T29.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T69.XYZW, T28.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T62.XYZW, T27.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T68.XYZW, T25.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T63.XYZW, T24.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T26.XYZW, T23.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T64.XYZW, T22.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T67.XYZW, T21.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T65.XYZW, T20.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T49.XYZW, T19.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 38:
+; EG-NEXT: VTX_READ_64 T26.XY, T26.X, 0, #1
+; EG-NEXT: ALU clause starting at 40:
+; EG-NEXT: LSHR T19.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T20.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T21.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T22.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T23.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T24.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: LSHR T25.X, PV.W, literal.x,
+; EG-NEXT: MOV * T26.X, KC0[2].Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 112(1.569454e-43), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 63:
+; EG-NEXT: LSHR T27.X, T0.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 128(1.793662e-43)
+; EG-NEXT: LSHR T28.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 144(2.017870e-43)
+; EG-NEXT: LSHR T29.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 160(2.242078e-43)
+; EG-NEXT: LSHR T30.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 176(2.466285e-43)
+; EG-NEXT: LSHR T31.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 192(2.690493e-43)
+; EG-NEXT: LSHR T32.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 208(2.914701e-43)
+; EG-NEXT: LSHR T33.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 224(3.138909e-43)
+; EG-NEXT: LSHR T34.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 240(3.363116e-43)
+; EG-NEXT: LSHR T35.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 256(3.587324e-43)
+; EG-NEXT: LSHR T36.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 272(3.811532e-43)
+; EG-NEXT: LSHR T37.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 288(4.035740e-43)
+; EG-NEXT: LSHR T38.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 304(4.259947e-43)
+; EG-NEXT: LSHR T39.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 320(4.484155e-43)
+; EG-NEXT: LSHR T40.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 336(4.708363e-43)
+; EG-NEXT: LSHR T41.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 352(4.932571e-43)
+; EG-NEXT: LSHR T42.X, PV.W, literal.x,
+; EG-NEXT: LSHR T0.Z, T26.Y, literal.y,
+; EG-NEXT: LSHR T0.W, T26.Y, literal.z,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 28(3.923636e-44)
+; EG-NEXT: 29(4.063766e-44), 368(5.156778e-43)
+; EG-NEXT: LSHR T43.X, PS, literal.x,
+; EG-NEXT: LSHR T0.Y, T26.Y, literal.y,
+; EG-NEXT: LSHR T1.Z, T26.Y, literal.z,
+; EG-NEXT: LSHR * T1.W, T26.Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 24(3.363116e-44)
+; EG-NEXT: 25(3.503246e-44), 20(2.802597e-44)
+; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,
+; EG-NEXT: 384(5.380986e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T44.X, PV.W, literal.x,
+; EG-NEXT: LSHR T1.Y, T26.Y, literal.y,
+; EG-NEXT: LSHR T2.Z, T26.Y, literal.z,
+; EG-NEXT: LSHR * T2.W, T26.Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 21(2.942727e-44)
+; EG-NEXT: 16(2.242078e-44), 17(2.382207e-44)
+; EG-NEXT: ADD_INT * T3.W, KC0[2].Y, literal.x,
+; EG-NEXT: 400(5.605194e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T45.X, PV.W, literal.x,
+; EG-NEXT: LSHR T2.Y, T26.Y, literal.y,
+; EG-NEXT: LSHR T3.Z, T26.Y, literal.z,
+; EG-NEXT: LSHR * T3.W, T26.Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 12(1.681558e-44)
+; EG-NEXT: 13(1.821688e-44), 8(1.121039e-44)
+; EG-NEXT: ADD_INT * T4.W, KC0[2].Y, literal.x,
+; EG-NEXT: 416(5.829402e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T46.X, PV.W, literal.x,
+; EG-NEXT: LSHR T3.Y, T26.Y, literal.y,
+; EG-NEXT: LSHR T4.Z, T26.Y, literal.z,
+; EG-NEXT: LSHR * T4.W, T26.Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 9(1.261169e-44)
+; EG-NEXT: 4(5.605194e-45), 5(7.006492e-45)
+; EG-NEXT: ADD_INT * T5.W, KC0[2].Y, literal.x,
+; EG-NEXT: 432(6.053609e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T47.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT T4.Y, KC0[2].Y, literal.y,
+; EG-NEXT: LSHR T5.Z, T26.Y, 1,
+; EG-NEXT: LSHR T5.W, T26.X, literal.z,
+; EG-NEXT: ADD_INT * T6.W, KC0[2].Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 464(6.502025e-43)
+; EG-NEXT: 28(3.923636e-44), 448(6.277817e-43)
+; EG-NEXT: ALU clause starting at 153:
+; EG-NEXT: LSHR T48.X, T6.W, literal.x,
+; EG-NEXT: LSHR T5.Y, T26.X, literal.y,
+; EG-NEXT: LSHR T6.Z, T26.X, literal.z,
+; EG-NEXT: LSHR * T6.W, T26.X, literal.w,
+; EG-NEXT: 2(2.802597e-45), 29(4.063766e-44)
+; EG-NEXT: 24(3.363116e-44), 25(3.503246e-44)
+; EG-NEXT: LSHR * T7.W, T26.X, literal.x,
+; EG-NEXT: 20(2.802597e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T49.X, T26.X, 0.0, 1,
+; EG-NEXT: LSHR T6.Y, T26.X, literal.x,
+; EG-NEXT: ASHR T50.Z, T26.Y, literal.y,
+; EG-NEXT: LSHR T8.W, T26.Y, literal.z,
+; EG-NEXT: LSHR * T9.W, T26.Y, literal.w,
+; EG-NEXT: 21(2.942727e-44), 31(4.344025e-44)
+; EG-NEXT: 27(3.783506e-44), 30(4.203895e-44)
+; EG-NEXT: BFE_INT T50.X, PS, 0.0, 1,
+; EG-NEXT: LSHR T7.Y, T26.X, literal.x,
+; EG-NEXT: BFE_INT T51.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T8.W, T26.Y, literal.y,
+; EG-NEXT: LSHR * T9.W, T26.Y, literal.z,
+; EG-NEXT: 16(2.242078e-44), 23(3.222986e-44)
+; EG-NEXT: 26(3.643376e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T51.X, PS, 0.0, 1,
+; EG-NEXT: MOV T50.Y, PV.X,
+; EG-NEXT: BFE_INT T52.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T8.W, T26.Y, literal.x,
+; EG-NEXT: LSHR * T9.W, T26.Y, literal.y,
+; EG-NEXT: 19(2.662467e-44), 22(3.082857e-44)
+; EG-NEXT: BFE_INT T52.X, PS, 0.0, 1,
+; EG-NEXT: MOV T51.Y, PV.X,
+; EG-NEXT: BFE_INT T53.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T8.W, T26.Y, literal.x,
+; EG-NEXT: LSHR * T9.W, T26.Y, literal.y,
+; EG-NEXT: 15(2.101948e-44), 18(2.522337e-44)
+; EG-NEXT: BFE_INT T53.X, PS, 0.0, 1,
+; EG-NEXT: MOV T52.Y, PV.X,
+; EG-NEXT: BFE_INT T54.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T8.W, T26.Y, literal.x,
+; EG-NEXT: LSHR * T9.W, T26.Y, literal.y,
+; EG-NEXT: 11(1.541428e-44), 14(1.961818e-44)
+; EG-NEXT: BFE_INT T54.X, PS, 0.0, 1,
+; EG-NEXT: MOV T53.Y, PV.X,
+; EG-NEXT: BFE_INT T55.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T8.W, T26.Y, literal.x,
+; EG-NEXT: LSHR * T9.W, T26.Y, literal.y,
+; EG-NEXT: 7(9.809089e-45), 10(1.401298e-44)
+; EG-NEXT: BFE_INT T55.X, PS, 0.0, 1,
+; EG-NEXT: MOV T54.Y, PV.X,
+; EG-NEXT: BFE_INT T56.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T8.W, T26.Y, literal.x,
+; EG-NEXT: LSHR * T9.W, T26.Y, literal.y,
+; EG-NEXT: 3(4.203895e-45), 6(8.407791e-45)
+; EG-NEXT: BFE_INT T56.X, PS, 0.0, 1,
+; EG-NEXT: MOV T55.Y, PV.X,
+; EG-NEXT: BFE_INT T57.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T8.W, T26.X, literal.x,
+; EG-NEXT: LSHR * T9.W, T26.Y, literal.y,
+; EG-NEXT: 17(2.382207e-44), 2(2.802597e-45)
+; EG-NEXT: BFE_INT T57.X, PS, 0.0, 1,
+; EG-NEXT: MOV T56.Y, PV.X,
+; EG-NEXT: ASHR T58.Z, T26.X, literal.x,
+; EG-NEXT: LSHR T9.W, T26.X, literal.y,
+; EG-NEXT: LSHR * T10.W, T26.X, literal.z,
+; EG-NEXT: 31(4.344025e-44), 27(3.783506e-44)
+; EG-NEXT: 30(4.203895e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T58.X, PS, 0.0, 1,
+; EG-NEXT: MOV T57.Y, PV.X,
+; EG-NEXT: BFE_INT T59.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T9.W, T26.X, literal.x,
+; EG-NEXT: LSHR * T10.W, T26.X, literal.y,
+; EG-NEXT: 23(3.222986e-44), 26(3.643376e-44)
+; EG-NEXT: BFE_INT T59.X, PS, 0.0, 1,
+; EG-NEXT: MOV T58.Y, PV.X,
+; EG-NEXT: BFE_INT T60.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T9.W, T26.X, literal.x,
+; EG-NEXT: LSHR * T10.W, T26.X, literal.y,
+; EG-NEXT: 19(2.662467e-44), 22(3.082857e-44)
+; EG-NEXT: BFE_INT T60.X, PS, 0.0, 1,
+; EG-NEXT: MOV T59.Y, PV.X,
+; EG-NEXT: BFE_INT T61.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T9.W, T26.X, literal.x,
+; EG-NEXT: LSHR * T10.W, T26.X, literal.y,
+; EG-NEXT: 15(2.101948e-44), 18(2.522337e-44)
+; EG-NEXT: BFE_INT T61.X, PS, 0.0, 1,
+; EG-NEXT: MOV T60.Y, PV.X,
+; EG-NEXT: BFE_INT T62.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T9.W, T26.X, literal.x,
+; EG-NEXT: LSHR * T10.W, T26.X, literal.y,
+; EG-NEXT: 11(1.541428e-44), 14(1.961818e-44)
+; EG-NEXT: BFE_INT T62.X, PS, 0.0, 1,
+; EG-NEXT: MOV T61.Y, PV.X,
+; EG-NEXT: BFE_INT T63.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T9.W, T26.X, literal.x,
+; EG-NEXT: LSHR * T10.W, T26.X, literal.y,
+; EG-NEXT: 7(9.809089e-45), 10(1.401298e-44)
+; EG-NEXT: BFE_INT T63.X, PS, 0.0, 1,
+; EG-NEXT: MOV T62.Y, PV.X,
+; EG-NEXT: BFE_INT T64.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR * T9.W, T26.X, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 253:
+; EG-NEXT: LSHR * T10.W, T26.X, literal.x,
+; EG-NEXT: 6(8.407791e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T64.X, PV.W, 0.0, 1,
+; EG-NEXT: MOV T63.Y, T63.X,
+; EG-NEXT: BFE_INT T65.Z, T9.W, 0.0, 1,
+; EG-NEXT: LSHR T9.W, T26.X, 1, BS:VEC_120/SCL_212
+; EG-NEXT: LSHR * T10.W, T26.X, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T65.X, PS, 0.0, 1,
+; EG-NEXT: MOV T64.Y, PV.X,
+; EG-NEXT: BFE_INT T49.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T9.W, T26.X, literal.x,
+; EG-NEXT: LSHR * T10.W, T26.X, literal.y,
+; EG-NEXT: 12(1.681558e-44), 5(7.006492e-45)
+; EG-NEXT: BFE_INT T66.X, T26.Y, 0.0, 1,
+; EG-NEXT: MOV T65.Y, PV.X,
+; EG-NEXT: BFE_INT T67.Z, PS, 0.0, 1,
+; EG-NEXT: LSHR T10.W, T26.X, literal.x,
+; EG-NEXT: LSHR * T11.W, T26.X, literal.y,
+; EG-NEXT: 9(1.261169e-44), 4(5.605194e-45)
+; EG-NEXT: BFE_INT T67.X, PS, 0.0, 1,
+; EG-NEXT: MOV T49.Y, T49.X,
+; EG-NEXT: BFE_INT T26.Z, PV.W, 0.0, 1,
+; EG-NEXT: LSHR T10.W, T26.X, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: LSHR * T11.W, T26.X, literal.y,
+; EG-NEXT: 13(1.821688e-44), 8(1.121039e-44)
+; EG-NEXT: BFE_INT T26.X, PS, 0.0, 1,
+; EG-NEXT: MOV T67.Y, PV.X,
+; EG-NEXT: BFE_INT T68.Z, PV.W, 0.0, 1,
+; EG-NEXT: MOV T49.W, T49.Z,
+; EG-NEXT: MOV * T65.W, T65.Z,
+; EG-NEXT: BFE_INT T68.X, T9.W, 0.0, 1,
+; EG-NEXT: MOV T26.Y, PV.X,
+; EG-NEXT: BFE_INT T69.Z, T8.W, 0.0, 1, BS:VEC_120/SCL_212
+; EG-NEXT: MOV T67.W, T67.Z,
+; EG-NEXT: MOV * T64.W, T64.Z,
+; EG-NEXT: BFE_INT T69.X, T7.Y, 0.0, 1,
+; EG-NEXT: MOV T68.Y, PV.X,
+; EG-NEXT: BFE_INT T70.Z, T6.Y, 0.0, 1, BS:VEC_120/SCL_212
+; EG-NEXT: MOV T26.W, T26.Z,
+; EG-NEXT: MOV * T63.W, T63.Z,
+; EG-NEXT: BFE_INT T70.X, T7.W, 0.0, 1,
+; EG-NEXT: MOV T69.Y, PV.X,
+; EG-NEXT: BFE_INT T71.Z, T6.W, 0.0, 1, BS:VEC_120/SCL_212
+; EG-NEXT: MOV T68.W, T68.Z,
+; EG-NEXT: MOV * T62.W, T62.Z,
+; EG-NEXT: BFE_INT T71.X, T6.Z, 0.0, 1,
+; EG-NEXT: MOV T70.Y, PV.X,
+; EG-NEXT: BFE_INT T72.Z, T5.Y, 0.0, 1,
+; EG-NEXT: MOV T69.W, T69.Z, BS:VEC_120/SCL_212
+; EG-NEXT: MOV * T61.W, T61.Z,
+; EG-NEXT: BFE_INT T72.X, T5.W, 0.0, 1,
+; EG-NEXT: MOV T71.Y, PV.X,
+; EG-NEXT: BFE_INT T66.Z, T5.Z, 0.0, 1,
+; EG-NEXT: MOV T70.W, T70.Z, BS:VEC_120/SCL_212
+; EG-NEXT: MOV * T60.W, T60.Z,
+; EG-NEXT: LSHR T73.X, T4.Y, literal.x,
+; EG-NEXT: MOV T72.Y, PV.X,
+; EG-NEXT: BFE_INT T74.Z, T4.W, 0.0, 1,
+; EG-NEXT: MOV T71.W, T71.Z,
+; EG-NEXT: MOV * T59.W, T59.Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T74.X, T4.Z, 0.0, 1,
+; EG-NEXT: MOV T66.Y, T66.X,
+; EG-NEXT: BFE_INT T75.Z, T3.Y, 0.0, 1,
+; EG-NEXT: MOV T72.W, T72.Z, BS:VEC_120/SCL_212
+; EG-NEXT: MOV * T58.W, T58.Z,
+; EG-NEXT: BFE_INT T75.X, T3.W, 0.0, 1,
+; EG-NEXT: MOV T74.Y, PV.X,
+; EG-NEXT: BFE_INT T76.Z, T3.Z, 0.0, 1,
+; EG-NEXT: MOV T66.W, T66.Z, BS:VEC_120/SCL_212
+; EG-NEXT: MOV * T57.W, T57.Z,
+; EG-NEXT: BFE_INT T76.X, T2.Y, 0.0, 1,
+; EG-NEXT: MOV T75.Y, PV.X,
+; EG-NEXT: BFE_INT T77.Z, T2.W, 0.0, 1,
+; EG-NEXT: MOV T74.W, T74.Z,
+; EG-NEXT: MOV * T56.W, T56.Z,
+; EG-NEXT: BFE_INT T77.X, T2.Z, 0.0, 1,
+; EG-NEXT: MOV T76.Y, PV.X,
+; EG-NEXT: BFE_INT T78.Z, T1.Y, 0.0, 1,
+; EG-NEXT: MOV T75.W, T75.Z, BS:VEC_120/SCL_212
+; EG-NEXT: MOV * T55.W, T55.Z,
+; EG-NEXT: BFE_INT T78.X, T1.W, 0.0, 1,
+; EG-NEXT: MOV T77.Y, PV.X,
+; EG-NEXT: BFE_INT T79.Z, T1.Z, 0.0, 1,
+; EG-NEXT: MOV T76.W, T76.Z, BS:VEC_120/SCL_212
+; EG-NEXT: MOV * T54.W, T54.Z,
+; EG-NEXT: BFE_INT T79.X, T0.Y, 0.0, 1,
+; EG-NEXT: MOV T78.Y, PV.X,
+; EG-NEXT: BFE_INT T80.Z, T0.W, 0.0, 1,
+; EG-NEXT: MOV T77.W, T77.Z,
+; EG-NEXT: MOV * T53.W, T53.Z,
+; EG-NEXT: BFE_INT T80.X, T0.Z, 0.0, 1,
+; EG-NEXT: MOV T79.Y, PV.X,
+; EG-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.x,
+; EG-NEXT: MOV T78.W, T78.Z, BS:VEC_120/SCL_212
+; EG-NEXT: MOV * T52.W, T52.Z,
+; EG-NEXT: 480(6.726233e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T81.X, PV.Z, literal.x,
+; EG-NEXT: MOV T80.Y, PV.X,
+; EG-NEXT: ADD_INT T0.Z, KC0[2].Y, literal.y,
+; EG-NEXT: MOV T79.W, T79.Z,
+; EG-NEXT: MOV * T51.W, T51.Z,
+; EG-NEXT: 2(2.802597e-45), 496(6.950440e-43)
+; EG-NEXT: LSHR T82.X, PV.Z, literal.x,
+; EG-NEXT: MOV T80.W, T80.Z,
+; EG-NEXT: MOV * T50.W, T50.Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <64 x i1>, ptr addrspace(4) %in
%ext = sext <64 x i1> %load to <64 x i64>
store <64 x i64> %ext, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
index 885a8007e3b5f..5a3f5f4240d8b 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-NOHSA-SI %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-HSA %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-NOHSA-VI %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GCN-NOHSA-VI %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck --check-prefix=EG %s
define amdgpu_kernel void @constant_load_i16(ptr addrspace(1) %out, ptr addrspace(4) %in) {
@@ -38,18 +38,14 @@ define amdgpu_kernel void @constant_load_i16(ptr addrspace(1) %out, ptr addrspac
; GCN-NOHSA-VI-LABEL: constant_load_i16:
; GCN-NOHSA-VI: ; %bb.0: ; %entry
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s6
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s7
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v2, v[0:1]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: buffer_store_short v0, off, s[4:7], 0
+; GCN-NOHSA-VI-NEXT: flat_store_short v[0:1], v2
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_load_i16:
@@ -112,12 +108,12 @@ define amdgpu_kernel void @constant_load_v2i16(ptr addrspace(1) %out, ptr addrsp
; GCN-NOHSA-VI: ; %bb.0: ; %entry
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dword s4, s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-VI-NEXT: s_load_dword s2, s[2:3], 0x0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NOHSA-VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NOHSA-VI-NEXT: flat_store_dword v[0:1], v2
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_load_v2i16:
@@ -179,14 +175,18 @@ define amdgpu_kernel void @constant_load_v3i16(ptr addrspace(1) %out, ptr addrsp
; GCN-NOHSA-VI: ; %bb.0: ; %entry
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s0, 4
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s5
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s5
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s4
-; GCN-NOHSA-VI-NEXT: buffer_store_short v0, off, s[0:3], 0 offset:4
-; GCN-NOHSA-VI-NEXT: buffer_store_dword v1, off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s2
+; GCN-NOHSA-VI-NEXT: flat_store_short v[2:3], v4
+; GCN-NOHSA-VI-NEXT: flat_store_dword v[0:1], v5
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_load_v3i16:
@@ -261,13 +261,13 @@ define amdgpu_kernel void @constant_load_v4i16(ptr addrspace(1) %out, ptr addrsp
; GCN-NOHSA-VI: ; %bb.0: ; %entry
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s3
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_load_v4i16:
@@ -327,14 +327,14 @@ define amdgpu_kernel void @constant_load_v8i16(ptr addrspace(1) %out, ptr addrsp
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_load_v8i16:
@@ -409,19 +409,23 @@ define amdgpu_kernel void @constant_load_v16i16(ptr addrspace(1) %out, ptr addrs
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, -1
+; GCN-NOHSA-VI-NEXT: s_add_u32 s10, s8, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s11, s9, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s11
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s2
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s3
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s9
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_load_v16i16:
@@ -520,58 +524,118 @@ define amdgpu_kernel void @constant_load_v16i16_align2(ptr addrspace(4) %ptr0) #
; GCN-NOHSA-VI-LABEL: constant_load_v16i16_align2:
; GCN-NOHSA-VI: ; %bb.0: ; %entry
; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v0, off, s[0:3], 0 offset:14
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v1, off, s[0:3], 0 offset:10
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v2, off, s[0:3], 0 offset:6
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v3, off, s[0:3], 0 offset:2
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v4, off, s[0:3], 0 offset:30
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v5, off, s[0:3], 0 offset:26
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v6, off, s[0:3], 0 offset:22
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v7, off, s[0:3], 0 offset:18
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v8, off, s[0:3], 0 offset:12
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v9, off, s[0:3], 0 offset:8
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v10, off, s[0:3], 0 offset:4
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v11, off, s[0:3], 0
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v12, off, s[0:3], 0 offset:28
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v13, off, s[0:3], 0 offset:24
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v14, off, s[0:3], 0 offset:20
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v15, off, s[0:3], 0 offset:16
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 14
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 12
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s3
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 10
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 8
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 6
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v9, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v8, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 4
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v11, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v10, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 30
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v13, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v12, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 28
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v15, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v14, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 26
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v16, v[0:1]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v17, v[2:3]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v18, v[4:5]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v19, v[6:7]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v20, v[8:9]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v21, v[10:11]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v22, v[12:13]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v23, v[14:15]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 24
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s3
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 22
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 20
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v7, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v6, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 18
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v9, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v8, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v11, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v10, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 2
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v13, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v15, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v12, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v14, s0
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v0, v[0:1]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v24, v[2:3]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v4, v[4:5]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v5, v[6:7]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v8, v[8:9]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v9, v[10:11]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v10, v[12:13]
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v11, v[14:15]
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(14)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 16, v16
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v3, v17, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(13)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v16, 16, v2
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 16, v18
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(12)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v17, 16, v3
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v2, v19, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(11)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v1, 16, v20
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(10)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v1, v21, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(9)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v18, 16, v6
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v6, 16, v22
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(8)
-; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v19, 16, v7
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v7, v23, v6
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(7)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v3, v8, v0
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(6)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v2, v9, v1
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v6, v24, v0
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(5)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v1, v10, v16
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v4
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(4)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v0, v11, v17
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v5, v5, v0
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(3)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v7, v12, v4
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v8
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(2)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v6, v13, v5
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v4, v9, v0
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(1)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v5, v14, v18
+; GCN-NOHSA-VI-NEXT: v_lshlrev_b32_e32 v0, 16, v10
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v4, v15, v19
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_or_b32_e32 v0, v11, v0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[0:1], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_load_v16i16_align2:
@@ -630,18 +694,14 @@ define amdgpu_kernel void @constant_zextload_i16_to_i32(ptr addrspace(1) %out, p
; GCN-NOHSA-VI-LABEL: constant_zextload_i16_to_i32:
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s6
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s7
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v2, v[0:1]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GCN-NOHSA-VI-NEXT: flat_store_dword v[0:1], v2
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_i16_to_i32:
@@ -699,18 +759,14 @@ define amdgpu_kernel void @constant_sextload_i16_to_i32(ptr addrspace(1) %out, p
; GCN-NOHSA-VI-LABEL: constant_sextload_i16_to_i32:
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s6
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s7
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
-; GCN-NOHSA-VI-NEXT: buffer_load_sshort v0, off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: flat_load_sshort v2, v[0:1]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GCN-NOHSA-VI-NEXT: flat_store_dword v[0:1], v2
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_i16_to_i32:
@@ -769,18 +825,14 @@ define amdgpu_kernel void @constant_zextload_v1i16_to_v1i32(ptr addrspace(1) %ou
; GCN-NOHSA-VI-LABEL: constant_zextload_v1i16_to_v1i32:
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s6
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s7
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v2, v[0:1]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GCN-NOHSA-VI-NEXT: flat_store_dword v[0:1], v2
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v1i16_to_v1i32:
@@ -838,18 +890,14 @@ define amdgpu_kernel void @constant_sextload_v1i16_to_v1i32(ptr addrspace(1) %ou
; GCN-NOHSA-VI-LABEL: constant_sextload_v1i16_to_v1i32:
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s6
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s7
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
-; GCN-NOHSA-VI-NEXT: buffer_load_sshort v0, off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: flat_load_sshort v2, v[0:1]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GCN-NOHSA-VI-NEXT: flat_store_dword v[0:1], v2
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v1i16_to_v1i32:
@@ -909,15 +957,15 @@ define amdgpu_kernel void @constant_zextload_v2i16_to_v2i32(ptr addrspace(1) %ou
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dword s4, s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-VI-NEXT: s_load_dword s2, s[2:3], 0x0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s5, s4, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s0, s2, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s1, s2, 0xffff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v2i16_to_v2i32:
@@ -980,15 +1028,15 @@ define amdgpu_kernel void @constant_sextload_v2i16_to_v2i32(ptr addrspace(1) %ou
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dword s4, s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-VI-NEXT: s_load_dword s2, s[2:3], 0x0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s5, s4, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s5
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s0, s2, 16
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s1, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v2i16_to_v2i32:
@@ -1057,17 +1105,17 @@ define amdgpu_kernel void @constant_zextload_v3i16_to_v3i32(ptr addrspace(1) %ou
; GCN-NOHSA-VI: ; %bb.0: ; %entry
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s4, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: s_and_b32 s0, s3, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s1, s2, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s2, s2, 0xffff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v3i16_to_v3i32:
@@ -1140,17 +1188,17 @@ define amdgpu_kernel void @constant_sextload_v3i16_to_v3i32(ptr addrspace(1) %ou
; GCN-NOHSA-VI: ; %bb.0: ; %entry
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s6, s4, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx3 v[0:2], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s0, s2, 16
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s1, s3
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s2, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s1
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v3i16_to_v3i32:
@@ -1230,19 +1278,19 @@ define amdgpu_kernel void @constant_zextload_v4i16_to_v4i32(ptr addrspace(1) %ou
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s5, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s7, s4, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s7
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s6
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s0, s3, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s1, s3, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s3, s2, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s2, s2, 0xffff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v4i16_to_v4i32:
@@ -1319,19 +1367,19 @@ define amdgpu_kernel void @constant_sextload_v4i16_to_v4i32(ptr addrspace(1) %ou
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s6, s5, 16
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s7, s4, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s7
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s6
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s0, s3, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s1, s2, 16
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s3, s3
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s2, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v4i16_to_v4i32:
@@ -1434,28 +1482,31 @@ define amdgpu_kernel void @constant_zextload_v8i16_to_v8i32(ptr addrspace(1) %ou
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s7, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s11, s6, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s8, s5, 16
; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s9, s4, 16
; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s7, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s3, s7, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s7, s6, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s11
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s10
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s8
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v8i16_to_v8i32:
@@ -1565,28 +1616,31 @@ define amdgpu_kernel void @constant_sextload_v8i16_to_v8i32(ptr addrspace(1) %ou
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s10, s7, 16
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s11, s6, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
; GCN-NOHSA-VI-NEXT: s_ashr_i32 s8, s5, 16
; GCN-NOHSA-VI-NEXT: s_ashr_i32 s9, s4, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s2, s7, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s3, s6, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s11
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s10
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s8
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v8i16_to_v8i32:
@@ -1741,47 +1795,57 @@ define amdgpu_kernel void @constant_zextload_v16i16_to_v16i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s18, s11, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s11, s11, 0xffff
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s19, s10, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s10, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s12, s5, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s13, s4, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s14, s7, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s15, s6, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s16, s9, 16
; GCN-NOHSA-VI-NEXT: s_and_b32 s9, s9, 0xffff
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s17, s8, 16
; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s8, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s11, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s3, s11, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s11, s10, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s10, 0xffff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 48
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 32
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s19
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s18
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s14, s7, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s15, s6, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s12, s5, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s11
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s17
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s13, s4, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s15
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s14
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s13
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s12
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v16i16_to_v16i32:
@@ -1955,47 +2019,57 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s18, s11, 16
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s19, s10, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s11, s11
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s10, s10
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s12, s5, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s13, s4, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s14, s7, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s15, s6, 16
; GCN-NOHSA-VI-NEXT: s_ashr_i32 s16, s9, 16
; GCN-NOHSA-VI-NEXT: s_ashr_i32 s17, s8, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s9, s9
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s8, s8
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s2, s11, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s3, s10, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 48
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s11, s11
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s10, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 32
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s19
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s18
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s14, s7, 16
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s15, s6, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s12, s5, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s9, s9
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s8, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s17
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s16
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s13, s4, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s15
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s14
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s13
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s12
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v16i16_to_v16i32:
@@ -2265,83 +2339,109 @@ define amdgpu_kernel void @constant_zextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s19, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s18, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s35, s15, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s36, s14, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s15, s15, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s14, s14, 0xffff
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s33, s13, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s34, s12, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s13, s13, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s12, s12, 0xffff
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s36
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s15
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s35
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s30, s11, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s31, s10, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s18, s1, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s19, s0, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s20, s3, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s21, s2, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s22, s5, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s23, s4, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s24, s7, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s25, s6, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s26, s9, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s27, s8, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s28, s11, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s29, s10, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s30, s13, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s31, s12, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s33, s15, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s34, s14, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s35, s1, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s36, s0, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s3, s3, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s2, s2, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s9, s9, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s8, 0xffff
; GCN-NOHSA-VI-NEXT: s_and_b32 s11, s11, 0xffff
; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s10, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:112
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s28, s9, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
+; GCN-NOHSA-VI-NEXT: s_and_b32 s13, s13, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s12, s12, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s0, s15, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s1, s14, 0xffff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 0x70
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s1
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 0x60
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s34
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s13
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s33
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s29, s8, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s9, s9, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s8, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:96
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s26, s7, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 0x50
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s31
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s13
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s30
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s27, s6, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:80
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s24, s5, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 64
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s29
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s28
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s25, s4, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:64
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s22, s3, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 48
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s27
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s26
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s23, s2, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s3, s3, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s2, s2, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s20, s1, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 32
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s25
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s24
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s21, s0, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s1, s1, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s0, s0, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:32
-; GCN-NOHSA-VI-NEXT: s_nop 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s23
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s22
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s21
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s20
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s36
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s19
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s35
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s18
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s17
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v32i16_to_v32i32:
@@ -2649,83 +2749,109 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s19, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s18, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s35, s15, 16
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s36, s14, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s15, s15
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s14, s14
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s33, s13, 16
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s34, s12, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s13, s13
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s12, s12
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s36
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s15
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s35
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s18, s1, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s19, s0, 16
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s20, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s21, s0
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s22, s3, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s23, s2, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s24, s5, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s25, s4, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s26, s7, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s27, s6, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s28, s9, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s29, s8, 16
; GCN-NOHSA-VI-NEXT: s_ashr_i32 s30, s11, 16
; GCN-NOHSA-VI-NEXT: s_ashr_i32 s31, s10, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s11, s11
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s10, s10
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:112
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s28, s9, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s33, s13, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s34, s12, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s0, s15, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s1, s14, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 0x70
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s15, s15
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s14, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 0x60
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s15
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s13, s13
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s12, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 0x50
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s34
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s13
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s33
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s29, s8, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s9, s9
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s8, s8
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:96
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s26, s7, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s11, s11
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s10, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 64
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s31
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s30
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s27, s6, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:80
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s24, s5, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s9, s9
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s8, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 48
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s29
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s28
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s25, s4, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:64
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s22, s3, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 32
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s27
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s26
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s23, s2, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s3, s3
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s2, s2
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s20, s1, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s16, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s25
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s24
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s21, s0, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s1, s1
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s0, s0
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:32
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s17, 0
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s3, s3
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s2, s2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s23
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s22
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s21
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s1
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s20
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s21
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s19
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s20
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s18
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s17
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v32i16_to_v32i32:
@@ -3226,161 +3352,220 @@ define amdgpu_kernel void @constant_zextload_v64i16_to_v64i32(ptr addrspace(1) %
;
; GCN-NOHSA-VI-LABEL: constant_zextload_v64i16_to_v64i32:
; GCN-NOHSA-VI: ; %bb.0:
-; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s39, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s38, -1
+; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[36:39], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s36, s16
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s37, s17
-; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[16:31], s[18:19], 0x40
+; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x40
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s51, s15, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s52, s14, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s33, s1, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s34, s0, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s35, s3, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s40, s2, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s41, s5, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s42, s4, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s43, s7, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s44, s6, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s45, s9, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s46, s8, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s47, s11, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s48, s10, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s38, s13, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s39, s12, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s49, s15, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s50, s14, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s51, s17, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s52, s16, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s53, s19, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s54, s18, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s55, s21, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s56, s20, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s57, s23, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s58, s22, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s59, s25, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s60, s24, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s61, s27, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s62, s26, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s63, s29, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s64, s28, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s65, s31, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s66, s30, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s1, s1, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s0, s0, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s3, s3, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s2, s2, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s67, s9, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s68, s8, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s11, s11, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s10, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s13, s13, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s12, s12, 0xffff
; GCN-NOHSA-VI-NEXT: s_and_b32 s15, s15, 0xffff
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s67, s31, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s68, s30, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s31, s31, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s30, s30, 0xffff
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s65, s29, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s66, s28, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s29, s29, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s28, s28, 0xffff
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s30
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s68
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s31
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s67
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s63, s27, 16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s64, s26, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s14, s14, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s17, s17, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s16, s16, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s19, s19, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s18, s18, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s21, s21, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s20, s20, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s23, s23, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s22, s22, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s25, s25, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s24, s24, 0xffff
; GCN-NOHSA-VI-NEXT: s_and_b32 s27, s27, 0xffff
; GCN-NOHSA-VI-NEXT: s_and_b32 s26, s26, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:240
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s61, s25, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s28
+; GCN-NOHSA-VI-NEXT: s_and_b32 s29, s29, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s28, s28, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s31, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s9, s30, 0xffff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s8
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s36, 0xf0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s9
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s66
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s29
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s65
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s62, s24, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s25, s25, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s24, s24, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:224
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s59, s23, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s26
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s36, 0xe0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s28
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s64
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s27
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s29
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s63
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s60, s22, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s23, s23, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s22, s22, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:208
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s57, s21, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s24
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s36, 0xd0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s26
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s62
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s25
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s27
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s61
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s58, s20, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s21, s21, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s20, s20, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:192
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s55, s19, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s22
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s36, 0xc0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s24
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s60
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s23
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s25
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s59
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s56, s18, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s19, s19, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s18, s18, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:176
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s53, s17, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s20
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s36, 0xb0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s22
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s58
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s21
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s23
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s57
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s54, s16, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s17, s17, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s16, s16, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:160
-; GCN-NOHSA-VI-NEXT: s_and_b32 s14, s14, 0xffff
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s18
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s36, 0xa0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s20
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s56
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s19
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s21
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s55
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:144
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s49, s13, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s36, 0x90
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s18
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s54
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s17
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s19
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s53
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s50, s12, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s13, s13, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s12, s12, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:128
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s47, s11, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s36, 0x80
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s52
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s15
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s17
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s51
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s48, s10, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s11, s11, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s10, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:112
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s45, s9, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s36, 0x70
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s50
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s15
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s49
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s46, s8, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s9, s9, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s8, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:96
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s43, s7, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s36, 0x60
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s39
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s38
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s36, 0x50
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s48
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s47
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s44, s6, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:80
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s41, s5, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s36, 64
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s68
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s46
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s67
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s45
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s42, s4, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:64
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s35, s3, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s44
+; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s36, 48
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s44
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s43
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s40, s2, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s3, s3, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s2, s2, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s33, s1, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s42
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s36, 32
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s42
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s41
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s34, s0, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s1, s1, 0xffff
-; GCN-NOHSA-VI-NEXT: s_and_b32 s0, s0, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:32
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s40
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s36, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s3
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s40
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s35
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s36
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s34
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s33
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s37
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v64i16_to_v64i32:
@@ -3959,161 +4144,217 @@ define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(ptr addrspace(1) %
;
; GCN-NOHSA-VI-LABEL: constant_sextload_v64i16_to_v64i32:
; GCN-NOHSA-VI: ; %bb.0:
-; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s39, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s38, -1
+; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[36:39], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[16:31], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s36, s0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s37, s1
-; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x40
+; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x0
+; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x40
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s51, s31, 16
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s52, s30, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s31, s31
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s67, s15, 16
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s68, s14, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s15, s15
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s14, s14
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s33, s17, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s34, s16, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s35, s19, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s38, s18, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s39, s21, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s40, s20, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s41, s23, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s42, s22, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s43, s25, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s44, s24, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s45, s27, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s46, s26, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s47, s29, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s48, s28, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s49, s31, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s50, s30, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s51, s1, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s52, s0, 16
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s53, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s54, s0
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s55, s3, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s56, s2, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s57, s5, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s58, s4, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s59, s7, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s60, s6, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s61, s9, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s62, s8, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s63, s11, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s64, s10, 16
; GCN-NOHSA-VI-NEXT: s_ashr_i32 s65, s13, 16
; GCN-NOHSA-VI-NEXT: s_ashr_i32 s66, s12, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s13, s13
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s12, s12
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s0, s15, 16
+; GCN-NOHSA-VI-NEXT: s_ashr_i32 s1, s14, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0xf0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s15, s15
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s14, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0xe0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s68
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s15
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s67
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s63, s11, 16
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s64, s10, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s11, s11
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s10, s10
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:240
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s61, s9, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s13, s13
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s12, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0xd0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s66
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s13
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s65
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s62, s8, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s9, s9
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s8, s8
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:224
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s59, s7, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s11, s11
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s10, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0xc0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s64
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s63
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s60, s6, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:208
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s57, s5, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s9, s9
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s8, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0xb0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s62
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s61
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s58, s4, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:192
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s55, s3, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s7, s7
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s6, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0xa0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s60
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s59
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s56, s2, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s3, s3
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s2, s2
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:176
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s53, s1, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s5, s5
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s4, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0x90
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s58
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s57
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s54, s0, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s1, s1
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s0, s0
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:160
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s30, s30
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s3, s3
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s2, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0x80
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s56
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s55
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:144
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s49, s29, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s54
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s1
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s53
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s50, s28, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s29, s29
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s28, s28
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:128
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s47, s27, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s30
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0x70
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s54
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s52
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s31
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s53
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s51
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s48, s26, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s27, s27
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s26, s26
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:112
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s45, s25, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s28
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s31, s31
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s30, s30
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0x60
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s30
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s50
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s29
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s31
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s49
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s46, s24, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s25, s25
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s24, s24
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:96
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s43, s23, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s26
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s29, s29
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s28, s28
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 0x50
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s28
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s48
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s27
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s29
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s47
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s44, s22, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s23, s23
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s22, s22
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:80
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s41, s21, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s24
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s27, s27
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s26, s26
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 64
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s26
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s46
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s25
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s27
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s45
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s42, s20, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s21, s21
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s20, s20
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:64
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s35, s19, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s22
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s25, s25
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s24, s24
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 48
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s24
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s44
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s23
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s25
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s43
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s40, s18, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s19, s19
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s18, s18
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s33, s17, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s20
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s23, s23
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s22, s22
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 32
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s22
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s42
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s21
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s23
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s41
-; GCN-NOHSA-VI-NEXT: s_ashr_i32 s34, s16, 16
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s17, s17
-; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s16, s16
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:32
-; GCN-NOHSA-VI-NEXT: s_nop 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s18
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s21, s21
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s20, s20
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s0, s36, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s20
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s40
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s21
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s39
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s1, s37, 0
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s19, s19
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s18, s18
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s18
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s38
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s19
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s35
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s17, s17
+; GCN-NOHSA-VI-NEXT: s_sext_i32_i16 s16, s16
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s36
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s34
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s17
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s33
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s37
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v64i16_to_v64i32:
@@ -4360,20 +4601,16 @@ define amdgpu_kernel void @constant_zextload_i16_to_i64(ptr addrspace(1) %out, p
; GCN-NOHSA-VI-LABEL: constant_zextload_i16_to_i64:
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s6
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, 0
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v2, v[0:1]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_i16_to_i64:
@@ -4439,20 +4676,16 @@ define amdgpu_kernel void @constant_sextload_i16_to_i64(ptr addrspace(1) %out, p
; GCN-NOHSA-VI-LABEL: constant_sextload_i16_to_i64:
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s6
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s7
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v2, v[0:1]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_i16_to_i64:
@@ -4515,20 +4748,16 @@ define amdgpu_kernel void @constant_zextload_v1i16_to_v1i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI-LABEL: constant_zextload_v1i16_to_v1i64:
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s6
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s7
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, 0
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v2, v[0:1]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NOHSA-VI-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v1i16_to_v1i64:
@@ -4589,20 +4818,16 @@ define amdgpu_kernel void @constant_sextload_v1i16_to_v1i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI-LABEL: constant_sextload_v1i16_to_v1i64:
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s6
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, s7
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s2
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s9, s3
-; GCN-NOHSA-VI-NEXT: buffer_load_ushort v0, off, s[8:11], 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
+; GCN-NOHSA-VI-NEXT: flat_load_ushort v2, v[0:1]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt vmcnt(0)
-; GCN-NOHSA-VI-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GCN-NOHSA-VI-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GCN-NOHSA-VI-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v1i16_to_v1i64:
@@ -4668,19 +4893,17 @@ define amdgpu_kernel void @constant_zextload_v2i16_to_v2i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dword s2, s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s0, s2, 16
; GCN-NOHSA-VI-NEXT: s_and_b32 s1, s2, 0xffff
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s0
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v2i16_to_v2i64:
@@ -4750,18 +4973,18 @@ define amdgpu_kernel void @constant_sextload_v2i16_to_v2i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dword s4, s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-VI-NEXT: s_load_dword s2, s[2:3], 0x0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s4, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s7
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s5
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x100000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s2, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s3
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v2i16_to_v2i64:
@@ -4846,25 +5069,26 @@ define amdgpu_kernel void @constant_zextload_v4i16_to_v4i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, 0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s7, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, -1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s5, s1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s0, s2, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s1, s2, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s2, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s2, 0xffff
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s3, 16
; GCN-NOHSA-VI-NEXT: s_and_b32 s3, s3, 0xffff
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s1
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s0
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s3
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s5
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v4i16_to_v4i64:
@@ -4963,28 +5187,31 @@ define amdgpu_kernel void @constant_sextload_v4i16_to_v4i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI: ; %bb.0:
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
+; GCN-NOHSA-VI-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s5
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s5, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s4, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[2:3], 0x100000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s2, 16
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, s3
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s8, s3, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s9
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s10
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s11
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
+; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s0, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s7
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s5
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s9
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s5
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v4i16_to_v4i64:
@@ -5110,31 +5337,41 @@ define amdgpu_kernel void @constant_zextload_v8i16_to_v8i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s11, s7, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s6, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s7
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s11
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s8, s4, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s9, s5, 16
; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s8, s4, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s6, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s7, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s3, s7, 0xffff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 48
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s3
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 32
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s10
-; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s9
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s8
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v8i16_to_v8i64:
@@ -5293,45 +5530,55 @@ define amdgpu_kernel void @constant_sextload_v8i16_to_v8i64(ptr addrspace(1) %ou
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[6:7], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[6:7], 0x100000
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s6, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[6:7], 0x100000
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, s7
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x100000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s4, 16
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s8, s5
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s10, s5, 16
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[16:17], s[6:7], 0x100000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, s7
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[18:19], s[6:7], 0x100000
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s7, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, s5
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s12, s5, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s18
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s19
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6
+; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s0, 48
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s4, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s15
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s17
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
-; GCN-NOHSA-VI-NEXT: s_nop 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s11
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s12
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s13
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s17
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
+; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s0, 32
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s15
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
+; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s0, 16
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s9
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s11
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s5
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v8i16_to_v8i64:
@@ -5536,51 +5783,77 @@ define amdgpu_kernel void @constant_zextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s3, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s19, s9, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s9, s9, 0xffff
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s18, s8, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s8, 0xffff
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s9
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s19
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s12, s4, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s13, s5, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s14, s6, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s15, s7, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s16, s10, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s10, 0xffff
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s17, s11, 16
; GCN-NOHSA-VI-NEXT: s_and_b32 s11, s11, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s16, s10, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s18, s8, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s8, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s9, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s3, s9, 0xffff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 0x50
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s3
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 64
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 0x70
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s18
-; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s10, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s15, s7, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 0x60
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s11
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s17
-; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s14, s6, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 48
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s13, s5, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 32
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s15
-; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s12, s4, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s0, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s14
-; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s1, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s5
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s13
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s12
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v16i16_to_v16i64:
@@ -5862,79 +6135,106 @@ define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s11, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s10, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[30:31], s[4:5], 0x100000
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s12, s1
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s18, s1, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[16:17], s[2:3], 0x100000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s2, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[22:23], s[6:7], 0x100000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s6, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[28:29], s[4:5], 0x100000
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s4, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[34:35], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s5
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[12:13], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[18:19], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[18:19], s[2:3], 0x100000
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, s3
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[24:25], s[6:7], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s6, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[36:37], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s5, 16
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s14, s1
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s18, s1, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[26:27], s[6:7], 0x100000
; GCN-NOHSA-VI-NEXT: s_mov_b32 s6, s7
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[16:17], s[14:15], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[18:19], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[18:19], s[2:3], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s2, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[28:29], s[6:7], 0x100000
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s7, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s36
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s37
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s5
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[30:31], s[4:5], 0x100000
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s4, s5
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[0:1], 0x100000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s0, s0, 16
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[20:21], s[2:3], 0x100000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s2, s3
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:80
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[22:23], s[2:3], 0x100000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s30
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s31
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s34
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s35
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s2, s3, 16
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:64
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[26:27], s[6:7], 0x100000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s6, s7, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[34:35], s[4:5], 0x100000
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s4, s5, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x100000
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s8, 0x50
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s5
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s9, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s34
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s35
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s8, 64
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s9, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s28
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s29
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s30
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s31
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s8, 0x70
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s9, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s26
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s27
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:112
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[0:1], 0x100000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s24
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s25
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s26
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s27
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:96
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s0, s0, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s8, 0x60
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s9, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s22
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s23
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s24
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s25
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s8, 48
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s3
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s18
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s19
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s20
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s21
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:32
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s9, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s8, 32
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s20
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s21
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s9, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s8, 16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s17
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s14
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s15
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_nop 0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s18
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s19
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s9, 0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s15
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s12
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s13
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s11
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s1
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v16i16_to_v16i64:
@@ -6296,91 +6596,150 @@ define amdgpu_kernel void @constant_zextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, v1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s19, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s18, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s27, s15, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s15, s15, 0xffff
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s20, s1, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s21, s3, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s22, s5, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s23, s7, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s24, s9, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s25, s11, 16
; GCN-NOHSA-VI-NEXT: s_lshr_b32 s26, s13, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s27, s15, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s28, s14, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s29, s12, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s30, s10, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s31, s8, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s33, s6, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s34, s4, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s19, s2, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s18, s0, 16
+; GCN-NOHSA-VI-NEXT: s_and_b32 s0, s0, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s2, s2, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s35, s4, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s8, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s10, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s12, s12, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s14, s14, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s1, s1, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s3, s3, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s36, s5, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s9, s9, 0xffff
+; GCN-NOHSA-VI-NEXT: s_and_b32 s11, s11, 0xffff
; GCN-NOHSA-VI-NEXT: s_and_b32 s13, s13, 0xffff
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s15
+; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s15, 0xffff
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0xf0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s27
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s25, s11, 16
-; GCN-NOHSA-VI-NEXT: s_and_b32 s11, s11, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:240
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s24, s9, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0xd0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s13
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s26
-; GCN-NOHSA-VI-NEXT: s_and_b32 s9, s9, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:208
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s23, s7, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0xb0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s11
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s25
-; GCN-NOHSA-VI-NEXT: s_and_b32 s7, s7, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:176
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s22, s5, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0x90
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s9
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s24
-; GCN-NOHSA-VI-NEXT: s_and_b32 s5, s5, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:144
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s21, s3, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0x70
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s7
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s23
-; GCN-NOHSA-VI-NEXT: s_and_b32 s3, s3, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:112
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s20, s1, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s5
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0x50
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s36
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s22
-; GCN-NOHSA-VI-NEXT: s_and_b32 s1, s1, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:80
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s28, s14, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 48
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s21
-; GCN-NOHSA-VI-NEXT: s_and_b32 s14, s14, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s29, s12, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 16
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s1
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s20
-; GCN-NOHSA-VI-NEXT: s_and_b32 s12, s12, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s30, s10, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0xe0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s14
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s28
-; GCN-NOHSA-VI-NEXT: s_and_b32 s10, s10, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:224
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s31, s8, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0xc0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s12
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s29
-; GCN-NOHSA-VI-NEXT: s_and_b32 s8, s8, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:192
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s33, s6, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0xa0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s10
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s30
-; GCN-NOHSA-VI-NEXT: s_and_b32 s6, s6, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:160
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s34, s4, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0x80
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s31
-; GCN-NOHSA-VI-NEXT: s_and_b32 s4, s4, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:128
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s35, s2, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 0x60
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s33
-; GCN-NOHSA-VI-NEXT: s_and_b32 s2, s2, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:96
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s36, s0, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 64
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s35
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s34
-; GCN-NOHSA-VI-NEXT: s_and_b32 s0, s0, 0xffff
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:64
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s2
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s35
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:32
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s16, 32
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s19
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s16
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s0
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s36
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s18
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s17
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_zextload_v32i16_to_v32i64:
@@ -6908,139 +7267,207 @@ define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(ptr addrspace(1) %
; GCN-NOHSA-VI-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NOHSA-VI-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s19, 0xf000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s18, -1
; GCN-NOHSA-VI-NEXT: s_waitcnt lgkmcnt(0)
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s38, s15
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s40, s13
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s54, s14, 16
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[36:37], s[14:15], 0x100000
-; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[14:15], s[14:15], 48
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x100000
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s42, s11
-; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[82:83], s[12:13], 48
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s46, s15
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s48, s13
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s50, s11
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s52, s9
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s54, s7
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s56, s5
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s44, s3
+; GCN-NOHSA-VI-NEXT: s_mov_b32 s40, s1
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s58, s14, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s60, s12, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s62, s10, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s64, s8, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s66, s6, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s68, s4, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s70, s2, 16
+; GCN-NOHSA-VI-NEXT: s_lshr_b32 s72, s0, 16
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[18:19], s[0:1], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[20:21], s[2:3], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[22:23], s[4:5], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[24:25], s[6:7], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[26:27], s[8:9], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[28:29], s[10:11], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[30:31], s[12:13], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[34:35], s[14:15], 0x100000
+; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[36:37], s[0:1], 48
+; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[38:39], s[2:3], 48
+; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[42:43], s[4:5], 48
+; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[74:75], s[6:7], 48
+; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[76:77], s[8:9], 48
+; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[78:79], s[10:11], 48
+; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[80:81], s[12:13], 48
+; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[82:83], s[14:15], 48
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[0:1], s[72:73], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[2:3], s[70:71], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[68:69], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[66:67], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[64:65], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[62:63], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[60:61], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[14:15], s[58:59], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x100000
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s38
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s39
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s14
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s15
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s44, s9
-; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[80:81], s[10:11], 48
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:240
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s46, s7
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s40
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s41
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s82
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s83
-; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[78:79], s[8:9], 48
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:208
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s48, s5
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s42
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s43
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s80
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s81
-; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[76:77], s[6:7], 48
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:176
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s50, s3
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s44
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s45
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s78
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s79
-; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[74:75], s[4:5], 48
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x100000
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x100000
; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:144
-; GCN-NOHSA-VI-NEXT: s_mov_b32 s52, s1
+; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x100000
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s46
+; GCN-NOHSA-VI-NEXT: s_add_u32 s46, s16, 0xf0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s47
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s76
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s77
-; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[72:73], s[2:3], 48
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:112
-; GCN-NOHSA-VI-NEXT: s_ashr_i64 s[70:71], s[0:1], 48
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s47, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s46
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s82
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s83
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s47
+; GCN-NOHSA-VI-NEXT: s_add_u32 s46, s16, 0xd0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s47, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s46
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s48
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s49
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s74
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s75
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:80
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s56, s12, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s80
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s81
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s47
+; GCN-NOHSA-VI-NEXT: s_add_u32 s46, s16, 0xb0
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s47, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s46
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s50
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s51
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s72
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s73
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:48
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s58, s10, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s78
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s79
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s47
+; GCN-NOHSA-VI-NEXT: s_add_u32 s46, s16, 0x90
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s47, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s46
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s52
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s53
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s70
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s71
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[34:35], s[12:13], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[12:13], s[56:57], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s60, s8, 16
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s36
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s37
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s54
-; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s55
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[30:31], s[10:11], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[10:11], s[58:59], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:224
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s62, s6, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s76
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s77
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s47
+; GCN-NOHSA-VI-NEXT: s_add_u32 s46, s16, 0x70
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s47, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s46
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s54
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s55
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s74
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s75
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s47
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s42
+; GCN-NOHSA-VI-NEXT: s_add_u32 s42, s16, 0x50
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s43
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s43, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s42
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s56
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s57
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s43
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s38
+; GCN-NOHSA-VI-NEXT: s_add_u32 s38, s16, 48
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s39
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s39, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s38
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s44
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s45
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s39
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s36
+; GCN-NOHSA-VI-NEXT: s_add_u32 s36, s16, 16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s37
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s37, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s36
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s40
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s41
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s37
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s14
+; GCN-NOHSA-VI-NEXT: s_add_u32 s14, s16, 0xe0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s15
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s15, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s14
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s34
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s35
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s15
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s12
+; GCN-NOHSA-VI-NEXT: s_add_u32 s12, s16, 0xc0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s13
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[28:29], s[8:9], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[8:9], s[60:61], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:192
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s64, s4, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s13, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s12
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s30
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s31
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s13
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s10
+; GCN-NOHSA-VI-NEXT: s_add_u32 s10, s16, 0xa0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s11
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[26:27], s[6:7], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[6:7], s[62:63], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:160
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s66, s2, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s11, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s10
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s28
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s29
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s11
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s8
+; GCN-NOHSA-VI-NEXT: s_add_u32 s8, s16, 0x80
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s9
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[24:25], s[4:5], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[4:5], s[64:65], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:128
-; GCN-NOHSA-VI-NEXT: s_lshr_b32 s68, s0, 16
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s9, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s8
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s26
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s27
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s9
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s6
+; GCN-NOHSA-VI-NEXT: s_add_u32 s6, s16, 0x60
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s7
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[22:23], s[2:3], 0x100000
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[2:3], s[66:67], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:96
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[20:21], s[0:1], 0x100000
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s7, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s6
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s24
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s25
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s7
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s4
+; GCN-NOHSA-VI-NEXT: s_add_u32 s4, s16, 64
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s5
-; GCN-NOHSA-VI-NEXT: s_bfe_i64 s[0:1], s[68:69], 0x100000
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:64
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s5, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s4
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s22
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s23
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s5
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: s_nop 0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s2
+; GCN-NOHSA-VI-NEXT: s_add_u32 s2, s16, 32
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s3
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:32
-; GCN-NOHSA-VI-NEXT: s_nop 0
+; GCN-NOHSA-VI-NEXT: s_addc_u32 s3, s17, 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s3
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s20
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s21
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s2
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v4, s16
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v0, s18
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v1, s19
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v2, s0
; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v3, s1
-; GCN-NOHSA-VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
+; GCN-NOHSA-VI-NEXT: v_mov_b32_e32 v5, s17
+; GCN-NOHSA-VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GCN-NOHSA-VI-NEXT: s_endpgm
;
; EG-LABEL: constant_sextload_v32i16_to_v32i64:
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
index 9cea104c46290..6de7af87c5cc6 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
@@ -1,486 +1,4818 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6-NOHSA %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GFX7-HSA %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8-NOHSA %s
+; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9-HSA %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9-HSA %s
-; FUNC-LABEL: {{^}}constant_load_i32:
-; GCN: s_load_dword s{{[0-9]+}}
-
-; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
define amdgpu_kernel void @constant_load_i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_i32:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_i32:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: flat_store_dword v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_i32:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_i32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_load_i32:
+; GFX9-HSA: ; %bb.0: ; %entry
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-HSA-NEXT: global_store_dword v0, v1, s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
entry:
%ld = load i32, ptr addrspace(4) %in
store i32 %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v2i32:
-; GCN: s_load_dwordx2
-
-; EG: VTX_READ_64
define amdgpu_kernel void @constant_load_v2i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v2i32:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v2i32:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v2i32:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v2i32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_load_v2i32:
+; GFX9-HSA: ; %bb.0: ; %entry
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-HSA-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
entry:
%ld = load <2 x i32>, ptr addrspace(4) %in
store <2 x i32> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v3i32:
-; GCN: s_load_dwordx4
-
-; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v3i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v3i32:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v3i32:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v3i32:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NOHSA-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v3i32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 6, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.X, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: MOV * T2.X, T0.Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T3.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_load_v3i32:
+; GFX9-HSA: ; %bb.0: ; %entry
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-HSA-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
entry:
%ld = load <3 x i32>, ptr addrspace(4) %in
store <3 x i32> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v4i32:
-; GCN: s_load_dwordx4
-
-; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v4i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v4i32:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v4i32:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v4i32:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v4i32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_load_v4i32:
+; GFX9-HSA: ; %bb.0: ; %entry
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
entry:
%ld = load <4 x i32>, ptr addrspace(4) %in
store <4 x i32> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v8i32:
-; GCN: s_load_dwordx8
-
-; EG: VTX_READ_128
-; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v8i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v8i32:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v8i32:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX7-HSA-NEXT: s_add_u32 s10, s8, 16
+; GFX7-HSA-NEXT: s_addc_u32 s11, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s11
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v8i32:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s8, 16
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s11
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v8i32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @6
+; EG-NEXT: ALU 4, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T2.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR * T3.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_load_v8i32:
+; GFX9-HSA: ; %bb.0: ; %entry
+; GFX9-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX9-HSA-NEXT: v_mov_b32_e32 v6, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9] offset:16
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[4:7], s[8:9]
+; GFX9-HSA-NEXT: s_endpgm
entry:
%ld = load <8 x i32>, ptr addrspace(4) %in
store <8 x i32> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v9i32:
-; GCN: s_load_dword
-; GCN: s_load_dwordx8
-
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_32
define amdgpu_kernel void @constant_load_v9i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v9i32:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s12, s[10:11], 0x8
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[8:11], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v9i32:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s12, s[10:11], 0x8
+; GFX7-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX7-HSA-NEXT: s_add_u32 s10, s8, 32
+; GFX7-HSA-NEXT: s_addc_u32 s11, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s8, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: flat_store_dword v[4:5], v6
+; GFX7-HSA-NEXT: s_addc_u32 s5, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v9i32:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s12, s[10:11], 0x20
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s8, 32
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s8, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: flat_store_dword v[4:5], v6
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v9i32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 2 @8
+; EG-NEXT: ALU 7, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T5.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T4.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T3.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 0, #1
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 32, #1
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 15:
+; EG-NEXT: LSHR T3.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T4.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR * T5.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_load_v9i32:
+; GFX9-HSA: ; %bb.0: ; %entry
+; GFX9-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dword s12, s[10:11], 0x20
+; GFX9-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v5, s12
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX9-HSA-NEXT: global_store_dword v8, v5, s[8:9] offset:32
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9] offset:16
+; GFX9-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX9-HSA-NEXT: v_mov_b32_e32 v6, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[4:7], s[8:9]
+; GFX9-HSA-NEXT: s_endpgm
entry:
%ld = load <9 x i32>, ptr addrspace(4) %in
store <9 x i32> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v10i32:
-; GCN: s_load_dwordx2
-; GCN: s_load_dwordx8
-
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v10i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v10i32:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[12:13], s[10:11], 0x8
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v10i32:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[12:13], s[10:11], 0x8
+; GFX7-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX7-HSA-NEXT: s_add_u32 s10, s8, 32
+; GFX7-HSA-NEXT: s_addc_u32 s11, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s8, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[4:5], v[6:7]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v10i32:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[12:13], s[10:11], 0x20
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s8, 32
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s8, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[4:5], v[6:7]
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v10i32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 2 @8
+; EG-NEXT: ALU 8, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T5.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T4.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T3.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 0, #1
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 32, #1
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 15:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T3.X, PV.W, literal.x,
+; EG-NEXT: LSHR * T4.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T5.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_load_v10i32:
+; GFX9-HSA: ; %bb.0: ; %entry
+; GFX9-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx2 s[12:13], s[10:11], 0x20
+; GFX9-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v5, s12
+; GFX9-HSA-NEXT: v_mov_b32_e32 v6, s13
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX9-HSA-NEXT: global_store_dwordx2 v8, v[5:6], s[8:9] offset:32
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[8:9] offset:16
+; GFX9-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX9-HSA-NEXT: v_mov_b32_e32 v6, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[4:7], s[8:9]
+; GFX9-HSA-NEXT: s_endpgm
entry:
%ld = load <10 x i32>, ptr addrspace(4) %in
store <10 x i32> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v11i32:
-; GCN: s_load_dwordx4
-; GCN: s_load_dwordx8
-
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v11i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v11i32:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[12:15], s[10:11], 0x8
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[8:11], 0 offset:40
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v11i32:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[12:15], s[10:11], 0x8
+; GFX7-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX7-HSA-NEXT: s_add_u32 s10, s8, 16
+; GFX7-HSA-NEXT: s_addc_u32 s11, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s11
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[7:8], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s9
+; GFX7-HSA-NEXT: s_add_u32 s0, s8, 32
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[7:8], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: flat_store_dwordx3 v[0:1], v[4:6]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v11i32:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[12:15], s[10:11], 0x20
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s8, 16
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s11
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[7:8], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s9
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 32
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[7:8], v[0:3]
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: flat_store_dwordx3 v[0:1], v[4:6]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v11i32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 2 @8
+; EG-NEXT: ALU 13, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T7.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T6.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T5.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T3.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 0, #1
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 32, #1
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 15:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T3.X, PV.W, literal.x,
+; EG-NEXT: MOV * T4.X, T0.Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 40(5.605194e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T5.X, PV.W, literal.x,
+; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T7.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_load_v11i32:
+; GFX9-HSA: ; %bb.0: ; %entry
+; GFX9-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v7, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx4 s[12:15], s[10:11], 0x20
+; GFX9-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-HSA-NEXT: global_store_dwordx4 v7, v[0:3], s[8:9] offset:16
+; GFX9-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX9-HSA-NEXT: v_mov_b32_e32 v6, s14
+; GFX9-HSA-NEXT: global_store_dwordx4 v7, v[0:3], s[8:9]
+; GFX9-HSA-NEXT: global_store_dwordx3 v7, v[4:6], s[8:9] offset:32
+; GFX9-HSA-NEXT: s_endpgm
entry:
%ld = load <11 x i32>, ptr addrspace(4) %in
store <11 x i32> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v12i32:
-; GCN: s_load_dwordx4
-; GCN: s_load_dwordx8
-
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v12i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v12i32:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[12:15], s[10:11], 0x8
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v12i32:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[12:15], s[10:11], 0x8
+; GFX7-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX7-HSA-NEXT: s_add_u32 s10, s8, 32
+; GFX7-HSA-NEXT: s_addc_u32 s11, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s10
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s8, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v12i32:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[12:15], s[10:11], 0x20
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s8, 32
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s10
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s8, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v12i32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 7, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 2 @8
+; EG-NEXT: ALU 1, @22, KC0[], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T5.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T1.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T3.XYZW, T2.X, 32, #1
+; EG-NEXT: VTX_READ_128 T4.XYZW, T2.X, 16, #1
+; EG-NEXT: VTX_READ_128 T2.XYZW, T2.X, 0, #1
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T1.X, PV.W, literal.x,
+; EG-NEXT: MOV * T2.X, KC0[2].Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 22:
+; EG-NEXT: LSHR * T5.X, T0.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_load_v12i32:
+; GFX9-HSA: ; %bb.0: ; %entry
+; GFX9-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v12, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx4 s[12:15], s[10:11], 0x20
+; GFX9-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX9-HSA-NEXT: v_mov_b32_e32 v8, s0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v9, s1
+; GFX9-HSA-NEXT: v_mov_b32_e32 v10, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v11, s3
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v6, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v7, s7
+; GFX9-HSA-NEXT: global_store_dwordx4 v12, v[0:3], s[8:9] offset:32
+; GFX9-HSA-NEXT: global_store_dwordx4 v12, v[4:7], s[8:9] offset:16
+; GFX9-HSA-NEXT: global_store_dwordx4 v12, v[8:11], s[8:9]
+; GFX9-HSA-NEXT: s_endpgm
entry:
%ld = load <12 x i32>, ptr addrspace(4) %in
store <12 x i32> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v16i32:
-; GCN: s_load_dwordx16
-
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v16i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v16i32:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s19, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s18, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v16i32:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 48
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s19
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s16, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v16i32:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX8-NOHSA-NEXT: s_add_u32 s18, s16, 48
+; GFX8-NOHSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s19
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s16, 32
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v16i32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 10, @16, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 3 @8
+; EG-NEXT: ALU 1, @27, KC0[], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T7.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T2.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T1.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T4.XYZW, T3.X, 48, #1
+; EG-NEXT: VTX_READ_128 T5.XYZW, T3.X, 32, #1
+; EG-NEXT: VTX_READ_128 T6.XYZW, T3.X, 16, #1
+; EG-NEXT: VTX_READ_128 T3.XYZW, T3.X, 0, #1
+; EG-NEXT: ALU clause starting at 16:
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T1.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T2.X, PV.W, literal.x,
+; EG-NEXT: MOV * T3.X, KC0[2].Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 27:
+; EG-NEXT: LSHR * T7.X, T0.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_load_v16i32:
+; GFX9-HSA: ; %bb.0: ; %entry
+; GFX9-HSA-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX9-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX9-HSA-NEXT: v_mov_b32_e32 v6, s10
+; GFX9-HSA-NEXT: v_mov_b32_e32 v7, s11
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:48
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[4:7], s[16:17] offset:32
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17] offset:16
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[16:17]
+; GFX9-HSA-NEXT: s_endpgm
entry:
%ld = load <16 x i32>, ptr addrspace(4) %in
store <16 x i32> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_i32_to_i64:
-; GCN-DAG: s_load_dword s[[SLO:[0-9]+]],
-; GCN-DAG: v_mov_b32_e32 v[[SHI:[0-9]+]], 0{{$}}
-; GCN: store_dwordx2
-
-; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
-; EG: CF_END
-; EG: VTX_READ_32
define amdgpu_kernel void @constant_zextload_i32_to_i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_i32_to_i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_i32_to_i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, 0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_i32_to_i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, 0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_i32_to_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV * T0.Y, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_zextload_i32_to_i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-HSA-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load i32, ptr addrspace(4) %in
%ext = zext i32 %ld to i64
store i64 %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_i32_to_i64:
-; GCN: s_load_dword s[[SLO:[0-9]+]]
-; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[SLO]], 31
-; GCN: store_dwordx2
-
-; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
-; EG: CF_END
-; EG: VTX_READ_32
-; EG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.
-; EG: 31
define amdgpu_kernel void @constant_sextload_i32_to_i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_i32_to_i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s5, s4, 31
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_i32_to_i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s0, s2, 31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_i32_to_i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_ashr_i32 s0, s2, 31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_i32_to_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: ASHR * T0.Y, T0.X, literal.y,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
+;
+; GFX9-HSA-LABEL: constant_sextload_i32_to_i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_ashr_i32 s3, s2, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-HSA-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load i32, ptr addrspace(4) %in
%ext = sext i32 %ld to i64
store i64 %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v1i32_to_v1i64:
-; GCN: s_load_dword
-; GCN: store_dwordx2
define amdgpu_kernel void @constant_zextload_v1i32_to_v1i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v1i32_to_v1i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v1i32_to_v1i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, 0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v1i32_to_v1i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, 0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v1i32_to_v1i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV * T0.Y, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_zextload_v1i32_to_v1i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-HSA-NEXT: global_store_dwordx2 v1, v[0:1], s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <1 x i32>, ptr addrspace(4) %in
%ext = zext <1 x i32> %ld to <1 x i64>
store <1 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v1i32_to_v1i64:
-; GCN: s_load_dword s[[LO:[0-9]+]]
-; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[LO]], 31
-; GCN: store_dwordx2
define amdgpu_kernel void @constant_sextload_v1i32_to_v1i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v1i32_to_v1i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s5, s4, 31
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v1i32_to_v1i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s0, s2, 31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v1i32_to_v1i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_ashr_i32 s0, s2, 31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v1i32_to_v1i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: ASHR * T0.Y, T0.X, literal.y,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
+;
+; GFX9-HSA-LABEL: constant_sextload_v1i32_to_v1i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_ashr_i32 s3, s2, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-HSA-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <1 x i32>, ptr addrspace(4) %in
%ext = sext <1 x i32> %ld to <1 x i64>
store <1 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v2i32_to_v2i64:
-; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
-; GCN: store_dwordx4
define amdgpu_kernel void @constant_zextload_v2i32_to_v2i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v2i32_to_v2i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v2i32_to_v2i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v2i32_to_v2i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v2i32_to_v2i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 5, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV T1.X, T0.X,
+; EG-NEXT: MOV T1.Y, 0.0,
+; EG-NEXT: MOV T1.Z, T0.Y,
+; EG-NEXT: MOV T1.W, 0.0,
+; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_zextload_v2i32_to_v2i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <2 x i32>, ptr addrspace(4) %in
%ext = zext <2 x i32> %ld to <2 x i64>
store <2 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v2i32_to_v2i64:
-; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
-
-; GCN-DAG: s_ashr_i32
-; GCN-DAG: s_ashr_i32
-
-; GCN: store_dwordx4
define amdgpu_kernel void @constant_sextload_v2i32_to_v2i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v2i32_to_v2i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s7, s5, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s8, s4, 31
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v2i32_to_v2i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s1, s3, 31
+; GFX7-HSA-NEXT: s_mov_b32 s0, s3
+; GFX7-HSA-NEXT: s_ashr_i32 s3, s2, 31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v2i32_to_v2i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_ashr_i32 s1, s3, 31
+; GFX8-NOHSA-NEXT: s_mov_b32 s0, s3
+; GFX8-NOHSA-NEXT: s_ashr_i32 s3, s2, 31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v2i32_to_v2i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: ASHR * T1.W, T0.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR * T1.Y, T0.X, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T1.X, T0.X,
+; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV * T1.Z, T0.Y,
+;
+; GFX9-HSA-LABEL: constant_sextload_v2i32_to_v2i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_ashr_i32 s5, s3, 31
+; GFX9-HSA-NEXT: s_mov_b32 s4, s3
+; GFX9-HSA-NEXT: s_ashr_i32 s3, s2, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <2 x i32>, ptr addrspace(4) %in
%ext = sext <2 x i32> %ld to <2 x i64>
store <2 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v4i32_to_v4i64:
-; GCN: s_load_dwordx4
-
-; GCN: store_dwordx4
-; GCN: store_dwordx4
define amdgpu_kernel void @constant_zextload_v4i32_to_v4i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v4i32_to_v4i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v4i32_to_v4i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v4i32_to_v4i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v4i32_to_v4i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV T1.X, T0.Z,
+; EG-NEXT: MOV T1.Y, 0.0,
+; EG-NEXT: MOV * T2.X, T0.X,
+; EG-NEXT: MOV T2.Y, 0.0,
+; EG-NEXT: MOV T1.Z, T0.W,
+; EG-NEXT: MOV T1.W, 0.0,
+; EG-NEXT: MOV * T2.Z, T0.Y,
+; EG-NEXT: MOV * T2.W, 0.0,
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR * T3.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_zextload_v4i32_to_v4i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1] offset:16
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <4 x i32>, ptr addrspace(4) %in
%ext = zext <4 x i32> %ld to <4 x i64>
store <4 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v4i32_to_v4i64:
-; GCN: s_load_dwordx4
-
-; GCN: s_ashr_i32
-; GCN: s_ashr_i32
-; GCN: s_ashr_i32
-; GCN: s_ashr_i32
-
-; GCN: store_dwordx4
-; GCN: store_dwordx4
define amdgpu_kernel void @constant_sextload_v4i32_to_v4i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v4i32_to_v4i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s8, s5, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s9, s7, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s10, s6, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s11, s4, 31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s9
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s8
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v4i32_to_v4i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s8, s5, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s9, s4, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s2, s7, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s3, s6, 31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v4i32_to_v4i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_ashr_i32 s8, s5, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s9, s4, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s2, s7, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s3, s6, 31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v4i32_to_v4i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 15, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: ASHR * T1.W, T0.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,
+; EG-NEXT: ASHR T1.Y, T0.X, literal.y,
+; EG-NEXT: ASHR T3.W, T0.W, literal.y,
+; EG-NEXT: MOV * T1.X, T0.X,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
+; EG-NEXT: ASHR * T3.Y, T0.Z, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T3.X, T0.Z,
+; EG-NEXT: MOV T1.Z, T0.Y,
+; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T0.X, PV.W, literal.x,
+; EG-NEXT: MOV * T3.Z, T0.W,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_sextload_v4i32_to_v4i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_ashr_i32 s2, s5, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s3, s4, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s8, s7, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s9, s6, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX9-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX9-HSA-NEXT: v_mov_b32_e32 v6, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v7, s2
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1] offset:16
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <4 x i32>, ptr addrspace(4) %in
%ext = sext <4 x i32> %ld to <4 x i64>
store <4 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v8i32_to_v8i64:
-; GCN: s_load_dwordx8
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-SA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @constant_zextload_v8i32_to_v8i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v8i32_to_v8i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v8i32_to_v8i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 32
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v8i32_to_v8i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v8i32_to_v8i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @8
+; EG-NEXT: ALU 26, @13, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T7.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T6.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T1.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 13:
+; EG-NEXT: MOV T2.X, T1.Z,
+; EG-NEXT: MOV T2.Y, 0.0,
+; EG-NEXT: MOV * T3.X, T1.X,
+; EG-NEXT: MOV * T3.Y, 0.0,
+; EG-NEXT: MOV T4.X, T0.Z,
+; EG-NEXT: MOV T4.Y, 0.0,
+; EG-NEXT: MOV * T5.X, T0.X,
+; EG-NEXT: MOV T5.Y, 0.0,
+; EG-NEXT: MOV T2.Z, T1.W,
+; EG-NEXT: MOV T2.W, 0.0,
+; EG-NEXT: MOV * T3.Z, T1.Y,
+; EG-NEXT: MOV * T3.W, 0.0,
+; EG-NEXT: MOV T4.Z, T0.W,
+; EG-NEXT: MOV T4.W, 0.0,
+; EG-NEXT: MOV * T5.Z, T0.Y,
+; EG-NEXT: MOV * T5.W, 0.0,
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T1.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T6.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR * T7.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_zextload_v8i32_to_v8i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[8:9] offset:48
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[8:9] offset:32
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[8:9] offset:16
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[8:9]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <8 x i32>, ptr addrspace(4) %in
%ext = zext <8 x i32> %ld to <8 x i64>
store <8 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v8i32_to_v8i64:
-; GCN: s_load_dwordx8
-
-; GCN: s_ashr_i32
-; GCN: s_ashr_i32
-; GCN: s_ashr_i32
-; GCN: s_ashr_i32
-; GCN: s_ashr_i32
-; GCN: s_ashr_i32
-; GCN: s_ashr_i32
-; GCN: s_ashr_i32
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @constant_sextload_v8i32_to_v8i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v8i32_to_v8i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s12, s1, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s13, s0, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s14, s3, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s15, s2, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s16, s5, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s17, s7, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s18, s6, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s19, s4, 31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s3
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v14, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s18
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s17
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:48
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s16
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:32
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v9, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s14
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v13, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v15, s12
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v8i32_to_v8i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s10, s1, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s11, s0, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s12, s3, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s13, s2, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s14, s5, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s15, s4, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s16, s7, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s17, s6, 31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s8, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: s_addc_u32 s7, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s8, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: s_addc_u32 s5, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s8, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v8i32_to_v8i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_ashr_i32 s10, s1, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s11, s0, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s12, s3, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s13, s2, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s14, s5, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s15, s4, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s16, s7, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s17, s6, 31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s8, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s8, 32
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s8, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v8i32_to_v8i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @8
+; EG-NEXT: ALU 31, @13, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T0.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T5.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T2.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 13:
+; EG-NEXT: LSHR T2.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T3.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT T2.W, KC0[2].Y, literal.y,
+; EG-NEXT: ASHR * T4.W, T0.Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T5.X, PV.W, literal.x,
+; EG-NEXT: ASHR T4.Y, T0.X, literal.y,
+; EG-NEXT: ASHR T6.W, T0.W, literal.y,
+; EG-NEXT: MOV * T4.X, T0.X,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
+; EG-NEXT: ASHR T6.Y, T0.Z, literal.x,
+; EG-NEXT: ASHR * T7.W, T1.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T6.X, T0.Z,
+; EG-NEXT: ASHR T7.Y, T1.X, literal.x,
+; EG-NEXT: MOV T4.Z, T0.Y,
+; EG-NEXT: ASHR T8.W, T1.W, literal.x,
+; EG-NEXT: MOV * T7.X, T1.X,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR T8.Y, T1.Z, literal.x,
+; EG-NEXT: MOV * T6.Z, T0.W,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T8.X, T1.Z,
+; EG-NEXT: MOV T7.Z, T1.Y,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T0.X, PV.W, literal.x,
+; EG-NEXT: MOV * T8.Z, T1.W,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_sextload_v8i32_to_v8i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_ashr_i32 s16, s11, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s17, s10, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s14, s9, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s15, s8, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s16
+; GFX9-HSA-NEXT: s_ashr_i32 s12, s7, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s13, s6, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:48
+; GFX9-HSA-NEXT: s_ashr_i32 s2, s5, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX9-HSA-NEXT: s_ashr_i32 s3, s4, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:32
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1] offset:16
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s2
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <8 x i32>, ptr addrspace(4) %in
%ext = sext <8 x i32> %ld to <8 x i64>
store <8 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v16i32_to_v16i64:
-; GCN: s_load_dwordx16
-
-
-; GCN-DAG: s_ashr_i32
-
-; GCN: store_dwordx4
-; GCN: store_dwordx4
-; GCN: store_dwordx4
-; GCN: store_dwordx4
-; GCN: store_dwordx4
-; GCN: store_dwordx4
-; GCN: store_dwordx4
-; GCN: store_dwordx4
define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v16i32_to_v16i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s19, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s18, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s20, s1, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s21, s0, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s22, s3, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s23, s2, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s24, s5, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s25, s4, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s26, s7, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s27, s6, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s28, s9, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s29, s8, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s30, s11, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s31, s10, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s33, s13, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s34, s15, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s35, s14, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s36, s12, 31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v14, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v16, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v18, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v20, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v22, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v24, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v26, s3
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s35
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s34
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:112
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s36
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s33
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[16:19], 0 offset:96
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v9, s31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s30
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[16:19], 0 offset:80
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v13, s29
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v15, s28
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[16:19], 0 offset:64
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v17, s27
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v19, s26
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[16:19], 0 offset:48
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v21, s25
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v23, s24
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[20:23], off, s[16:19], 0 offset:32
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v25, s23
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v27, s22
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[24:27], off, s[16:19], 0 offset:16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s20
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v16i32_to_v16i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s18, s1, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s19, s0, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s20, s3, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s21, s2, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s22, s5, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s23, s4, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s24, s7, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s25, s6, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s26, s9, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s27, s8, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s28, s11, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s29, s10, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s30, s13, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s31, s12, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s33, s15, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s34, s14, 31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX7-HSA-NEXT: s_add_u32 s14, s16, 0x70
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX7-HSA-NEXT: s_addc_u32 s15, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s33
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s15
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX7-HSA-NEXT: s_add_u32 s12, s16, 0x60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX7-HSA-NEXT: s_addc_u32 s13, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX7-HSA-NEXT: s_add_u32 s10, s16, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX7-HSA-NEXT: s_addc_u32 s11, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s16, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s16, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v16i32_to_v16i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_ashr_i32 s18, s1, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s19, s0, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s20, s3, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s21, s2, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s22, s5, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s23, s4, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s24, s7, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s25, s6, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s26, s9, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s27, s8, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s28, s11, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s29, s10, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s30, s13, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s31, s12, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s33, s15, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s34, s14, 31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX8-NOHSA-NEXT: s_add_u32 s14, s16, 0x70
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX8-NOHSA-NEXT: s_addc_u32 s15, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s34
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s33
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s15
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NOHSA-NEXT: s_add_u32 s12, s16, 0x60
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX8-NOHSA-NEXT: s_addc_u32 s13, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s30
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s16, 0x50
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s28
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s16, 64
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s27
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s26
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 32
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s22
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s16, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s20
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v16i32_to_v16i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @20, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 3 @12
+; EG-NEXT: ALU 63, @21, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T1.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T11.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T9.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T8.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T7.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T6.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T5.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XYZW, T4.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 12:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 48, #1
+; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 32, #1
+; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 20:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 21:
+; EG-NEXT: LSHR T4.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T4.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T5.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T4.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T6.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T4.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T7.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T4.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T8.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T4.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T9.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT T4.W, KC0[2].Y, literal.y,
+; EG-NEXT: ASHR * T10.W, T0.Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T11.X, PV.W, literal.x,
+; EG-NEXT: ASHR T10.Y, T0.X, literal.y,
+; EG-NEXT: ASHR T12.W, T0.W, literal.y,
+; EG-NEXT: MOV * T10.X, T0.X,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
+; EG-NEXT: ASHR T12.Y, T0.Z, literal.x,
+; EG-NEXT: ASHR * T13.W, T3.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T12.X, T0.Z,
+; EG-NEXT: ASHR T13.Y, T3.X, literal.x,
+; EG-NEXT: MOV T10.Z, T0.Y,
+; EG-NEXT: ASHR T14.W, T3.W, literal.x,
+; EG-NEXT: MOV * T13.X, T3.X,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR T14.Y, T3.Z, literal.x,
+; EG-NEXT: MOV T12.Z, T0.W,
+; EG-NEXT: ASHR * T0.W, T2.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T14.X, T3.Z,
+; EG-NEXT: ASHR T0.Y, T2.X, literal.x,
+; EG-NEXT: MOV T13.Z, T3.Y,
+; EG-NEXT: ASHR T15.W, T2.W, literal.x,
+; EG-NEXT: MOV * T0.X, T2.X,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR T15.Y, T2.Z, literal.x,
+; EG-NEXT: MOV T14.Z, T3.W,
+; EG-NEXT: ASHR * T3.W, T1.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T15.X, T2.Z,
+; EG-NEXT: ASHR T3.Y, T1.X, literal.x,
+; EG-NEXT: MOV T0.Z, T2.Y,
+; EG-NEXT: ASHR T16.W, T1.W, literal.x,
+; EG-NEXT: MOV * T3.X, T1.X,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR T16.Y, T1.Z, literal.x,
+; EG-NEXT: MOV * T15.Z, T2.W,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T16.X, T1.Z,
+; EG-NEXT: MOV T3.Z, T1.Y,
+; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,
+; EG-NEXT: 112(1.569454e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T1.X, PV.W, literal.x,
+; EG-NEXT: MOV * T16.Z, T1.W,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_sextload_v16i32_to_v16i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_ashr_i32 s33, s15, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s34, s14, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s30, s13, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s31, s12, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s34
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s33
+; GFX9-HSA-NEXT: s_ashr_i32 s28, s11, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s29, s10, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] offset:112
+; GFX9-HSA-NEXT: s_ashr_i32 s26, s9, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s30
+; GFX9-HSA-NEXT: s_ashr_i32 s27, s8, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] offset:96
+; GFX9-HSA-NEXT: s_ashr_i32 s24, s7, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s28
+; GFX9-HSA-NEXT: s_ashr_i32 s25, s6, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] offset:80
+; GFX9-HSA-NEXT: s_ashr_i32 s22, s5, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s27
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s26
+; GFX9-HSA-NEXT: s_ashr_i32 s23, s4, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] offset:64
+; GFX9-HSA-NEXT: s_ashr_i32 s20, s3, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s24
+; GFX9-HSA-NEXT: s_ashr_i32 s21, s2, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] offset:48
+; GFX9-HSA-NEXT: s_ashr_i32 s18, s1, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s22
+; GFX9-HSA-NEXT: s_ashr_i32 s19, s0, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] offset:32
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s20
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17] offset:16
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX9-HSA-NEXT: global_store_dwordx4 v4, v[0:3], s[16:17]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <16 x i32>, ptr addrspace(4) %in
%ext = sext <16 x i32> %ld to <16 x i64>
store <16 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v16i32_to_v16i64
-; GCN: s_load_dwordx16
-
-; GCN-NOHSA: buffer_store_dwordx4
-; GCN-NOHSA: buffer_store_dwordx4
-; GCN-NOHSA: buffer_store_dwordx4
-; GCN-NOHSA: buffer_store_dwordx4
-; GCN-NOHSA: buffer_store_dwordx4
-; GCN-NOHSA: buffer_store_dwordx4
-; GCN-NOHSA: buffer_store_dwordx4
-; GCN-NOHSA: buffer_store_dwordx4
-
-; GCN-HSA: {{flat|global}}_store_dwordx4
-; GCN-HSA: {{flat|global}}_store_dwordx4
-; GCN-HSA: {{flat|global}}_store_dwordx4
-; GCN-HSA: {{flat|global}}_store_dwordx4
-; GCN-HSA: {{flat|global}}_store_dwordx4
-; GCN-HSA: {{flat|global}}_store_dwordx4
-; GCN-HSA: {{flat|global}}_store_dwordx4
-; GCN-HSA: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @constant_zextload_v16i32_to_v16i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v16i32_to_v16i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s19, 0xf000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s18, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:112
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:96
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:80
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:64
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v16i32_to_v16i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0x70
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s19
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX7-HSA-NEXT: s_add_u32 s12, s16, 0x60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX7-HSA-NEXT: s_addc_u32 s13, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX7-HSA-NEXT: s_add_u32 s10, s16, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX7-HSA-NEXT: s_addc_u32 s11, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s16, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s16, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v16i32_to_v16i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX8-NOHSA-NEXT: s_add_u32 s18, s16, 0x70
+; GFX8-NOHSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s19
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NOHSA-NEXT: s_add_u32 s12, s16, 0x60
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX8-NOHSA-NEXT: s_addc_u32 s13, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s16, 0x50
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s16, 64
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 32
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s16, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v16i32_to_v16i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @20, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 3 @12
+; EG-NEXT: ALU 54, @21, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T15.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T14.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T13.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T12.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T2.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XYZW, T1.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 12:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 48, #1
+; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 0, #1
+; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 32, #1
+; EG-NEXT: ALU clause starting at 20:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 21:
+; EG-NEXT: MOV T4.X, T1.Z,
+; EG-NEXT: MOV T4.Y, 0.0,
+; EG-NEXT: MOV * T5.X, T1.X,
+; EG-NEXT: MOV * T5.Y, 0.0,
+; EG-NEXT: MOV T6.X, T0.Z,
+; EG-NEXT: MOV T6.Y, 0.0,
+; EG-NEXT: MOV * T7.X, T0.X,
+; EG-NEXT: MOV * T7.Y, 0.0,
+; EG-NEXT: MOV T8.X, T3.Z,
+; EG-NEXT: MOV T8.Y, 0.0,
+; EG-NEXT: MOV * T9.X, T3.X,
+; EG-NEXT: MOV * T9.Y, 0.0,
+; EG-NEXT: MOV T10.X, T2.Z,
+; EG-NEXT: MOV T10.Y, 0.0,
+; EG-NEXT: MOV * T11.X, T2.X,
+; EG-NEXT: MOV T11.Y, 0.0,
+; EG-NEXT: MOV T4.Z, T1.W,
+; EG-NEXT: MOV T4.W, 0.0,
+; EG-NEXT: MOV * T5.Z, T1.Y,
+; EG-NEXT: MOV * T5.W, 0.0,
+; EG-NEXT: MOV T6.Z, T0.W,
+; EG-NEXT: MOV T6.W, 0.0,
+; EG-NEXT: MOV * T7.Z, T0.Y,
+; EG-NEXT: MOV * T7.W, 0.0,
+; EG-NEXT: MOV T8.Z, T3.W,
+; EG-NEXT: MOV T8.W, 0.0,
+; EG-NEXT: MOV * T9.Z, T3.Y,
+; EG-NEXT: MOV * T9.W, 0.0,
+; EG-NEXT: MOV T10.Z, T2.W,
+; EG-NEXT: MOV T10.W, 0.0,
+; EG-NEXT: MOV * T11.Z, T2.Y,
+; EG-NEXT: MOV * T11.W, 0.0,
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T1.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T2.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T3.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T12.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T13.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: LSHR T14.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43)
+; EG-NEXT: LSHR * T15.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_zextload_v16i32_to_v16i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[16:17] offset:112
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[16:17] offset:96
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[16:17] offset:80
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[16:17] offset:64
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[16:17] offset:48
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[16:17] offset:32
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[16:17] offset:16
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[16:17]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <16 x i32>, ptr addrspace(4) %in
%ext = zext <16 x i32> %ld to <16 x i64>
store <16 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v32i32_to_v32i64:
-
-; GCN: s_load_dwordx16
-; GCN-DAG: s_load_dwordx16
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-
define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v32i32_to_v32i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s39, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s38, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s36, s16
+; GFX6-NOHSA-NEXT: s_mov_b32 s37, s17
+; GFX6-NOHSA-NEXT: s_load_dwordx16 s[16:31], s[18:19], 0x10
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s33, s1, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s34, s0, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s35, s3, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s40, s2, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s41, s5, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s42, s4, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s43, s7, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s44, s6, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s45, s17, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s46, s16, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s47, s19, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s48, s18, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s49, s21, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s50, s20, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s51, s23, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s52, s30, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s53, s31, 31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s52
+; GFX6-NOHSA-NEXT: s_ashr_i32 s52, s28, 31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s53
+; GFX6-NOHSA-NEXT: s_ashr_i32 s53, s29, 31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s52
+; GFX6-NOHSA-NEXT: s_ashr_i32 s52, s26, 31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s53
+; GFX6-NOHSA-NEXT: s_ashr_i32 s53, s27, 31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v9, s52
+; GFX6-NOHSA-NEXT: s_ashr_i32 s52, s22, 31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s53
+; GFX6-NOHSA-NEXT: s_ashr_i32 s53, s25, 31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s28
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s29
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s26
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s27
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s24
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v14, s25
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v16, s22
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v18, s23
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:240
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s21
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[36:39], 0 offset:224
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s18
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s19
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[36:39], 0 offset:208
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s17
+; GFX6-NOHSA-NEXT: s_ashr_i32 s16, s24, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s17, s9, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s18, s8, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s19, s11, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s20, s10, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s21, s13, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s22, s12, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s23, s15, 31
+; GFX6-NOHSA-NEXT: s_ashr_i32 s24, s14, 31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v13, s16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v15, s53
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[36:39], 0 offset:192
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v14, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v17, s52
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v19, s51
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[36:39], 0 offset:176
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v16, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v18, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s50
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s49
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:160
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s48
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s47
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[36:39], 0 offset:144
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v9, s46
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s45
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[36:39], 0 offset:128
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v13, s24
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v15, s23
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[36:39], 0 offset:112
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v14, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v17, s22
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v19, s21
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[36:39], 0 offset:96
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v16, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v18, s3
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s20
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s19
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:80
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s18
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s17
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[36:39], 0 offset:64
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v9, s44
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s43
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[36:39], 0 offset:48
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v13, s42
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v15, s41
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[36:39], 0 offset:32
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v17, s40
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v19, s35
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[16:19], off, s[36:39], 0 offset:16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s34
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s33
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v32i32_to_v32i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x10
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s20, s1, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s21, s0, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s22, s3, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s23, s2, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s24, s5, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s25, s4, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s26, s7, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s27, s6, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s28, s9, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s29, s8, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s30, s11, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s31, s10, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s33, s13, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s34, s12, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s35, s15, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s36, s14, 31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v28, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v30, s1
+; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s35
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s33
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s37, s1, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s38, s0, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s39, s3, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s40, s2, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s41, s5, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s42, s4, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s43, s7, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s44, s6, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s45, s9, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s46, s8, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s47, s11, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s48, s10, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s49, s13, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s50, s12, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s51, s15, 31
+; GFX7-HSA-NEXT: s_ashr_i32 s52, s14, 31
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0xf0
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v32, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v31, s18
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0xe0
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v34, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v33, s18
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0xd0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[31:32], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0xc0
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s19
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0xb0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s28
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[33:34], v[4:7]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[2:3], v[12:15]
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0xa0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0x90
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[20:23]
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT: s_add_u32 s18, s16, 0x80
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[24:27]
+; GFX7-HSA-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v29, s21
+; GFX7-HSA-NEXT: v_mov_b32_e32 v31, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[28:31]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX7-HSA-NEXT: s_add_u32 s14, s16, 0x70
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX7-HSA-NEXT: s_addc_u32 s15, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s52
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s51
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s15
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX7-HSA-NEXT: s_add_u32 s12, s16, 0x60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX7-HSA-NEXT: s_addc_u32 s13, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s49
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX7-HSA-NEXT: s_add_u32 s10, s16, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX7-HSA-NEXT: s_addc_u32 s11, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s47
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s16, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX7-HSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s46
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s45
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s44
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s43
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s42
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s41
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s16, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s40
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s39
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s37
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v32i32_to_v32i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[36:39], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GFX8-NOHSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x40
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_ashr_i32 s33, s1, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s34, s0, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s35, s3, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s38, s2, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s39, s5, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s40, s4, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s41, s7, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s42, s6, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s43, s9, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s44, s8, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s45, s11, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s46, s10, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s47, s13, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s48, s12, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s49, s15, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s50, s14, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s51, s17, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s52, s16, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s53, s19, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s54, s18, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s55, s21, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s56, s20, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s57, s23, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s58, s22, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s59, s25, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s60, s24, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s61, s27, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s62, s26, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s63, s29, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s64, s28, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s65, s31, 31
+; GFX8-NOHSA-NEXT: s_ashr_i32 s66, s30, 31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX8-NOHSA-NEXT: s_add_u32 s30, s36, 0xf0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s31
+; GFX8-NOHSA-NEXT: s_addc_u32 s31, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s30
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s66
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s65
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s31
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX8-NOHSA-NEXT: s_add_u32 s28, s36, 0xe0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s29
+; GFX8-NOHSA-NEXT: s_addc_u32 s29, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s28
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s64
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s63
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s29
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s26
+; GFX8-NOHSA-NEXT: s_add_u32 s26, s36, 0xd0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s27
+; GFX8-NOHSA-NEXT: s_addc_u32 s27, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s62
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s61
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX8-NOHSA-NEXT: s_add_u32 s24, s36, 0xc0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s25
+; GFX8-NOHSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s60
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s59
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s25
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s22
+; GFX8-NOHSA-NEXT: s_add_u32 s22, s36, 0xb0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s23
+; GFX8-NOHSA-NEXT: s_addc_u32 s23, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s22
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s58
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s57
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s23
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX8-NOHSA-NEXT: s_add_u32 s20, s36, 0xa0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s21
+; GFX8-NOHSA-NEXT: s_addc_u32 s21, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s20
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s56
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s55
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s21
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX8-NOHSA-NEXT: s_add_u32 s18, s36, 0x90
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX8-NOHSA-NEXT: s_addc_u32 s19, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s54
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s53
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s19
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX8-NOHSA-NEXT: s_add_u32 s16, s36, 0x80
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s17
+; GFX8-NOHSA-NEXT: s_addc_u32 s17, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s52
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s51
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX8-NOHSA-NEXT: s_add_u32 s14, s36, 0x70
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX8-NOHSA-NEXT: s_addc_u32 s15, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s50
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s49
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s15
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NOHSA-NEXT: s_add_u32 s12, s36, 0x60
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX8-NOHSA-NEXT: s_addc_u32 s13, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s47
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s36, 0x50
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s46
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s45
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s36, 64
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s44
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s43
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s36, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s42
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s41
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s36, 32
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s40
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s39
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s36, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s38
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s35
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s36
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s34
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s33
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s37
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v32i32_to_v32i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 32, @36, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 7 @20
+; EG-NEXT: ALU 96, @69, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T32.XYZW, T12.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T23.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T31.XYZW, T21.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T20.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T30.XYZW, T19.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T10.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T29.XYZW, T9.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T8.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T28.XYZW, T7.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T18.XYZW, T6.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T27.XYZW, T5.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T4.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T26.XYZW, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T25.XYZW, T2.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T24.XYZW, T1.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T22.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 20:
+; EG-NEXT: VTX_READ_128 T12.XYZW, T11.X, 112, #1
+; EG-NEXT: VTX_READ_128 T13.XYZW, T11.X, 96, #1
+; EG-NEXT: VTX_READ_128 T14.XYZW, T11.X, 80, #1
+; EG-NEXT: VTX_READ_128 T15.XYZW, T11.X, 64, #1
+; EG-NEXT: VTX_READ_128 T16.XYZW, T11.X, 48, #1
+; EG-NEXT: VTX_READ_128 T17.XYZW, T11.X, 32, #1
+; EG-NEXT: VTX_READ_128 T18.XYZW, T11.X, 16, #1
+; EG-NEXT: VTX_READ_128 T11.XYZW, T11.X, 0, #1
+; EG-NEXT: ALU clause starting at 36:
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T1.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T2.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T3.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T4.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T5.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: LSHR T6.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43)
+; EG-NEXT: LSHR T7.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 128(1.793662e-43)
+; EG-NEXT: LSHR T8.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 144(2.017870e-43)
+; EG-NEXT: LSHR T9.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 160(2.242078e-43)
+; EG-NEXT: LSHR T10.X, PV.W, literal.x,
+; EG-NEXT: MOV * T11.X, KC0[2].Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 69:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 176(2.466285e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T19.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 192(2.690493e-43)
+; EG-NEXT: LSHR T20.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 208(2.914701e-43)
+; EG-NEXT: LSHR T21.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: ASHR * T22.W, T11.Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 224(3.138909e-43)
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T23.X, PV.W, literal.x,
+; EG-NEXT: ASHR T22.Y, T11.X, literal.y,
+; EG-NEXT: ASHR T24.W, T11.W, literal.y,
+; EG-NEXT: MOV * T22.X, T11.X,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
+; EG-NEXT: ASHR T24.Y, T11.Z, literal.x,
+; EG-NEXT: ASHR * T25.W, T18.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T24.X, T11.Z,
+; EG-NEXT: ASHR T25.Y, T18.X, literal.x,
+; EG-NEXT: MOV T22.Z, T11.Y,
+; EG-NEXT: ASHR T26.W, T18.W, literal.x,
+; EG-NEXT: MOV * T25.X, T18.X,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR T26.Y, T18.Z, literal.x,
+; EG-NEXT: MOV T24.Z, T11.W,
+; EG-NEXT: ASHR * T11.W, T17.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T26.X, T18.Z,
+; EG-NEXT: ASHR T11.Y, T17.X, literal.x,
+; EG-NEXT: MOV T25.Z, T18.Y,
+; EG-NEXT: ASHR T27.W, T17.W, literal.x,
+; EG-NEXT: MOV * T11.X, T17.X,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR T27.Y, T17.Z, literal.x,
+; EG-NEXT: MOV T26.Z, T18.W,
+; EG-NEXT: ASHR * T18.W, T16.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T27.X, T17.Z,
+; EG-NEXT: ASHR T18.Y, T16.X, literal.x,
+; EG-NEXT: MOV T11.Z, T17.Y,
+; EG-NEXT: ASHR T28.W, T16.W, literal.x,
+; EG-NEXT: MOV * T18.X, T16.X,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR T28.Y, T16.Z, literal.x,
+; EG-NEXT: MOV T27.Z, T17.W,
+; EG-NEXT: ASHR * T17.W, T15.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T28.X, T16.Z,
+; EG-NEXT: ASHR T17.Y, T15.X, literal.x,
+; EG-NEXT: MOV T18.Z, T16.Y,
+; EG-NEXT: ASHR T29.W, T15.W, literal.x,
+; EG-NEXT: MOV * T17.X, T15.X,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR T29.Y, T15.Z, literal.x,
+; EG-NEXT: MOV T28.Z, T16.W,
+; EG-NEXT: ASHR * T16.W, T14.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T29.X, T15.Z,
+; EG-NEXT: ASHR T16.Y, T14.X, literal.x,
+; EG-NEXT: MOV T17.Z, T15.Y,
+; EG-NEXT: ASHR T30.W, T14.W, literal.x,
+; EG-NEXT: MOV * T16.X, T14.X,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR T30.Y, T14.Z, literal.x,
+; EG-NEXT: MOV T29.Z, T15.W,
+; EG-NEXT: ASHR * T15.W, T13.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T30.X, T14.Z,
+; EG-NEXT: ASHR T15.Y, T13.X, literal.x,
+; EG-NEXT: MOV T16.Z, T14.Y,
+; EG-NEXT: ASHR T31.W, T13.W, literal.x,
+; EG-NEXT: MOV * T15.X, T13.X,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR T31.Y, T13.Z, literal.x,
+; EG-NEXT: MOV T30.Z, T14.W,
+; EG-NEXT: ASHR * T14.W, T12.Y, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T31.X, T13.Z,
+; EG-NEXT: ASHR T14.Y, T12.X, literal.x,
+; EG-NEXT: MOV T15.Z, T13.Y,
+; EG-NEXT: ASHR T32.W, T12.W, literal.x,
+; EG-NEXT: MOV * T14.X, T12.X,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR T32.Y, T12.Z, literal.x,
+; EG-NEXT: MOV * T31.Z, T13.W,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: MOV T32.X, T12.Z,
+; EG-NEXT: MOV T14.Z, T12.Y,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 240(3.363116e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T12.X, PV.W, literal.x,
+; EG-NEXT: MOV * T32.Z, T12.W,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_sextload_v32i32_to_v32i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[36:39], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x40
+; GFX9-HSA-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_ashr_i32 s65, s31, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s66, s30, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s63, s29, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s64, s28, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s30
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s66
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s65
+; GFX9-HSA-NEXT: s_ashr_i32 s61, s27, 31
+; GFX9-HSA-NEXT: s_ashr_i32 s62, s26, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:240
+; GFX9-HSA-NEXT: s_ashr_i32 s59, s25, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s28
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s64
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s29
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s63
+; GFX9-HSA-NEXT: s_ashr_i32 s60, s24, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:224
+; GFX9-HSA-NEXT: s_ashr_i32 s57, s23, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s26
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s62
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s27
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s61
+; GFX9-HSA-NEXT: s_ashr_i32 s58, s22, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:208
+; GFX9-HSA-NEXT: s_ashr_i32 s55, s21, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s24
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s60
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s25
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s59
+; GFX9-HSA-NEXT: s_ashr_i32 s56, s20, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:192
+; GFX9-HSA-NEXT: s_ashr_i32 s53, s19, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s22
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s58
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s23
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s57
+; GFX9-HSA-NEXT: s_ashr_i32 s54, s18, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:176
+; GFX9-HSA-NEXT: s_ashr_i32 s51, s17, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s20
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s56
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s21
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s55
+; GFX9-HSA-NEXT: s_ashr_i32 s52, s16, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:160
+; GFX9-HSA-NEXT: s_ashr_i32 s49, s15, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s18
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s54
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s19
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s53
+; GFX9-HSA-NEXT: s_ashr_i32 s50, s14, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:144
+; GFX9-HSA-NEXT: s_ashr_i32 s47, s13, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s16
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s52
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s17
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s51
+; GFX9-HSA-NEXT: s_ashr_i32 s48, s12, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:128
+; GFX9-HSA-NEXT: s_ashr_i32 s45, s11, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s14
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s50
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s49
+; GFX9-HSA-NEXT: s_ashr_i32 s46, s10, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:112
+; GFX9-HSA-NEXT: s_ashr_i32 s43, s9, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s12
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s48
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s13
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s47
+; GFX9-HSA-NEXT: s_ashr_i32 s44, s8, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:96
+; GFX9-HSA-NEXT: s_ashr_i32 s41, s7, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s10
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s46
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s45
+; GFX9-HSA-NEXT: s_ashr_i32 s42, s6, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:80
+; GFX9-HSA-NEXT: s_ashr_i32 s39, s5, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s8
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s44
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s9
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s43
+; GFX9-HSA-NEXT: s_ashr_i32 s40, s4, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:64
+; GFX9-HSA-NEXT: s_ashr_i32 s35, s3, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s42
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s41
+; GFX9-HSA-NEXT: s_ashr_i32 s38, s2, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:48
+; GFX9-HSA-NEXT: s_ashr_i32 s33, s1, 31
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s40
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s39
+; GFX9-HSA-NEXT: s_ashr_i32 s34, s0, 31
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:32
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s38
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s35
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37] offset:16
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s34
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s33
+; GFX9-HSA-NEXT: global_store_dwordx4 v0, v[1:4], s[36:37]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <32 x i32>, ptr addrspace(4) %in
%ext = sext <32 x i32> %ld to <32 x i64>
store <32 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v32i32_to_v32i64:
-; GCN: s_load_dwordx16
-; GCN: s_load_dwordx16
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @constant_zextload_v32i32_to_v32i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v32i32_to_v32i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx16 s[16:31], s[2:3], 0x10
+; GFX6-NOHSA-NEXT: s_mov_b32 s39, 0xf000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s38, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NOHSA-NEXT: s_mov_b32 s36, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s37, s1
+; GFX6-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s31
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:240
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s29
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:224
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s26
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s27
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:208
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s25
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:192
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s22
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s23
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:176
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s21
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:160
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:144
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s17
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:128
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:112
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:96
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:80
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:64
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v32i32_to_v32i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[36:39], s[4:5], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x10
+; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GFX7-HSA-NEXT: s_add_u32 s34, s36, 0xf0
+; GFX7-HSA-NEXT: s_addc_u32 s35, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s35
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s31
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX7-HSA-NEXT: s_add_u32 s28, s36, 0xe0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s29
+; GFX7-HSA-NEXT: s_addc_u32 s29, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s29
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s26
+; GFX7-HSA-NEXT: s_add_u32 s26, s36, 0xd0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s27
+; GFX7-HSA-NEXT: s_addc_u32 s27, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s27
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0xc0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s25
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s25
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s22
+; GFX7-HSA-NEXT: s_add_u32 s22, s36, 0xb0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s23
+; GFX7-HSA-NEXT: s_addc_u32 s23, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s23
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX7-HSA-NEXT: s_add_u32 s20, s36, 0xa0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s21
+; GFX7-HSA-NEXT: s_addc_u32 s21, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s21
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX7-HSA-NEXT: s_add_u32 s18, s36, 0x90
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX7-HSA-NEXT: s_addc_u32 s19, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s19
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX7-HSA-NEXT: s_add_u32 s16, s36, 0x80
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s17
+; GFX7-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX7-HSA-NEXT: s_add_u32 s14, s36, 0x70
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX7-HSA-NEXT: s_addc_u32 s15, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s15
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX7-HSA-NEXT: s_add_u32 s12, s36, 0x60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX7-HSA-NEXT: s_addc_u32 s13, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX7-HSA-NEXT: s_add_u32 s10, s36, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX7-HSA-NEXT: s_addc_u32 s11, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s36, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX7-HSA-NEXT: s_addc_u32 s9, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s36, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: s_addc_u32 s7, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s36, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: s_addc_u32 s5, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s36, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s37
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v32i32_to_v32i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[36:39], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x40
+; GFX8-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GFX8-NOHSA-NEXT: s_add_u32 s34, s36, 0xf0
+; GFX8-NOHSA-NEXT: s_addc_u32 s35, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s34
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s35
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s31
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX8-NOHSA-NEXT: s_add_u32 s28, s36, 0xe0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s29
+; GFX8-NOHSA-NEXT: s_addc_u32 s29, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s28
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s29
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s26
+; GFX8-NOHSA-NEXT: s_add_u32 s26, s36, 0xd0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s27
+; GFX8-NOHSA-NEXT: s_addc_u32 s27, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s26
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s27
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX8-NOHSA-NEXT: s_add_u32 s24, s36, 0xc0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s25
+; GFX8-NOHSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s25
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s22
+; GFX8-NOHSA-NEXT: s_add_u32 s22, s36, 0xb0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s23
+; GFX8-NOHSA-NEXT: s_addc_u32 s23, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s22
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s23
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX8-NOHSA-NEXT: s_add_u32 s20, s36, 0xa0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s21
+; GFX8-NOHSA-NEXT: s_addc_u32 s21, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s20
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s21
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX8-NOHSA-NEXT: s_add_u32 s18, s36, 0x90
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX8-NOHSA-NEXT: s_addc_u32 s19, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s19
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX8-NOHSA-NEXT: s_add_u32 s16, s36, 0x80
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s17
+; GFX8-NOHSA-NEXT: s_addc_u32 s17, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX8-NOHSA-NEXT: s_add_u32 s14, s36, 0x70
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX8-NOHSA-NEXT: s_addc_u32 s15, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s15
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NOHSA-NEXT: s_add_u32 s12, s36, 0x60
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX8-NOHSA-NEXT: s_addc_u32 s13, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s36, 0x50
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s36, 64
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s36, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s36, 32
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s36, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s36
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s37
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v32i32_to_v32i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @38, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 2 @22
+; EG-NEXT: ALU 10, @39, KC0[], KC1[]
+; EG-NEXT: TEX 4 @28
+; EG-NEXT: ALU 99, @50, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T31.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T30.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T29.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T28.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T27.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T26.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T25.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T24.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T13.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T12.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T18.XYZW, T11.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T10.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T21.XYZW, T2.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T22.XYZW, T1.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T23.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 22:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 112, #1
+; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 80, #1
+; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 96, #1
+; EG-NEXT: Fetch clause starting at 28:
+; EG-NEXT: VTX_READ_128 T10.XYZW, T0.X, 0, #1
+; EG-NEXT: VTX_READ_128 T11.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T12.XYZW, T0.X, 32, #1
+; EG-NEXT: VTX_READ_128 T13.XYZW, T0.X, 48, #1
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 64, #1
+; EG-NEXT: ALU clause starting at 38:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 39:
+; EG-NEXT: MOV T4.X, T1.Z,
+; EG-NEXT: MOV T4.Y, 0.0,
+; EG-NEXT: MOV * T5.X, T1.X,
+; EG-NEXT: MOV * T5.Y, 0.0,
+; EG-NEXT: MOV T6.X, T3.Z,
+; EG-NEXT: MOV T6.Y, 0.0,
+; EG-NEXT: MOV * T7.X, T3.X,
+; EG-NEXT: MOV * T7.Y, 0.0,
+; EG-NEXT: MOV T8.X, T2.Z,
+; EG-NEXT: MOV T8.Y, 0.0,
+; EG-NEXT: MOV * T9.X, T2.X,
+; EG-NEXT: ALU clause starting at 50:
+; EG-NEXT: MOV * T9.Y, 0.0,
+; EG-NEXT: MOV T14.X, T0.Z,
+; EG-NEXT: MOV T14.Y, 0.0,
+; EG-NEXT: MOV * T15.X, T0.X,
+; EG-NEXT: MOV * T15.Y, 0.0,
+; EG-NEXT: MOV T16.X, T13.Z,
+; EG-NEXT: MOV T16.Y, 0.0,
+; EG-NEXT: MOV * T17.X, T13.X,
+; EG-NEXT: MOV * T17.Y, 0.0,
+; EG-NEXT: MOV T18.X, T12.Z,
+; EG-NEXT: MOV T18.Y, 0.0,
+; EG-NEXT: MOV * T19.X, T12.X,
+; EG-NEXT: MOV * T19.Y, 0.0,
+; EG-NEXT: MOV T20.X, T11.Z,
+; EG-NEXT: MOV T20.Y, 0.0,
+; EG-NEXT: MOV * T21.X, T11.X,
+; EG-NEXT: MOV * T21.Y, 0.0,
+; EG-NEXT: MOV T22.X, T10.Z,
+; EG-NEXT: MOV T22.Y, 0.0,
+; EG-NEXT: MOV * T23.X, T10.X,
+; EG-NEXT: MOV T23.Y, 0.0,
+; EG-NEXT: MOV T4.Z, T1.W,
+; EG-NEXT: MOV T4.W, 0.0,
+; EG-NEXT: MOV * T5.Z, T1.Y,
+; EG-NEXT: MOV * T5.W, 0.0,
+; EG-NEXT: MOV T6.Z, T3.W,
+; EG-NEXT: MOV T6.W, 0.0,
+; EG-NEXT: MOV * T7.Z, T3.Y,
+; EG-NEXT: MOV * T7.W, 0.0,
+; EG-NEXT: MOV T8.Z, T2.W,
+; EG-NEXT: MOV T8.W, 0.0,
+; EG-NEXT: MOV * T9.Z, T2.Y,
+; EG-NEXT: MOV * T9.W, 0.0,
+; EG-NEXT: MOV T14.Z, T0.W,
+; EG-NEXT: MOV T14.W, 0.0,
+; EG-NEXT: MOV * T15.Z, T0.Y,
+; EG-NEXT: MOV * T15.W, 0.0,
+; EG-NEXT: MOV T16.Z, T13.W,
+; EG-NEXT: MOV T16.W, 0.0,
+; EG-NEXT: MOV * T17.Z, T13.Y,
+; EG-NEXT: MOV * T17.W, 0.0,
+; EG-NEXT: MOV T18.Z, T12.W,
+; EG-NEXT: MOV T18.W, 0.0,
+; EG-NEXT: MOV * T19.Z, T12.Y,
+; EG-NEXT: MOV * T19.W, 0.0,
+; EG-NEXT: MOV T20.Z, T11.W,
+; EG-NEXT: MOV T20.W, 0.0,
+; EG-NEXT: MOV * T21.Z, T11.Y,
+; EG-NEXT: MOV * T21.W, 0.0,
+; EG-NEXT: MOV T22.Z, T10.W,
+; EG-NEXT: MOV T22.W, 0.0,
+; EG-NEXT: MOV * T23.Z, T10.Y,
+; EG-NEXT: MOV * T23.W, 0.0,
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T1.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T2.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T3.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T10.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T11.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: LSHR T12.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43)
+; EG-NEXT: LSHR T13.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 128(1.793662e-43)
+; EG-NEXT: LSHR T24.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 144(2.017870e-43)
+; EG-NEXT: LSHR T25.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 160(2.242078e-43)
+; EG-NEXT: LSHR T26.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 176(2.466285e-43)
+; EG-NEXT: LSHR T27.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 192(2.690493e-43)
+; EG-NEXT: LSHR T28.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 208(2.914701e-43)
+; EG-NEXT: LSHR T29.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 224(3.138909e-43)
+; EG-NEXT: LSHR T30.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 240(3.363116e-43)
+; EG-NEXT: LSHR * T31.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_zextload_v32i32_to_v32i64:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[36:39], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x40
+; GFX9-HSA-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s31
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:240
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s29
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:224
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s26
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s27
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:208
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s25
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:192
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s22
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s23
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:176
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s21
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:160
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:144
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s17
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:128
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:112
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:96
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:80
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:64
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:48
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:32
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37] offset:16
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX9-HSA-NEXT: global_store_dwordx4 v1, v[0:3], s[36:37]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <32 x i32>, ptr addrspace(4) %in
%ext = zext <32 x i32> %ld to <32 x i64>
store <32 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v32i32:
-; GCN: s_load_dwordx16
-; GCN: s_load_dwordx16
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-; GCN-NOHSA-DAG: buffer_store_dwordx4
-
-; GCN-NOT: accvgpr
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
-; GCN-HSA-DAG: {{flat|global}}_store_dwordx4
define amdgpu_kernel void @constant_load_v32i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v32i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx16 s[16:31], s[2:3], 0x10
+; GFX6-NOHSA-NEXT: s_mov_b32 s39, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s38, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s36, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s37, s1
+; GFX6-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s30
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s31
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:112
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s26
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s27
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:96
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s23
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:80
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s19
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:64
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v32i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[36:39], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x10
+; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GFX7-HSA-NEXT: s_add_u32 s34, s36, 0x70
+; GFX7-HSA-NEXT: s_addc_u32 s35, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s35
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s24
+; GFX7-HSA-NEXT: s_add_u32 s24, s36, 0x60
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s25
+; GFX7-HSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX7-HSA-NEXT: s_add_u32 s20, s36, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX7-HSA-NEXT: s_addc_u32 s21, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s21
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX7-HSA-NEXT: s_add_u32 s16, s36, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX7-HSA-NEXT: s_addc_u32 s17, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX7-HSA-NEXT: s_add_u32 s12, s36, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: s_addc_u32 s13, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s36, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-HSA-NEXT: s_addc_u32 s9, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s36, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: s_addc_u32 s5, s37, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s37
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v32i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[36:39], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x40
+; GFX8-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GFX8-NOHSA-NEXT: s_add_u32 s34, s36, 0x70
+; GFX8-NOHSA-NEXT: s_addc_u32 s35, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s34
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s35
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s30
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s24
+; GFX8-NOHSA-NEXT: s_add_u32 s24, s36, 0x60
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s25
+; GFX8-NOHSA-NEXT: s_addc_u32 s25, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s26
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s27
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX8-NOHSA-NEXT: s_add_u32 s20, s36, 0x50
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX8-NOHSA-NEXT: s_addc_u32 s21, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s20
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s23
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s21
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX8-NOHSA-NEXT: s_add_u32 s16, s36, 64
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX8-NOHSA-NEXT: s_addc_u32 s17, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s19
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NOHSA-NEXT: s_add_u32 s12, s36, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX8-NOHSA-NEXT: s_addc_u32 s13, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s36, 32
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s36, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s37, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s36
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s37
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v32i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 22, @28, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 7 @12
+; EG-NEXT: ALU 1, @51, KC0[], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T15.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T6.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XYZW, T5.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T4.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T3.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T2.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T1.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 12:
+; EG-NEXT: VTX_READ_128 T8.XYZW, T7.X, 112, #1
+; EG-NEXT: VTX_READ_128 T9.XYZW, T7.X, 96, #1
+; EG-NEXT: VTX_READ_128 T10.XYZW, T7.X, 80, #1
+; EG-NEXT: VTX_READ_128 T11.XYZW, T7.X, 64, #1
+; EG-NEXT: VTX_READ_128 T12.XYZW, T7.X, 48, #1
+; EG-NEXT: VTX_READ_128 T13.XYZW, T7.X, 32, #1
+; EG-NEXT: VTX_READ_128 T14.XYZW, T7.X, 16, #1
+; EG-NEXT: VTX_READ_128 T7.XYZW, T7.X, 0, #1
+; EG-NEXT: ALU clause starting at 28:
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T1.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T2.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T3.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T4.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T5.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: LSHR T6.X, PV.W, literal.x,
+; EG-NEXT: MOV * T7.X, KC0[2].Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 112(1.569454e-43), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 51:
+; EG-NEXT: LSHR * T15.X, T0.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+;
+; GFX9-HSA-LABEL: constant_load_v32i32:
+; GFX9-HSA: ; %bb.0:
+; GFX9-HSA-NEXT: s_load_dwordx4 s[36:39], s[4:5], 0x0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v8, 0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x40
+; GFX9-HSA-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GFX9-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s30
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s31
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[36:37] offset:112
+; GFX9-HSA-NEXT: v_mov_b32_e32 v4, s24
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s23
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[36:37] offset:80
+; GFX9-HSA-NEXT: v_mov_b32_e32 v5, s25
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s19
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[36:37] offset:64
+; GFX9-HSA-NEXT: v_mov_b32_e32 v6, s26
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[36:37] offset:48
+; GFX9-HSA-NEXT: v_mov_b32_e32 v7, s27
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[36:37] offset:32
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[4:7], s[36:37] offset:96
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[36:37] offset:16
+; GFX9-HSA-NEXT: s_nop 0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX9-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX9-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX9-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX9-HSA-NEXT: global_store_dwordx4 v8, v[0:3], s[36:37]
+; GFX9-HSA-NEXT: s_endpgm
%ld = load <32 x i32>, ptr addrspace(4) %in
store <32 x i32> %ld, ptr addrspace(1) %out
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i64.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
index 4f8dcdd7aa6d2..1a1e8c7f77fbc 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
@@ -1,81 +1,812 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,FUNC %s
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=EG,FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck --check-prefix=GFX6 %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck --check-prefix=GFX7 %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck --check-prefix=GFX8 %s
+; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=EG %s
-
-; FUNC-LABEL: {{^}}constant_load_i64:
-; GCN: s_load_dwordx2 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
-; EG: VTX_READ_64
define amdgpu_kernel void @constant_load_i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-LABEL: constant_load_i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX7-LABEL: constant_load_i64:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%ld = load i64, ptr addrspace(4) %in
store i64 %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v2i64:
-; GCN: s_load_dwordx4
-
-; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v2i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-LABEL: constant_load_v2i64:
+; GFX6: ; %bb.0: ; %entry
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX7-LABEL: constant_load_v2i64:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_v2i64:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v2i64:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%ld = load <2 x i64>, ptr addrspace(4) %in
store <2 x i64> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v3i64:
-; GCN-DAG: s_load_dwordx4 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
-; GCN-DAG: s_load_dwordx2 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x{{[0-9]+}}{{$}}
-
-; EG-DAG: VTX_READ_128
-; EG-DAG: VTX_READ_128
define amdgpu_kernel void @constant_load_v3i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-LABEL: constant_load_v3i64:
+; GFX6: ; %bb.0: ; %entry
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dwordx2 s[8:9], s[2:3], 0x4
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NEXT: v_mov_b32_e32 v1, s9
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 offset:16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX7-LABEL: constant_load_v3i64:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_load_dwordx2 s[8:9], s[2:3], 0x4
+; GFX7-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-NEXT: s_add_u32 s2, s0, 16
+; GFX7-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s3
+; GFX7-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v5, s8
+; GFX7-NEXT: v_mov_b32_e32 v6, s9
+; GFX7-NEXT: flat_store_dwordx2 v[3:4], v[5:6]
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_v3i64:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx2 s[8:9], s[2:3], 0x10
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s3
+; GFX8-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v5, s8
+; GFX8-NEXT: v_mov_b32_e32 v6, s9
+; GFX8-NEXT: flat_store_dwordx2 v[3:4], v[5:6]
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v3i64:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 1, @13, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
+; EG-NEXT: TEX 0 @10
+; EG-NEXT: ALU 3, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 0, #1
+; EG-NEXT: Fetch clause starting at 10:
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 16, #1
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 13:
+; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 15:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T1.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%ld = load <3 x i64>, ptr addrspace(4) %in
store <3 x i64> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v4i64
-; GCN: s_load_dwordx8
-
-; EG: VTX_READ_128
-; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v4i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-LABEL: constant_load_v4i64:
+; GFX6: ; %bb.0: ; %entry
+; GFX6-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NEXT: s_mov_b32 s10, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX7-LABEL: constant_load_v4i64:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX7-NEXT: s_add_u32 s10, s8, 16
+; GFX7-NEXT: s_addc_u32 s11, s9, 0
+; GFX7-NEXT: v_mov_b32_e32 v6, s10
+; GFX7-NEXT: v_mov_b32_e32 v7, s11
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX7-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-NEXT: v_mov_b32_e32 v6, s2
+; GFX7-NEXT: v_mov_b32_e32 v7, s3
+; GFX7-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_v4i64:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NEXT: s_add_u32 s10, s8, 16
+; GFX8-NEXT: s_addc_u32 s11, s9, 0
+; GFX8-NEXT: v_mov_b32_e32 v6, s10
+; GFX8-NEXT: v_mov_b32_e32 v7, s11
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NEXT: v_mov_b32_e32 v7, s3
+; GFX8-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v4i64:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 3, @13, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
+; EG-NEXT: TEX 0 @10
+; EG-NEXT: ALU 1, @17, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: Fetch clause starting at 10:
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 13:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 17:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%ld = load <4 x i64>, ptr addrspace(4) %in
store <4 x i64> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v8i64:
-; GCN: s_load_dwordx16
-
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v8i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-LABEL: constant_load_v8i64:
+; GFX6: ; %bb.0: ; %entry
+; GFX6-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX6-NEXT: s_mov_b32 s19, 0xf000
+; GFX6-NEXT: s_mov_b32 s18, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NEXT: v_mov_b32_e32 v3, s15
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:48
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NEXT: v_mov_b32_e32 v1, s9
+; GFX6-NEXT: v_mov_b32_e32 v2, s10
+; GFX6-NEXT: v_mov_b32_e32 v3, s11
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:32
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0 offset:16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[16:19], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX7-LABEL: constant_load_v8i64:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x0
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX7-NEXT: s_add_u32 s18, s16, 48
+; GFX7-NEXT: s_addc_u32 s19, s17, 0
+; GFX7-NEXT: v_mov_b32_e32 v6, s18
+; GFX7-NEXT: v_mov_b32_e32 v7, s19
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v0, s12
+; GFX7-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-NEXT: v_mov_b32_e32 v2, s14
+; GFX7-NEXT: v_mov_b32_e32 v3, s15
+; GFX7-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-NEXT: s_add_u32 s8, s16, 32
+; GFX7-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX7-NEXT: s_addc_u32 s9, s17, 0
+; GFX7-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-NEXT: v_mov_b32_e32 v6, s10
+; GFX7-NEXT: v_mov_b32_e32 v7, s11
+; GFX7-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-NEXT: s_add_u32 s4, s16, 16
+; GFX7-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-NEXT: v_mov_b32_e32 v4, s16
+; GFX7-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-NEXT: v_mov_b32_e32 v5, s17
+; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_v8i64:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX8-NEXT: s_add_u32 s18, s16, 48
+; GFX8-NEXT: s_addc_u32 s19, s17, 0
+; GFX8-NEXT: v_mov_b32_e32 v6, s18
+; GFX8-NEXT: v_mov_b32_e32 v7, s19
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NEXT: v_mov_b32_e32 v1, s13
+; GFX8-NEXT: v_mov_b32_e32 v2, s14
+; GFX8-NEXT: v_mov_b32_e32 v3, s15
+; GFX8-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NEXT: s_add_u32 s8, s16, 32
+; GFX8-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX8-NEXT: s_addc_u32 s9, s17, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NEXT: v_mov_b32_e32 v6, s10
+; GFX8-NEXT: v_mov_b32_e32 v7, s11
+; GFX8-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: s_add_u32 s4, s16, 16
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v4, s16
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s17
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v8i64:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @22, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @14
+; EG-NEXT: ALU 3, @23, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
+; EG-NEXT: TEX 0 @16
+; EG-NEXT: ALU 3, @27, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
+; EG-NEXT: TEX 0 @18
+; EG-NEXT: ALU 3, @31, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
+; EG-NEXT: TEX 0 @20
+; EG-NEXT: ALU 1, @35, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 14:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 48, #1
+; EG-NEXT: Fetch clause starting at 16:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 32, #1
+; EG-NEXT: Fetch clause starting at 18:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: Fetch clause starting at 20:
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 22:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 23:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 27:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 31:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 35:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%ld = load <8 x i64>, ptr addrspace(4) %in
store <8 x i64> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v16i64:
-; GCN: s_load_dwordx16
-; GCN: s_load_dwordx16
-
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
-; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v16i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-LABEL: constant_load_v16i64:
+; GFX6: ; %bb.0: ; %entry
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_load_dwordx16 s[16:31], s[2:3], 0x10
+; GFX6-NEXT: s_mov_b32 s39, 0xf000
+; GFX6-NEXT: s_mov_b32 s38, -1
+; GFX6-NEXT: s_mov_b32 s36, s0
+; GFX6-NEXT: s_mov_b32 s37, s1
+; GFX6-NEXT: s_load_dwordx16 s[0:15], s[2:3], 0x0
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s28
+; GFX6-NEXT: v_mov_b32_e32 v1, s29
+; GFX6-NEXT: v_mov_b32_e32 v2, s30
+; GFX6-NEXT: v_mov_b32_e32 v3, s31
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:112
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s24
+; GFX6-NEXT: v_mov_b32_e32 v1, s25
+; GFX6-NEXT: v_mov_b32_e32 v2, s26
+; GFX6-NEXT: v_mov_b32_e32 v3, s27
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:96
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s20
+; GFX6-NEXT: v_mov_b32_e32 v1, s21
+; GFX6-NEXT: v_mov_b32_e32 v2, s22
+; GFX6-NEXT: v_mov_b32_e32 v3, s23
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:80
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s16
+; GFX6-NEXT: v_mov_b32_e32 v1, s17
+; GFX6-NEXT: v_mov_b32_e32 v2, s18
+; GFX6-NEXT: v_mov_b32_e32 v3, s19
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:64
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NEXT: v_mov_b32_e32 v3, s15
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:48
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NEXT: v_mov_b32_e32 v1, s9
+; GFX6-NEXT: v_mov_b32_e32 v2, s10
+; GFX6-NEXT: v_mov_b32_e32 v3, s11
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:32
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0 offset:16
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[36:39], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX7-LABEL: constant_load_v16i64:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_load_dwordx4 s[36:39], s[4:5], 0x0
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x10
+; GFX7-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GFX7-NEXT: s_add_u32 s34, s36, 0x70
+; GFX7-NEXT: s_addc_u32 s35, s37, 0
+; GFX7-NEXT: v_mov_b32_e32 v5, s34
+; GFX7-NEXT: v_mov_b32_e32 v6, s35
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v0, s28
+; GFX7-NEXT: v_mov_b32_e32 v1, s29
+; GFX7-NEXT: v_mov_b32_e32 v2, s30
+; GFX7-NEXT: v_mov_b32_e32 v3, s31
+; GFX7-NEXT: v_mov_b32_e32 v4, s24
+; GFX7-NEXT: s_add_u32 s24, s36, 0x60
+; GFX7-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
+; GFX7-NEXT: v_mov_b32_e32 v5, s25
+; GFX7-NEXT: s_addc_u32 s25, s37, 0
+; GFX7-NEXT: v_mov_b32_e32 v0, s24
+; GFX7-NEXT: v_mov_b32_e32 v6, s26
+; GFX7-NEXT: v_mov_b32_e32 v7, s27
+; GFX7-NEXT: v_mov_b32_e32 v1, s25
+; GFX7-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX7-NEXT: v_mov_b32_e32 v0, s20
+; GFX7-NEXT: s_add_u32 s20, s36, 0x50
+; GFX7-NEXT: v_mov_b32_e32 v1, s21
+; GFX7-NEXT: s_addc_u32 s21, s37, 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s20
+; GFX7-NEXT: v_mov_b32_e32 v2, s22
+; GFX7-NEXT: v_mov_b32_e32 v3, s23
+; GFX7-NEXT: v_mov_b32_e32 v5, s21
+; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-NEXT: s_nop 0
+; GFX7-NEXT: v_mov_b32_e32 v0, s16
+; GFX7-NEXT: s_add_u32 s16, s36, 64
+; GFX7-NEXT: v_mov_b32_e32 v1, s17
+; GFX7-NEXT: s_addc_u32 s17, s37, 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s16
+; GFX7-NEXT: v_mov_b32_e32 v2, s18
+; GFX7-NEXT: v_mov_b32_e32 v3, s19
+; GFX7-NEXT: v_mov_b32_e32 v5, s17
+; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-NEXT: s_nop 0
+; GFX7-NEXT: v_mov_b32_e32 v0, s12
+; GFX7-NEXT: s_add_u32 s12, s36, 48
+; GFX7-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-NEXT: s_addc_u32 s13, s37, 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-NEXT: v_mov_b32_e32 v2, s14
+; GFX7-NEXT: v_mov_b32_e32 v3, s15
+; GFX7-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-NEXT: s_nop 0
+; GFX7-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-NEXT: s_add_u32 s8, s36, 32
+; GFX7-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-NEXT: s_addc_u32 s9, s37, 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-NEXT: v_mov_b32_e32 v2, s10
+; GFX7-NEXT: v_mov_b32_e32 v3, s11
+; GFX7-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-NEXT: s_nop 0
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-NEXT: s_add_u32 s4, s36, 16
+; GFX7-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-NEXT: s_addc_u32 s5, s37, 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-NEXT: v_mov_b32_e32 v4, s36
+; GFX7-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-NEXT: v_mov_b32_e32 v5, s37
+; GFX7-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: constant_load_v16i64:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[36:39], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx16 s[16:31], s[38:39], 0x40
+; GFX8-NEXT: s_load_dwordx16 s[0:15], s[38:39], 0x0
+; GFX8-NEXT: s_add_u32 s34, s36, 0x70
+; GFX8-NEXT: s_addc_u32 s35, s37, 0
+; GFX8-NEXT: v_mov_b32_e32 v5, s34
+; GFX8-NEXT: v_mov_b32_e32 v6, s35
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s28
+; GFX8-NEXT: v_mov_b32_e32 v1, s29
+; GFX8-NEXT: v_mov_b32_e32 v2, s30
+; GFX8-NEXT: v_mov_b32_e32 v3, s31
+; GFX8-NEXT: v_mov_b32_e32 v4, s24
+; GFX8-NEXT: s_add_u32 s24, s36, 0x60
+; GFX8-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v5, s25
+; GFX8-NEXT: s_addc_u32 s25, s37, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s24
+; GFX8-NEXT: v_mov_b32_e32 v6, s26
+; GFX8-NEXT: v_mov_b32_e32 v7, s27
+; GFX8-NEXT: v_mov_b32_e32 v1, s25
+; GFX8-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NEXT: v_mov_b32_e32 v0, s20
+; GFX8-NEXT: s_add_u32 s20, s36, 0x50
+; GFX8-NEXT: v_mov_b32_e32 v1, s21
+; GFX8-NEXT: s_addc_u32 s21, s37, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s20
+; GFX8-NEXT: v_mov_b32_e32 v2, s22
+; GFX8-NEXT: v_mov_b32_e32 v3, s23
+; GFX8-NEXT: v_mov_b32_e32 v5, s21
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_nop 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s16
+; GFX8-NEXT: s_add_u32 s16, s36, 64
+; GFX8-NEXT: v_mov_b32_e32 v1, s17
+; GFX8-NEXT: s_addc_u32 s17, s37, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s16
+; GFX8-NEXT: v_mov_b32_e32 v2, s18
+; GFX8-NEXT: v_mov_b32_e32 v3, s19
+; GFX8-NEXT: v_mov_b32_e32 v5, s17
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_nop 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NEXT: s_add_u32 s12, s36, 48
+; GFX8-NEXT: v_mov_b32_e32 v1, s13
+; GFX8-NEXT: s_addc_u32 s13, s37, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s12
+; GFX8-NEXT: v_mov_b32_e32 v2, s14
+; GFX8-NEXT: v_mov_b32_e32 v3, s15
+; GFX8-NEXT: v_mov_b32_e32 v5, s13
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_nop 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NEXT: s_add_u32 s8, s36, 32
+; GFX8-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NEXT: s_addc_u32 s9, s37, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NEXT: v_mov_b32_e32 v2, s10
+; GFX8-NEXT: v_mov_b32_e32 v3, s11
+; GFX8-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_nop 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: s_add_u32 s4, s36, 16
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: s_addc_u32 s5, s37, 0
+; GFX8-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: v_mov_b32_e32 v4, s36
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NEXT: v_mov_b32_e32 v5, s37
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v16i64:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @42, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @26
+; EG-NEXT: ALU 3, @43, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
+; EG-NEXT: TEX 0 @28
+; EG-NEXT: ALU 3, @47, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
+; EG-NEXT: TEX 0 @30
+; EG-NEXT: ALU 3, @51, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
+; EG-NEXT: TEX 0 @32
+; EG-NEXT: ALU 3, @55, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
+; EG-NEXT: TEX 0 @34
+; EG-NEXT: ALU 3, @59, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
+; EG-NEXT: TEX 0 @36
+; EG-NEXT: ALU 3, @63, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
+; EG-NEXT: TEX 0 @38
+; EG-NEXT: ALU 3, @67, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
+; EG-NEXT: TEX 0 @40
+; EG-NEXT: ALU 1, @71, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 26:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 112, #1
+; EG-NEXT: Fetch clause starting at 28:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 96, #1
+; EG-NEXT: Fetch clause starting at 30:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 80, #1
+; EG-NEXT: Fetch clause starting at 32:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 64, #1
+; EG-NEXT: Fetch clause starting at 34:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 48, #1
+; EG-NEXT: Fetch clause starting at 36:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 32, #1
+; EG-NEXT: Fetch clause starting at 38:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: Fetch clause starting at 40:
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 42:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 43:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 112(1.569454e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 47:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 96(1.345247e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 51:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 80(1.121039e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 55:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 64(8.968310e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 59:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 63:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 67:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 71:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%ld = load <16 x i64>, ptr addrspace(4) %in
store <16 x i64> %ld, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
index 9c193a7d4a452..f47e77f933ced 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
@@ -1,176 +1,956 @@
-; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
-; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=EG -check-prefix=FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6-NOHSA %s
+; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GFX7-HSA %s
+; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8-NOHSA %s
+; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG %s
-
-; FUNC-LABEL: {{^}}constant_load_i8:
-; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}
-; GCN-HSA: flat_load_ubyte
-
-; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; TODO: NOT AND
define amdgpu_kernel void @constant_load_i8(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_i8:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: buffer_store_byte v0, off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_i8:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: flat_store_byte v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_i8:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: flat_store_byte v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_i8:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.X, literal.y,
+; EG-NEXT: 3(4.203895e-45), 255(3.573311e-43)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL T0.X, T1.W, PV.W,
+; EG-NEXT: LSHL * T0.W, literal.x, PV.W,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%ld = load i8, ptr addrspace(4) %in
store i8 %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v2i8:
-; GCN-NOHSA: buffer_load_ushort v
-; GCN-HSA: flat_load_ushort v
-
-; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v2i8(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v2i8:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: buffer_store_short v0, off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v2i8:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ushort v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: flat_store_short v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v2i8:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ushort v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: flat_store_short v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v2i8:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_16 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: AND_INT T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.X, literal.y,
+; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL T0.X, T1.W, PV.W,
+; EG-NEXT: LSHL * T0.W, literal.x, PV.W,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%ld = load <2 x i8>, ptr addrspace(4) %in
store <2 x i8> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v3i8:
-; GCN: s_load_dword s
-
-; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v3i8(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v3i8:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s5, s4, 16
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: buffer_store_byte v1, off, s[0:3], 0 offset:2
+; GFX6-NOHSA-NEXT: buffer_store_short v0, off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v3i8:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_add_u32 s0, s0, 2
+; GFX7-HSA-NEXT: s_addc_u32 s1, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_lshr_b32 s0, s2, 16
+; GFX7-HSA-NEXT: flat_store_short v[0:1], v4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: flat_store_byte v[2:3], v0
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v3i8:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s0, 2
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s2, 16
+; GFX8-NOHSA-NEXT: flat_store_short v[0:1], v4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: flat_store_byte v[2:3], v0
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v3i8:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 27, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T6.XW, T8.X
+; EG-NEXT: MEM_RAT MSKOR T5.XW, T7.X
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T5.X, T5.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T5.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV * T2.X, T5.X,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.W, literal.x,
+; EG-NEXT: MOV * T2.W, literal.y,
+; EG-NEXT: 3(4.203895e-45), 8(1.121039e-44)
+; EG-NEXT: BFE_UINT T2.W, T0.Y, literal.x, PS,
+; EG-NEXT: LSHL * T1.W, PV.W, literal.y,
+; EG-NEXT: 16(2.242078e-44), 3(4.203895e-45)
+; EG-NEXT: LSHL T6.X, PV.W, PS,
+; EG-NEXT: LSHL * T6.W, literal.x, PS,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: MOV T6.Y, 0.0,
+; EG-NEXT: AND_INT T1.W, KC0[2].Y, literal.x,
+; EG-NEXT: AND_INT * T2.W, T5.X, literal.y,
+; EG-NEXT: 3(4.203895e-45), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T1.W, PV.W, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL T5.X, T2.W, PV.W,
+; EG-NEXT: LSHL * T5.W, literal.x, PV.W,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: MOV T5.Y, 0.0,
+; EG-NEXT: MOV T6.Z, 0.0,
+; EG-NEXT: MOV * T5.Z, 0.0,
+; EG-NEXT: LSHR T7.X, KC0[2].Y, literal.x,
+; EG-NEXT: LSHR * T8.X, T0.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%ld = load <3 x i8>, ptr addrspace(4) %in
store <3 x i8> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v4i8:
-; GCN: s_load_dword s
-
-; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v4i8(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v4i8:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v4i8:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: flat_store_dword v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v4i8:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v4i8:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%ld = load <4 x i8>, ptr addrspace(4) %in
store <4 x i8> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v8i8:
-; GCN: s_load_dwordx2
-
-; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v8i8(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v8i8:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v8i8:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v8i8:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v8i8:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%ld = load <8 x i8>, ptr addrspace(4) %in
store <8 x i8> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_load_v16i8:
-; GCN: s_load_dwordx4
-
-; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v16i8(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_load_v16i8:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_load_v16i8:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_load_v16i8:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_load_v16i8:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%ld = load <16 x i8>, ptr addrspace(4) %in
store <16 x i8> %ld, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_i8_to_i32:
-; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}},
-; GCN-HSA: flat_load_ubyte
-
-; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_i8_to_i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_i8_to_i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_i8_to_i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: flat_store_dword v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_i8_to_i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_i8_to_i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%a = load i8, ptr addrspace(4) %in
%ext = zext i8 %a to i32
store i32 %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_i8_to_i32:
-; GCN-NOHSA: buffer_load_sbyte
-; GCN-HSA: flat_load_sbyte
-
-; EG: VTX_READ_8 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1
-; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
-; EG: 8
define amdgpu_kernel void @constant_sextload_i8_to_i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_i8_to_i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_sbyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_i8_to_i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_sbyte v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: flat_store_dword v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_i8_to_i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_sbyte v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_i8_to_i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)
%ld = load i8, ptr addrspace(4) %in
%ext = sext i8 %ld to i32
store i32 %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v1i8_to_v1i32:
-
-; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v1i8_to_v1i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v1i8_to_v1i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v1i8_to_v1i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: flat_store_dword v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v1i8_to_v1i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v1i8_to_v1i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 1, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <1 x i8>, ptr addrspace(4) %in
%ext = zext <1 x i8> %load to <1 x i32>
store <1 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v1i8_to_v1i32:
-
-; EG: VTX_READ_8 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1
-; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
-; EG: 8
define amdgpu_kernel void @constant_sextload_v1i8_to_v1i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v1i8_to_v1i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_sbyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v1i8_to_v1i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_sbyte v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: flat_store_dword v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v1i8_to_v1i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_sbyte v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v1i8_to_v1i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)
%load = load <1 x i8>, ptr addrspace(4) %in
%ext = sext <1 x i8> %load to <1 x i32>
store <1 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v2i8_to_v2i32:
-; GCN-NOHSA: buffer_load_ushort
-; GCN-HSA: flat_load_ushort
-
-; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; TODO: This should use DST, but for some there are redundant MOVs
-; EG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG: 8
define amdgpu_kernel void @constant_zextload_v2i8_to_v2i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v2i8_to_v2i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX6-NOHSA-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v2i8_to_v2i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ushort v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: v_lshrrev_b32_e32 v3, 8, v2
+; GFX7-HSA-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v2i8_to_v2i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ushort v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e32 v3, 8, v2
+; GFX8-NOHSA-NEXT: v_and_b32_e32 v2, 0xff, v2
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v2i8_to_v2i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 12, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XY, T5.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_16 T4.X, T4.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.Y, T2.X,
+; EG-NEXT: MOV * T4.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: AND_INT T0.W, T4.X, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 65535(9.183409e-41), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T2.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: MOV * T1.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T4.Y, PV.Y, literal.x, PV.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T4.X, T0.W, literal.x,
+; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.y,
+; EG-NEXT: 255(3.573311e-43), 2(2.802597e-45)
%load = load <2 x i8>, ptr addrspace(4) %in
%ext = zext <2 x i8> %load to <2 x i32>
store <2 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v2i8_to_v2i32:
-; GCN-NOHSA: buffer_load_ushort
-
-; GCN-HSA: flat_load_ushort
-
-; GCN: v_bfe_i32
-; GCN: v_bfe_i32
-
-; EG: VTX_READ_16 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: 8
-; EG-DAG: 8
define amdgpu_kernel void @constant_sextload_v2i8_to_v2i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v2i8_to_v2i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: v_bfe_i32 v1, v0, 8, 8
+; GFX6-NOHSA-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v2i8_to_v2i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ushort v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: v_bfe_i32 v3, v2, 8, 8
+; GFX7-HSA-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v2i8_to_v2i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ushort v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e32 v3, 8, v2
+; GFX8-NOHSA-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX8-NOHSA-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v2i8_to_v2i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 11, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XY, T5.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_16 T4.X, T4.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.Y, T2.X,
+; EG-NEXT: MOV * T4.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: AND_INT T0.W, T4.X, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 65535(9.183409e-41), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T2.X, PV.W,
+; EG-NEXT: MOV * T0.Y, PV.X,
+; EG-NEXT: BFE_INT T4.X, T0.W, 0.0, literal.x,
+; EG-NEXT: LSHR T0.W, PV.Y, literal.x,
+; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)
+; EG-NEXT: BFE_INT * T4.Y, PV.W, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
%load = load <2 x i8>, ptr addrspace(4) %in
%ext = sext <2 x i8> %load to <2 x i32>
store <2 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v3i8_to_v3i32:
-; GCN: s_load_dword s
-
-; GCN-DAG: s_bfe_u32
-; GCN-DAG: s_bfe_u32
-; GCN-DAG: s_and_b32
-
-; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: 8
-; EG-DAG: 8
define amdgpu_kernel void @constant_zextload_v3i8_to_v3i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v3i8_to_v3i32:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_bfe_u32 s5, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_u32 s6, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v3i8_to_v3i32:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_bfe_u32 s0, s2, 0x80008
+; GFX7-HSA-NEXT: s_and_b32 s1, s2, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s2, s2, 0x80010
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v3i8_to_v3i32:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_and_b32 s0, s2, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s1, s2, 0x80010
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NOHSA-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v3i8_to_v3i32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.X, T7.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XY, T6.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T4.X, T4.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T4.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T5.Y, T4.X, literal.x, PV.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T5.X, T4.X, literal.x,
+; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.y,
+; EG-NEXT: 255(3.573311e-43), 2(2.802597e-45)
+; EG-NEXT: BFE_UINT T4.X, T4.X, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), 8(1.121039e-44)
+; EG-NEXT: LSHR * T7.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%ld = load <3 x i8>, ptr addrspace(4) %in
%ext = zext <3 x i8> %ld to <3 x i32>
@@ -178,22 +958,86 @@ entry:
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v3i8_to_v3i32:
-; GCN: s_load_dword s
-
-; GCN-DAG: s_bfe_i32
-; GCN-DAG: s_bfe_i32
-; GCN-DAG: s_bfe_i32
-
-; EG: VTX_READ_32 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
define amdgpu_kernel void @constant_sextload_v3i8_to_v3i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v3i8_to_v3i32:
+; GFX6-NOHSA: ; %bb.0: ; %entry
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_bfe_i32 s5, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_i32 s6, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[0:3], 0 offset:8
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v3i8_to_v3i32:
+; GFX7-HSA: ; %bb.0: ; %entry
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_bfe_i32 s0, s2, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s1, s2, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-HSA-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v3i8_to_v3i32:
+; GFX8-NOHSA: ; %bb.0: ; %entry
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s2
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s2, 0x80010
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s1, s2
+; GFX8-NOHSA-NEXT: v_bfe_i32 v1, v0, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx3 v[3:4], v[0:2]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v3i8_to_v3i32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.X, T4.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XY, T5.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T4.X, T4.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T4.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHR T5.X, KC0[2].Y, literal.x,
+; EG-NEXT: LSHR * T0.W, T4.X, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: BFE_INT * T6.X, PV.W, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T7.X, T4.X, 0.0, literal.x,
+; EG-NEXT: LSHR T0.W, T4.X, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T4.X, PS, literal.x,
+; EG-NEXT: BFE_INT * T7.Y, PV.W, 0.0, literal.y,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
entry:
%ld = load <3 x i8>, ptr addrspace(4) %in
%ext = sext <3 x i8> %ld to <3 x i32>
@@ -201,521 +1045,6524 @@ entry:
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v4i8_to_v4i32:
-; GCN: s_load_dword s
-; GCN-DAG: s_and_b32
-; GCN-DAG: s_lshr_b32
-
-; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
define amdgpu_kernel void @constant_zextload_v4i8_to_v4i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v4i8_to_v4i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s4, s2, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s5, s2, 0x80008
+; GFX6-NOHSA-NEXT: s_and_b32 s6, s2, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s7, s2, 0x80010
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s4
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v4i8_to_v4i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s0, s2, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s1, s2, 0x80008
+; GFX7-HSA-NEXT: s_and_b32 s3, s2, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s2, s2, 0x80010
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v4i8_to_v4i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s2, 24
+; GFX8-NOHSA-NEXT: s_and_b32 s1, s2, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s2
+; GFX8-NOHSA-NEXT: s_bfe_u32 s2, s2, 0x80010
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v4i8_to_v4i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 9, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T5.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T4.X, T4.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T4.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T4.Z, T4.X, literal.x, PV.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T4.Y, T4.X, literal.x, T0.W,
+; EG-NEXT: LSHR * T4.W, T4.X, literal.y,
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: AND_INT T4.X, T4.X, literal.x,
+; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.y,
+; EG-NEXT: 255(3.573311e-43), 2(2.802597e-45)
%load = load <4 x i8>, ptr addrspace(4) %in
%ext = zext <4 x i8> %load to <4 x i32>
store <4 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v4i8_to_v4i32:
-; GCN: s_load_dword s
-; GCN-DAG: s_sext_i32_i8
-; GCN-DAG: s_ashr_i32
-
-; EG: VTX_READ_32 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
define amdgpu_kernel void @constant_sextload_v4i8_to_v4i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v4i8_to_v4i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s4, s2, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s5, s2, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s6, s2, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s7, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s4
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v4i8_to_v4i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s0, s2, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s1, s2, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s3, s2, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v4i8_to_v4i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s2
+; GFX8-NOHSA-NEXT: s_ashr_i32 s0, s2, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s1, s2, 0x80010
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX8-NOHSA-NEXT: v_bfe_i32 v1, v0, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v4i8_to_v4i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 11, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T4.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T4.X, T4.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T4.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T5.X, T4.X, 0.0, literal.x,
+; EG-NEXT: LSHR * T0.W, T4.X, literal.y,
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: BFE_INT T5.W, PV.W, 0.0, literal.x,
+; EG-NEXT: LSHR * T0.W, T4.X, literal.y,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T5.Z, PS, 0.0, literal.x,
+; EG-NEXT: LSHR * T0.W, T4.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T4.X, KC0[2].Y, literal.x,
+; EG-NEXT: BFE_INT * T5.Y, PV.W, 0.0, literal.y,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
%load = load <4 x i8>, ptr addrspace(4) %in
%ext = sext <4 x i8> %load to <4 x i32>
store <4 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v8i8_to_v8i32:
-; GCN: s_load_dwordx2
-; GCN-DAG: s_and_b32
-; GCN-DAG: s_lshr_b32
-
-; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
define amdgpu_kernel void @constant_zextload_v8i8_to_v8i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v8i8_to_v8i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s6, s4, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s7, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s8, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s9, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_and_b32 s10, s4, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s11, s5, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s6
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v8i8_to_v8i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s4, s2, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s5, s2, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s6, s3, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s7, s3, 0x80008
+; GFX7-HSA-NEXT: s_and_b32 s8, s2, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s9, s2, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s2, s3, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s3, s3, 0x80010
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v8i8_to_v8i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s4, s3, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s5, s2, 24
+; GFX8-NOHSA-NEXT: s_and_b32 s6, s3, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s3
+; GFX8-NOHSA-NEXT: s_bfe_u32 s3, s3, 0x80010
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v3, 8, s2
+; GFX8-NOHSA-NEXT: s_and_b32 s7, s2, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s2, s2, 0x80010
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s0, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[2:5]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v8i8_to_v8i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 20, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T8.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T5.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T5.XY, T5.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T5.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T6.Z, T5.X, literal.x, PV.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T6.Y, T5.X, literal.x, T0.W,
+; EG-NEXT: BFE_UINT T7.Z, T5.Y, literal.y, T0.W,
+; EG-NEXT: LSHR * T6.W, T5.X, literal.z,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T6.X, T5.X, literal.x,
+; EG-NEXT: BFE_UINT T7.Y, T5.Y, literal.y, T0.W,
+; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.z,
+; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44)
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: LSHR * T7.W, T5.Y, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T7.X, T5.Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 255(3.573311e-43), 16(2.242078e-44)
+; EG-NEXT: LSHR * T8.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <8 x i8>, ptr addrspace(4) %in
%ext = zext <8 x i8> %load to <8 x i32>
store <8 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v8i8_to_v8i32:
-; GCN: s_load_dwordx2
-; GCN-DAG: s_ashr_i32
-; GCN-DAG: s_sext_i32_i8
-
-; EG: VTX_READ_64 [[DST:T[0-9]+\.XY]], T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
define amdgpu_kernel void @constant_sextload_v8i8_to_v8i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v8i8_to_v8i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s6, s4, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s7, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s8, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_ashr_i32 s9, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s10, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s11, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s9
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s6
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v8i8_to_v8i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s4, s2, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s5, s2, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s6, s2, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s7, s2
+; GFX7-HSA-NEXT: s_ashr_i32 s2, s3, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s8, s3, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s9, s3, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s3, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v8i8_to_v8i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_ashr_i32 s4, s3, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s5, s3, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s6, s2, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s7, s2, 0x80010
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s2
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s0, 16
+; GFX8-NOHSA-NEXT: v_bfe_i32 v3, v0, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s6
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s3
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s3, s3
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[2:5]
+; GFX8-NOHSA-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v8i8_to_v8i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 23, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T8.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T5.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T5.XY, T5.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T5.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T6.X, T5.X, 0.0, literal.x,
+; EG-NEXT: LSHR * T0.W, T5.X, literal.y,
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: BFE_INT T7.X, T5.Y, 0.0, literal.x,
+; EG-NEXT: LSHR T0.Z, T5.Y, literal.y,
+; EG-NEXT: BFE_INT T6.W, PV.W, 0.0, literal.x,
+; EG-NEXT: LSHR * T0.W, T5.X, literal.z,
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T0.Y, T5.Y, literal.x,
+; EG-NEXT: BFE_INT T6.Z, PS, 0.0, literal.y,
+; EG-NEXT: BFE_INT T7.W, PV.Z, 0.0, literal.y,
+; EG-NEXT: LSHR * T0.W, T5.X, literal.y,
+; EG-NEXT: 16(2.242078e-44), 8(1.121039e-44)
+; EG-NEXT: LSHR T5.X, KC0[2].Y, literal.x,
+; EG-NEXT: BFE_INT T6.Y, PS, 0.0, literal.y,
+; EG-NEXT: BFE_INT T7.Z, PV.Y, 0.0, literal.y,
+; EG-NEXT: LSHR T0.W, T5.Y, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T8.X, PS, literal.x,
+; EG-NEXT: BFE_INT * T7.Y, PV.W, 0.0, literal.y,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
%load = load <8 x i8>, ptr addrspace(4) %in
%ext = sext <8 x i8> %load to <8 x i32>
store <8 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v16i8_to_v16i32:
-
-; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
define amdgpu_kernel void @constant_zextload_v16i8_to_v16i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v16i8_to_v16i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s8, s4, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s9, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s10, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s11, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s12, s6, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s13, s6, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s14, s7, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s15, s7, 0x80008
+; GFX6-NOHSA-NEXT: s_and_b32 s16, s4, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s17, s5, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s18, s6, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s19, s7, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s7, s7, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s6, s6, 0x80010
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s17
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s10
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v16i8_to_v16i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s8, s4, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s9, s4, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s10, s5, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s11, s5, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s12, s6, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s13, s6, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s2, s7, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s3, s7, 0x80008
+; GFX7-HSA-NEXT: s_and_b32 s14, s4, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s15, s5, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s16, s6, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s6, s6, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s17, s7, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s7, s7, 0x80010
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v16i8_to_v16i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s8, s4, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s9, s5, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s10, s6, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s2, s7, 24
+; GFX8-NOHSA-NEXT: s_and_b32 s11, s4, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s4
+; GFX8-NOHSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s12, s5, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v3, 8, s5
+; GFX8-NOHSA-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s13, s6, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v5, 8, s6
+; GFX8-NOHSA-NEXT: s_bfe_u32 s6, s6, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s3, s7, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v7, 8, s7
+; GFX8-NOHSA-NEXT: s_bfe_u32 s7, s7, 0x80010
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s7
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[6:9]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s10
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[2:5]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v16i8_to_v16i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 39, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T14.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XYZW, T13.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T11.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T7.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T7.XYZW, T7.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T7.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T8.Z, T7.X, literal.x, PV.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T8.Y, T7.X, literal.x, T0.W,
+; EG-NEXT: BFE_UINT T9.Z, T7.Y, literal.y, T0.W,
+; EG-NEXT: LSHR * T8.W, T7.X, literal.z,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T8.X, T7.X, literal.x,
+; EG-NEXT: BFE_UINT T9.Y, T7.Y, literal.y, T0.W,
+; EG-NEXT: LSHR * T7.X, KC0[2].Y, literal.z,
+; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44)
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T10.Z, T7.Z, literal.x, T0.W,
+; EG-NEXT: LSHR * T9.W, T7.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: AND_INT T9.X, T7.Y, literal.x,
+; EG-NEXT: BFE_UINT T10.Y, T7.Z, literal.y, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T11.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T12.Z, T7.W, literal.y, T0.W,
+; EG-NEXT: LSHR T10.W, T7.Z, literal.z,
+; EG-NEXT: AND_INT * T10.X, T7.Z, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T12.Y, T7.W, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 32(4.484155e-44)
+; EG-NEXT: LSHR T13.X, PV.W, literal.x,
+; EG-NEXT: LSHR T12.W, T7.W, literal.y,
+; EG-NEXT: AND_INT * T12.X, T7.W, literal.z,
+; EG-NEXT: 2(2.802597e-45), 24(3.363116e-44)
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR * T14.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <16 x i8>, ptr addrspace(4) %in
%ext = zext <16 x i8> %load to <16 x i32>
store <16 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v16i8_to_v16i32:
-
-; EG: VTX_READ_128 [[DST:T[0-9]+\.XYZW]], T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
define amdgpu_kernel void @constant_sextload_v16i8_to_v16i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v16i8_to_v16i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s8, s4, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s9, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s10, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX6-NOHSA-NEXT: s_ashr_i32 s11, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s12, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s13, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX6-NOHSA-NEXT: s_ashr_i32 s14, s6, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s15, s6, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s16, s6, 0x80008
+; GFX6-NOHSA-NEXT: s_ashr_i32 s17, s7, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s18, s7, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s19, s7, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s6, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s17
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v16i8_to_v16i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s8, s4, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s9, s4, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s10, s4, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s11, s5, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s12, s5, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s13, s5, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s14, s6, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s15, s6, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s16, s6, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s2, s7, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s3, s7, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s17, s7, 0x80008
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: s_sext_i32_i8 s6, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v16i8_to_v16i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_ashr_i32 s8, s4, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s9, s4, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s10, s5, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s11, s5, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s12, s6, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s13, s6, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s2, s7, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s3, s7, 0x80010
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s3
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s7
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NOHSA-NEXT: v_bfe_i32 v7, v0, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s7
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[6:9]
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v2, 8, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s3
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s6, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: v_bfe_i32 v5, v2, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s12
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v3, 8, s5
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NOHSA-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s4
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[2:5]
+; GFX8-NOHSA-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v16i8_to_v16i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 47, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T14.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T13.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XYZW, T7.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T8.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T7.XYZW, T7.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T7.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: LSHR T8.X, KC0[2].Y, literal.x,
+; EG-NEXT: LSHR T0.W, T7.W, literal.y,
+; EG-NEXT: LSHR * T1.W, T7.Z, literal.z,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T9.X, T7.X, 0.0, literal.x,
+; EG-NEXT: LSHR T0.Y, T7.W, literal.y,
+; EG-NEXT: LSHR T0.Z, T7.Z, literal.z,
+; EG-NEXT: LSHR T2.W, T7.Y, literal.x,
+; EG-NEXT: LSHR * T3.W, T7.X, literal.y,
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T10.X, T7.Y, 0.0, literal.x,
+; EG-NEXT: LSHR T1.Y, T7.Z, literal.y,
+; EG-NEXT: LSHR T1.Z, T7.Y, literal.y,
+; EG-NEXT: BFE_INT T9.W, PS, 0.0, literal.x,
+; EG-NEXT: LSHR * T3.W, T7.X, literal.z,
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T11.X, T7.Z, 0.0, literal.x,
+; EG-NEXT: LSHR T2.Y, T7.Y, literal.y,
+; EG-NEXT: BFE_INT T9.Z, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T10.W, PV.Z, 0.0, literal.x,
+; EG-NEXT: LSHR * T3.W, T7.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T12.X, T7.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T9.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T10.Z, PV.Y, 0.0, literal.x,
+; EG-NEXT: BFE_INT T11.W, T1.Y, 0.0, literal.x,
+; EG-NEXT: ADD_INT * T3.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: LSHR T7.X, PS, literal.x,
+; EG-NEXT: BFE_INT T10.Y, T2.W, 0.0, literal.y,
+; EG-NEXT: BFE_INT T11.Z, T0.Z, 0.0, literal.y,
+; EG-NEXT: BFE_INT T12.W, T0.Y, 0.0, literal.y,
+; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
+; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T13.X, PS, literal.x,
+; EG-NEXT: BFE_INT T11.Y, T1.W, 0.0, literal.y,
+; EG-NEXT: BFE_INT T12.Z, T0.W, 0.0, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT: LSHR T0.W, T7.W, literal.y, BS:VEC_201
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
+; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T14.X, PS, literal.x,
+; EG-NEXT: BFE_INT * T12.Y, PV.W, 0.0, literal.y,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
%load = load <16 x i8>, ptr addrspace(4) %in
%ext = sext <16 x i8> %load to <16 x i32>
store <16 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v32i8_to_v32i32:
-
-; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
-; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
; TODO: These should use DST, but for some there are redundant MOVs
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, {{.*}}literal
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
define amdgpu_kernel void @constant_zextload_v32i8_to_v32i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v32i8_to_v32i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s12, s4, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s13, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s14, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s15, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s16, s6, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s17, s6, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s18, s7, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s19, s7, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s20, s8, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s21, s8, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s22, s9, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s23, s9, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s24, s10, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s25, s10, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s26, s11, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s27, s11, 0x80008
+; GFX6-NOHSA-NEXT: s_and_b32 s28, s4, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s29, s5, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s30, s6, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s6, s6, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s31, s7, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s7, s7, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s33, s8, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s8, s8, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s34, s9, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s9, s9, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s35, s10, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s36, s11, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s11, s11, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s10, s10, 0x80010
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s36
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s27
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s26
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s35
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s24
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s34
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s22
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s33
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s20
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s16
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s29
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v32i8_to_v32i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s12, s4, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s13, s4, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s14, s5, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s15, s5, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s16, s6, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s17, s6, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s18, s7, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s19, s7, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s20, s8, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s21, s8, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s22, s9, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s23, s9, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s24, s10, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s25, s10, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s2, s11, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s3, s11, 0x80008
+; GFX7-HSA-NEXT: s_and_b32 s26, s4, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s27, s5, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s28, s6, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s6, s6, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s29, s7, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s7, s7, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s30, s8, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s8, s8, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s31, s9, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s9, s9, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s33, s10, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s10, s10, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s34, s11, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s11, s11, 0x80010
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x70
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s33
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s24
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s22
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s20
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s16
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v32i8_to_v32i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s10, s0, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s11, s1, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s12, s2, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s13, s3, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s14, s4, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s15, s5, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s16, s6, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s17, s7, 24
+; GFX8-NOHSA-NEXT: s_and_b32 s18, s0, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s0
+; GFX8-NOHSA-NEXT: s_bfe_u32 s19, s0, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s20, s1, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v3, 8, s1
+; GFX8-NOHSA-NEXT: s_bfe_u32 s21, s1, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s22, s2, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v5, 8, s2
+; GFX8-NOHSA-NEXT: s_bfe_u32 s2, s2, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s23, s3, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v7, 8, s3
+; GFX8-NOHSA-NEXT: s_bfe_u32 s3, s3, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s24, s4, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v9, 8, s4
+; GFX8-NOHSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s25, s5, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s26, s5, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s27, s6, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s28, s6, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s0, s7, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s1, s7, 0x80010
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 0x70
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s1
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 0x60
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s17
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 0x50
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s27
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s28
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s16
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 64
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s25
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s26
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s15
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s14
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s23
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 32
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s13
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[6:9]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s22
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s12
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s20
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s21
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[2:5]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v32i8_to_v32i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @16, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @12
+; EG-NEXT: ALU 75, @17, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T24.XYZW, T26.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T22.XYZW, T25.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T21.XYZW, T23.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T12.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T20.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T18.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T16.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T11.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 12:
+; EG-NEXT: VTX_READ_128 T12.XYZW, T11.X, 16, #1
+; EG-NEXT: VTX_READ_128 T11.XYZW, T11.X, 0, #1
+; EG-NEXT: ALU clause starting at 16:
+; EG-NEXT: MOV * T11.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 17:
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T13.Z, T11.X, literal.x, PV.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T13.Y, T11.X, literal.x, T0.W,
+; EG-NEXT: BFE_UINT T14.Z, T11.Y, literal.y, T0.W,
+; EG-NEXT: LSHR * T13.W, T11.X, literal.z,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T13.X, T11.X, literal.x,
+; EG-NEXT: BFE_UINT T14.Y, T11.Y, literal.y, T0.W,
+; EG-NEXT: LSHR * T11.X, KC0[2].Y, literal.z,
+; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44)
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T15.Z, T11.Z, literal.x, T0.W,
+; EG-NEXT: LSHR * T14.W, T11.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: AND_INT T14.X, T11.Y, literal.x,
+; EG-NEXT: BFE_UINT T15.Y, T11.Z, literal.y, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T16.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T17.Z, T11.W, literal.y, T0.W,
+; EG-NEXT: LSHR T15.W, T11.Z, literal.z,
+; EG-NEXT: AND_INT * T15.X, T11.Z, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T17.Y, T11.W, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 32(4.484155e-44)
+; EG-NEXT: LSHR T18.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T19.Z, T12.X, literal.y, T0.W, BS:VEC_021/SCL_122
+; EG-NEXT: LSHR T17.W, T11.W, literal.z,
+; EG-NEXT: AND_INT * T17.X, T11.W, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T19.Y, T12.X, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 48(6.726233e-44)
+; EG-NEXT: LSHR T20.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T21.Z, T12.Y, literal.y, T0.W,
+; EG-NEXT: LSHR T19.W, T12.X, literal.z,
+; EG-NEXT: AND_INT * T19.X, T12.X, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T21.Y, T12.Y, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 64(8.968310e-44)
+; EG-NEXT: LSHR T12.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T22.Z, T12.Z, literal.y, T0.W,
+; EG-NEXT: LSHR T21.W, T12.Y, literal.z,
+; EG-NEXT: AND_INT * T21.X, T12.Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T22.Y, T12.Z, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 80(1.121039e-43)
+; EG-NEXT: LSHR T23.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T24.Z, T12.W, literal.y, T0.W,
+; EG-NEXT: LSHR T22.W, T12.Z, literal.z,
+; EG-NEXT: AND_INT * T22.X, T12.Z, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T24.Y, T12.W, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 96(1.345247e-43)
+; EG-NEXT: LSHR T25.X, PV.W, literal.x,
+; EG-NEXT: LSHR T24.W, T12.W, literal.y,
+; EG-NEXT: AND_INT * T24.X, T12.W, literal.z,
+; EG-NEXT: 2(2.802597e-45), 24(3.363116e-44)
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 112(1.569454e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR * T26.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <32 x i8>, ptr addrspace(4) %in
%ext = zext <32 x i8> %load to <32 x i32>
store <32 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v32i8_to_v32i32:
-
-; EG-DAG: VTX_READ_128 [[DST_LO:T[0-9]+\.XYZW]], T{{[0-9]+}}.X, 0, #1
-; EG-DAG: VTX_READ_128 [[DST_HI:T[0-9]+\.XYZW]], T{{[0-9]+}}.X, 16, #1
; TODO: These should use DST, but for some there are redundant MOVs
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9]+.[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
-; EG-DAG: 8
define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v32i8_to_v32i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s12, s4, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s13, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s14, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX6-NOHSA-NEXT: s_ashr_i32 s15, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s16, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s17, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX6-NOHSA-NEXT: s_ashr_i32 s18, s6, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s19, s6, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s20, s6, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s6, s6
+; GFX6-NOHSA-NEXT: s_ashr_i32 s21, s7, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s22, s7, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s23, s7, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX6-NOHSA-NEXT: s_ashr_i32 s24, s8, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s25, s8, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s26, s8, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s8, s8
+; GFX6-NOHSA-NEXT: s_ashr_i32 s27, s9, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s28, s9, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s29, s9, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s9, s9
+; GFX6-NOHSA-NEXT: s_ashr_i32 s30, s10, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s31, s10, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s33, s10, 0x80008
+; GFX6-NOHSA-NEXT: s_ashr_i32 s34, s11, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s35, s11, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s36, s11, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s11, s11
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s10, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s36
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s35
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s34
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s33
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s30
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s28
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s27
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s26
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s25
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s24
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s21
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s20
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v32i8_to_v32i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s12, s4, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s13, s4, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s14, s4, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s15, s5, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s16, s5, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s17, s5, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s18, s6, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s19, s6, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s20, s6, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s21, s7, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s22, s7, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s23, s7, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s24, s8, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s25, s8, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s26, s8, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s27, s9, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s28, s9, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s29, s9, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s30, s10, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s31, s10, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s33, s10, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s2, s11, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s3, s11, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s34, s11, 0x80008
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x70
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: s_sext_i32_i8 s11, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s34
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: s_sext_i32_i8 s10, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s33
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s30
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: s_sext_i32_i8 s9, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s27
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: s_sext_i32_i8 s8, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s24
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s21
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: s_sext_i32_i8 s6, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v32i8_to_v32i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v3, 8, s1
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s0
+; GFX8-NOHSA-NEXT: s_ashr_i32 s10, s0, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s11, s0, 0x80010
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s12, s0
+; GFX8-NOHSA-NEXT: s_ashr_i32 s13, s1, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s14, s1, 0x80010
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s15, s1
+; GFX8-NOHSA-NEXT: s_ashr_i32 s16, s2, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s17, s2, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s18, s3, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s19, s3, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s20, s4, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s21, s4, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s22, s5, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s23, s5, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s24, s6, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s25, s6, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s0, s7, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s1, s7, 0x80010
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 0x70
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s1
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s1
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s7
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 0x60
+; GFX8-NOHSA-NEXT: v_bfe_i32 v11, v0, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s7
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s1
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v2, 8, s6
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s6, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 0x50
+; GFX8-NOHSA-NEXT: v_bfe_i32 v11, v2, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s25
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s24
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s1
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v4, 8, s5
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 64
+; GFX8-NOHSA-NEXT: v_bfe_i32 v11, v4, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s23
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s22
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v6, 8, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s1
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 48
+; GFX8-NOHSA-NEXT: v_bfe_i32 v9, v6, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s21
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s20
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v7, 8, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s1
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s3, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 32
+; GFX8-NOHSA-NEXT: v_bfe_i32 v7, v7, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s19
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s18
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[6:9]
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v5, 8, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s1
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 16
+; GFX8-NOHSA-NEXT: v_bfe_i32 v5, v5, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s17
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s16
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NOHSA-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[2:5]
+; GFX8-NOHSA-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v32i8_to_v32i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @18, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @14
+; EG-NEXT: ALU 18, @19, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @16
+; EG-NEXT: ALU 75, @38, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T24.XYZW, T26.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T23.XYZW, T25.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T12.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T22.XYZW, T17.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T21.XYZW, T16.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T15.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T14.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T18.XYZW, T13.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 14:
+; EG-NEXT: VTX_READ_128 T12.XYZW, T11.X, 16, #1
+; EG-NEXT: Fetch clause starting at 16:
+; EG-NEXT: VTX_READ_128 T11.XYZW, T11.X, 0, #1
+; EG-NEXT: ALU clause starting at 18:
+; EG-NEXT: MOV * T11.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 19:
+; EG-NEXT: LSHR T13.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T14.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T15.X, PV.W, literal.x,
+; EG-NEXT: LSHR T0.Z, T12.W, literal.y,
+; EG-NEXT: LSHR T0.W, T12.Z, literal.z,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 8(1.121039e-44), 48(6.726233e-44)
+; EG-NEXT: LSHR T16.X, PS, literal.x,
+; EG-NEXT: LSHR T0.Y, T12.W, literal.y,
+; EG-NEXT: LSHR T1.Z, T12.Z, literal.z,
+; EG-NEXT: LSHR T1.W, T12.Y, literal.w,
+; EG-NEXT: LSHR * T2.W, T12.Z, literal.y,
+; EG-NEXT: 2(2.802597e-45), 24(3.363116e-44)
+; EG-NEXT: 16(2.242078e-44), 8(1.121039e-44)
+; EG-NEXT: ALU clause starting at 38:
+; EG-NEXT: ADD_INT * T3.W, KC0[2].Y, literal.x,
+; EG-NEXT: 64(8.968310e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T17.X, PV.W, literal.x,
+; EG-NEXT: LSHR T1.Y, T12.Y, literal.y,
+; EG-NEXT: LSHR T2.Z, T12.Y, literal.z,
+; EG-NEXT: LSHR T3.W, T12.X, literal.y,
+; EG-NEXT: LSHR * T4.W, T12.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T18.X, T11.X, 0.0, literal.x,
+; EG-NEXT: LSHR T2.Y, T11.W, literal.y,
+; EG-NEXT: LSHR T3.Z, T11.W, literal.z,
+; EG-NEXT: LSHR T5.W, T11.Z, literal.y,
+; EG-NEXT: LSHR * T6.W, T11.X, literal.z,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T19.X, T11.Y, 0.0, literal.x,
+; EG-NEXT: LSHR T3.Y, T11.Z, literal.y,
+; EG-NEXT: LSHR T4.Z, T11.Y, literal.y,
+; EG-NEXT: BFE_INT T18.W, PS, 0.0, literal.x,
+; EG-NEXT: LSHR * T6.W, T11.X, literal.z,
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T20.X, T11.Z, 0.0, literal.x,
+; EG-NEXT: LSHR T4.Y, T11.Y, literal.y,
+; EG-NEXT: BFE_INT T18.Z, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T19.W, PV.Z, 0.0, literal.x,
+; EG-NEXT: LSHR * T6.W, T11.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T21.X, T11.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T18.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T19.Z, PV.Y, 0.0, literal.x,
+; EG-NEXT: BFE_INT T20.W, T3.Y, 0.0, literal.x,
+; EG-NEXT: LSHR * T6.W, T11.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T22.X, T12.X, 0.0, literal.x,
+; EG-NEXT: BFE_INT T19.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T20.Z, T5.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T21.W, T3.Z, 0.0, literal.x,
+; EG-NEXT: LSHR * T5.W, T11.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T11.X, T12.Y, 0.0, literal.x,
+; EG-NEXT: BFE_INT T20.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T21.Z, T2.Y, 0.0, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: BFE_INT T22.W, T4.W, 0.0, literal.x,
+; EG-NEXT: LSHR * T4.W, T11.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T23.X, T12.Z, 0.0, literal.x,
+; EG-NEXT: BFE_INT T21.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T22.Z, T3.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T11.W, T2.Z, 0.0, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: LSHR * T3.W, T12.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T24.X, T12.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T22.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T11.Z, T1.Y, 0.0, literal.x,
+; EG-NEXT: BFE_INT T23.W, T2.W, 0.0, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 80(1.121039e-43)
+; EG-NEXT: LSHR T12.X, PS, literal.x,
+; EG-NEXT: BFE_INT T11.Y, T1.W, 0.0, literal.y,
+; EG-NEXT: BFE_INT T23.Z, T1.Z, 0.0, literal.y,
+; EG-NEXT: BFE_INT T24.W, T0.Y, 0.0, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
+; EG-NEXT: 96(1.345247e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T25.X, PS, literal.x,
+; EG-NEXT: BFE_INT T23.Y, T0.W, 0.0, literal.y,
+; EG-NEXT: BFE_INT T24.Z, T0.Z, 0.0, literal.y,
+; EG-NEXT: LSHR T0.W, T12.W, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
+; EG-NEXT: 112(1.569454e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T26.X, PS, literal.x,
+; EG-NEXT: BFE_INT * T24.Y, PV.W, 0.0, literal.y,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
%load = load <32 x i8>, ptr addrspace(4) %in
%ext = sext <32 x i8> %load to <32 x i32>
store <32 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v64i8_to_v64i32:
-
-; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 0, #1
-; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 16, #1
-; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 32, #1
-; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 48, #1
define amdgpu_kernel void @constant_zextload_v64i8_to_v64i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v64i8_to_v64i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s18, s0, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s19, s0, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s20, s1, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s21, s1, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s22, s2, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s23, s2, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s24, s3, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s25, s3, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s26, s4, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s27, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s28, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s29, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s30, s6, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s31, s6, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s33, s7, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s34, s7, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s35, s8, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s36, s8, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s37, s9, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s38, s9, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s39, s10, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s40, s10, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s41, s11, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s42, s11, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s43, s12, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s44, s12, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s45, s13, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s46, s13, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s47, s14, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s48, s14, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s49, s15, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s50, s15, 0x80008
+; GFX6-NOHSA-NEXT: s_and_b32 s51, s0, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s52, s0, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s53, s1, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s54, s1, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s55, s2, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s56, s2, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s57, s3, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s58, s3, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s59, s4, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s60, s5, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s61, s6, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s6, s6, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s62, s7, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s7, s7, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s63, s8, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s8, s8, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s64, s9, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s9, s9, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s65, s10, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s10, s10, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s66, s11, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s67, s12, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s12, s12, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s68, s13, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s69, s14, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s14, s14, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s70, s15, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s15, s15, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s13, s13, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s11, s11, 0x80010
+; GFX6-NOHSA-NEXT: s_mov_b32 s0, s16
+; GFX6-NOHSA-NEXT: s_mov_b32 s1, s17
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s70
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s50
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s49
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s69
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s48
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s47
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s68
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v9, s46
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s45
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s67
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v13, s44
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v14, s12
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:240
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:224
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:208
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v15, s43
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:192
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(3)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s66
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s42
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s41
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:176
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s65
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s40
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s39
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:160
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s64
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s38
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s37
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s63
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s36
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s35
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s62
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s34
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s33
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s61
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s30
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s60
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s28
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s59
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s27
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s26
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s57
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s58
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s24
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s55
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s56
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s22
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s53
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s54
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s20
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s51
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s52
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v64i8_to_v64i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s18, s0, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s19, s0, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s20, s1, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s21, s1, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s22, s2, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s23, s2, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s25, s3, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s26, s3, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s28, s4, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s29, s4, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s31, s5, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s33, s5, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s34, s6, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s35, s6, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s36, s7, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s37, s7, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s38, s8, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s39, s8, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s40, s9, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s41, s9, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s42, s10, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s43, s10, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s44, s11, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s45, s11, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s46, s12, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s47, s12, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s48, s13, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s49, s13, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s50, s14, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s51, s14, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s52, s15, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s53, s15, 0x80008
+; GFX7-HSA-NEXT: s_and_b32 s24, s0, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s0, s0, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s27, s1, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s1, s1, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s30, s2, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s2, s2, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s54, s3, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s3, s3, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s55, s4, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s56, s4, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s57, s5, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s58, s5, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s59, s6, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s6, s6, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s60, s7, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s7, s7, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s61, s8, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s8, s8, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s62, s9, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s9, s9, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s63, s10, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s10, s10, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s64, s11, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s11, s11, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s65, s12, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s12, s12, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s66, s13, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s13, s13, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s67, s14, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s14, s14, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s68, s15, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s15, s15, 0x80010
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 0xf0
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 0xe0
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 0xd0
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 0xc0
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v29, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v28, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 0xb0
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v31, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v30, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 0xa0
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v33, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v32, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 0x90
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s67
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s51
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s50
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[4:7]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 0x80
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v35, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s68
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s53
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s52
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s66
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s49
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s65
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s47
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s46
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s45
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s44
+; GFX7-HSA-NEXT: v_mov_b32_e32 v34, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s61
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s39
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s38
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 0x70
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s63
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s43
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s62
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s42
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s41
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[8:11]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[28:29], v[12:15]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s40
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[30:31], v[16:19]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[32:33], v[20:23]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[34:35], v[4:7]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s37
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 0x60
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s59
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s35
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 0x50
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s57
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s33
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s58
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 64
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s55
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s56
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 48
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s54
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s16, 32
+; GFX7-HSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s16, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s22
+; GFX7-HSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v64i8_to_v64i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s18, s0, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s19, s1, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s21, s2, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s23, s3, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s25, s4, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s27, s5, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s30, s6, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s31, s7, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s33, s8, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s34, s9, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s35, s10, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s36, s11, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s37, s12, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s38, s13, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s39, s14, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s28, s15, 24
+; GFX8-NOHSA-NEXT: s_and_b32 s20, s0, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s0
+; GFX8-NOHSA-NEXT: s_bfe_u32 s0, s0, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s22, s1, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v3, 8, s1
+; GFX8-NOHSA-NEXT: s_bfe_u32 s1, s1, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s24, s2, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v5, 8, s2
+; GFX8-NOHSA-NEXT: s_bfe_u32 s2, s2, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s26, s3, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v7, 8, s3
+; GFX8-NOHSA-NEXT: s_bfe_u32 s3, s3, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s40, s4, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v9, 8, s4
+; GFX8-NOHSA-NEXT: s_bfe_u32 s41, s4, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s4, s5, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s42, s5, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s43, s6, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s44, s6, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s45, s7, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s46, s7, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s47, s8, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s48, s8, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s49, s9, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s50, s9, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s51, s10, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s52, s10, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s53, s11, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s54, s11, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s55, s12, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s56, s12, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s57, s13, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s58, s13, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s59, s14, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s60, s14, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s29, s15, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s15
+; GFX8-NOHSA-NEXT: s_bfe_u32 s15, s15, 0x80010
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s28
+; GFX8-NOHSA-NEXT: s_add_u32 s28, s16, 0xf0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s29
+; GFX8-NOHSA-NEXT: s_addc_u32 s29, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s28
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s29
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s40
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s14
+; GFX8-NOHSA-NEXT: s_add_u32 s14, s16, 0xe0
+; GFX8-NOHSA-NEXT: s_addc_u32 s15, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s59
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s60
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s39
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s15
+; GFX8-NOHSA-NEXT: s_add_u32 s14, s16, 0xd0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: s_addc_u32 s15, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s14
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s57
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s58
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s38
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s15
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s26
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s12
+; GFX8-NOHSA-NEXT: s_add_u32 s12, s16, 0xc0
+; GFX8-NOHSA-NEXT: s_addc_u32 s13, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s12
+; GFX8-NOHSA-NEXT: s_add_u32 s12, s16, 0xb0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s55
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s56
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s37
+; GFX8-NOHSA-NEXT: s_addc_u32 s13, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s13
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s53
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s54
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s36
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s12
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s24
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s10
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s16, 0xa0
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s10
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s16, 0x90
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s51
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s52
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s35
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s11
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s49
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s50
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s34
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s10
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s8
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s16, 0x80
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s8
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s16, 0x70
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s47
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s33
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s9
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s45
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s46
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s8
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s6
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s16, 0x60
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s43
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s44
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s30
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s6
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 0x50
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v11, 8, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 64
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s42
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s27
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[14:15], v[10:13]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s41
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s25
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s23
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[6:9]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s16, 32
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s16, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s21
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s19
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[2:5]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v64i8_to_v64i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @30, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @22
+; EG-NEXT: ALU 59, @31, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @26
+; EG-NEXT: ALU 88, @91, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T48.XYZW, T50.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T46.XYZW, T49.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T45.XYZW, T47.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T43.XYZW, T32.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T41.XYZW, T44.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T39.XYZW, T42.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T38.XYZW, T40.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T36.XYZW, T33.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T34.XYZW, T37.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T35.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T30.XYZW, T31.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T28.XYZW, T20.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T26.XYZW, T29.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T24.XYZW, T27.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T23.XYZW, T25.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T22.XYZW, T21.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 22:
+; EG-NEXT: VTX_READ_128 T20.XYZW, T19.X, 16, #1
+; EG-NEXT: VTX_READ_128 T21.XYZW, T19.X, 0, #1
+; EG-NEXT: Fetch clause starting at 26:
+; EG-NEXT: VTX_READ_128 T32.XYZW, T19.X, 48, #1
+; EG-NEXT: VTX_READ_128 T33.XYZW, T19.X, 32, #1
+; EG-NEXT: ALU clause starting at 30:
+; EG-NEXT: MOV * T19.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 31:
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T22.Z, T21.X, literal.x, PV.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T22.Y, T21.X, literal.x, T0.W,
+; EG-NEXT: BFE_UINT T23.Z, T21.Y, literal.y, T0.W,
+; EG-NEXT: LSHR * T22.W, T21.X, literal.z,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T22.X, T21.X, literal.x,
+; EG-NEXT: BFE_UINT T23.Y, T21.Y, literal.y, T0.W,
+; EG-NEXT: LSHR * T21.X, KC0[2].Y, literal.z,
+; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44)
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T24.Z, T21.Z, literal.x, T0.W,
+; EG-NEXT: LSHR * T23.W, T21.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: AND_INT T23.X, T21.Y, literal.x,
+; EG-NEXT: BFE_UINT T24.Y, T21.Z, literal.y, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T25.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T26.Z, T21.W, literal.y, T0.W,
+; EG-NEXT: LSHR T24.W, T21.Z, literal.z,
+; EG-NEXT: AND_INT * T24.X, T21.Z, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T26.Y, T21.W, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 32(4.484155e-44)
+; EG-NEXT: LSHR T27.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T28.Z, T20.X, literal.y, T0.W, BS:VEC_021/SCL_122
+; EG-NEXT: LSHR T26.W, T21.W, literal.z,
+; EG-NEXT: AND_INT * T26.X, T21.W, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T28.Y, T20.X, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 48(6.726233e-44)
+; EG-NEXT: LSHR T29.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T30.Z, T20.Y, literal.y, T0.W,
+; EG-NEXT: LSHR T28.W, T20.X, literal.z,
+; EG-NEXT: AND_INT * T28.X, T20.X, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T30.Y, T20.Y, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 64(8.968310e-44)
+; EG-NEXT: LSHR T20.X, PV.W, literal.x,
+; EG-NEXT: LSHR T30.W, T20.Y, literal.y,
+; EG-NEXT: AND_INT * T30.X, T20.Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 24(3.363116e-44)
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T19.Z, T20.Z, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), 80(1.121039e-43)
+; EG-NEXT: LSHR T31.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT * T19.Y, T20.Z, literal.y, T0.W,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
+; EG-NEXT: ALU clause starting at 91:
+; EG-NEXT: BFE_UINT T34.Z, T20.W, literal.x, T0.W,
+; EG-NEXT: LSHR * T19.W, T20.Z, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: AND_INT T19.X, T20.Z, literal.x,
+; EG-NEXT: BFE_UINT T34.Y, T20.W, literal.y, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 255(3.573311e-43), 8(1.121039e-44)
+; EG-NEXT: 96(1.345247e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T35.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T36.Z, T33.X, literal.y, T0.W, BS:VEC_021/SCL_122
+; EG-NEXT: LSHR T34.W, T20.W, literal.z,
+; EG-NEXT: AND_INT * T34.X, T20.W, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T36.Y, T33.X, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 112(1.569454e-43)
+; EG-NEXT: LSHR T37.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T38.Z, T33.Y, literal.y, T0.W,
+; EG-NEXT: LSHR T36.W, T33.X, literal.z,
+; EG-NEXT: AND_INT * T36.X, T33.X, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T38.Y, T33.Y, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 128(1.793662e-43)
+; EG-NEXT: LSHR T33.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T39.Z, T33.Z, literal.y, T0.W,
+; EG-NEXT: LSHR T38.W, T33.Y, literal.z,
+; EG-NEXT: AND_INT * T38.X, T33.Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T39.Y, T33.Z, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 144(2.017870e-43)
+; EG-NEXT: LSHR T40.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T41.Z, T33.W, literal.y, T0.W,
+; EG-NEXT: LSHR T39.W, T33.Z, literal.z,
+; EG-NEXT: AND_INT * T39.X, T33.Z, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T41.Y, T33.W, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 160(2.242078e-43)
+; EG-NEXT: LSHR T42.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T43.Z, T32.X, literal.y, T0.W, BS:VEC_021/SCL_122
+; EG-NEXT: LSHR T41.W, T33.W, literal.z,
+; EG-NEXT: AND_INT * T41.X, T33.W, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T43.Y, T32.X, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 176(2.466285e-43)
+; EG-NEXT: LSHR T44.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T45.Z, T32.Y, literal.y, T0.W,
+; EG-NEXT: LSHR T43.W, T32.X, literal.z,
+; EG-NEXT: AND_INT * T43.X, T32.X, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T45.Y, T32.Y, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 192(2.690493e-43)
+; EG-NEXT: LSHR T32.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T46.Z, T32.Z, literal.y, T0.W,
+; EG-NEXT: LSHR T45.W, T32.Y, literal.z,
+; EG-NEXT: AND_INT * T45.X, T32.Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T46.Y, T32.Z, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 208(2.914701e-43)
+; EG-NEXT: LSHR T47.X, PV.W, literal.x,
+; EG-NEXT: BFE_UINT T48.Z, T32.W, literal.y, T0.W,
+; EG-NEXT: LSHR T46.W, T32.Z, literal.z,
+; EG-NEXT: AND_INT * T46.X, T32.Z, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 255(3.573311e-43)
+; EG-NEXT: BFE_UINT T48.Y, T32.W, literal.x, T0.W,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 224(3.138909e-43)
+; EG-NEXT: LSHR T49.X, PV.W, literal.x,
+; EG-NEXT: LSHR T48.W, T32.W, literal.y,
+; EG-NEXT: AND_INT * T48.X, T32.W, literal.z,
+; EG-NEXT: 2(2.802597e-45), 24(3.363116e-44)
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 240(3.363116e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR * T50.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <64 x i8>, ptr addrspace(4) %in
%ext = zext <64 x i8> %load to <64 x i32>
store <64 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v64i8_to_v64i32:
-
-; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 0, #1
-; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 16, #1
-; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 32, #1
-; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 48, #1
define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v64i8_to_v64i32:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s18, s0, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s19, s0, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s20, s0, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s21, s0
+; GFX6-NOHSA-NEXT: s_ashr_i32 s22, s1, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s23, s1, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s24, s1, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s25, s1
+; GFX6-NOHSA-NEXT: s_ashr_i32 s26, s2, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s27, s2, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s28, s2, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s29, s2
+; GFX6-NOHSA-NEXT: s_ashr_i32 s30, s3, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s31, s3, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s33, s3, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s34, s3
+; GFX6-NOHSA-NEXT: s_ashr_i32 s35, s4, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s36, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s37, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX6-NOHSA-NEXT: s_ashr_i32 s38, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s39, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s40, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX6-NOHSA-NEXT: s_ashr_i32 s41, s6, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s42, s6, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s43, s6, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s6, s6
+; GFX6-NOHSA-NEXT: s_ashr_i32 s44, s7, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s45, s7, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s46, s7, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX6-NOHSA-NEXT: s_ashr_i32 s47, s8, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s48, s8, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s49, s8, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s8, s8
+; GFX6-NOHSA-NEXT: s_ashr_i32 s50, s9, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s51, s9, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s52, s9, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s9, s9
+; GFX6-NOHSA-NEXT: s_ashr_i32 s53, s10, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s54, s10, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s55, s10, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s10, s10
+; GFX6-NOHSA-NEXT: s_ashr_i32 s56, s11, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s57, s11, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s58, s11, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s11, s11
+; GFX6-NOHSA-NEXT: s_bfe_i32 s59, s12, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s60, s12, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s61, s12
+; GFX6-NOHSA-NEXT: s_ashr_i32 s62, s13, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s63, s13, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s64, s13, 0x80008
+; GFX6-NOHSA-NEXT: s_ashr_i32 s65, s14, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s66, s14, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s67, s14, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s14, s14
+; GFX6-NOHSA-NEXT: s_ashr_i32 s68, s15, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s69, s15, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s70, s15, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s15, s15
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s13, s13
+; GFX6-NOHSA-NEXT: s_ashr_i32 s12, s12, 24
+; GFX6-NOHSA-NEXT: s_mov_b32 s0, s16
+; GFX6-NOHSA-NEXT: s_mov_b32 s1, s17
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s70
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s69
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s68
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s67
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s66
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s65
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v9, s64
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s63
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s62
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s61
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v13, s60
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v14, s59
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:240
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:224
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:208
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v15, s12
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[12:15], off, s[0:3], 0 offset:192
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(3)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s58
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s57
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s56
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:176
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s55
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s54
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s53
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:160
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s52
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s51
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s50
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:144
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s49
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s48
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s47
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:128
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s46
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s45
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s44
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s43
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s42
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s41
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s40
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s39
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s38
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s37
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s36
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s35
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s34
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s33
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s30
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s29
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s28
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s27
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s26
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s25
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s24
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s23
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s22
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s21
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s20
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v64i8_to_v64i32:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[16:19], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s18, s0, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s19, s0, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s20, s0, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s21, s1, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s22, s1, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s23, s1, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s24, s2, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s25, s2, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s26, s2, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s27, s3, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s28, s3, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s29, s3, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s30, s4, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s31, s4, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s33, s4, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s34, s5, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s35, s5, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s36, s5, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s37, s6, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s38, s6, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s39, s6, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s41, s7, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s42, s7, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s43, s7, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s45, s8, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s46, s8, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s47, s8, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s48, s9, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s49, s9, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s50, s9, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s51, s10, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s52, s10, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s53, s10, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s54, s11, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s55, s11, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s56, s11, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s57, s12, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s58, s12, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s59, s12, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s60, s13, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s61, s13, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s62, s13, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s63, s14, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s64, s14, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s65, s14, 0x80008
+; GFX7-HSA-NEXT: s_ashr_i32 s66, s15, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s67, s15, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s68, s15, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s40, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0xf0
+; GFX7-HSA-NEXT: s_sext_i32_i8 s44, s7
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0xe0
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0xd0
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0xc0
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v29, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v28, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0xb0
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v31, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v30, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0xa0
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v33, s7
+; GFX7-HSA-NEXT: s_sext_i32_i8 s14, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v32, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x90
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s65
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s63
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[4:7]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x80
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: s_sext_i32_i8 s8, s8
+; GFX7-HSA-NEXT: s_sext_i32_i8 s11, s11
+; GFX7-HSA-NEXT: s_sext_i32_i8 s12, s12
+; GFX7-HSA-NEXT: s_sext_i32_i8 s13, s13
+; GFX7-HSA-NEXT: s_sext_i32_i8 s15, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v35, s7
+; GFX7-HSA-NEXT: s_sext_i32_i8 s9, s9
+; GFX7-HSA-NEXT: s_sext_i32_i8 s10, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s68
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s67
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s66
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s62
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s61
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s59
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s58
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s57
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s56
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s55
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s54
+; GFX7-HSA-NEXT: v_mov_b32_e32 v34, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s47
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s46
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s45
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x70
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s53
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s52
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s51
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s50
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[8:11]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s49
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[28:29], v[12:15]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s48
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[30:31], v[16:19]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[32:33], v[20:23]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[0:3]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[34:35], v[4:7]
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s44
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s43
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s42
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s41
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x60
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s40
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s39
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s37
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX7-HSA-NEXT: s_add_u32 s6, s16, 0x50
+; GFX7-HSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s7, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s35
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_sext_i32_i8 s3, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 64
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s33
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s16, 48
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_sext_i32_i8 s1, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s16, 32
+; GFX7-HSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s16, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s24
+; GFX7-HSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s21
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_sext_i32_i8 s0, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v64i8_to_v64i32:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[16:19], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx16 s[0:15], s[18:19], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v17, 8, s14
+; GFX8-NOHSA-NEXT: s_ashr_i32 s18, s0, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s19, s0, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s20, s1, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s21, s1, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s22, s2, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s23, s2, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s24, s3, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s25, s3, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s26, s4, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s27, s4, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s28, s5, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s29, s5, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s30, s6, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s31, s6, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s33, s7, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s34, s7, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s35, s8, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s36, s8, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s37, s9, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s38, s9, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s39, s10, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s40, s10, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s41, s11, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s42, s11, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s43, s12, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s44, s12, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s45, s13, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s46, s13, 0x80010
+; GFX8-NOHSA-NEXT: s_ashr_i32 s47, s14, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s48, s14, 0x80010
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s49, s14
+; GFX8-NOHSA-NEXT: s_ashr_i32 s14, s15, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s50, s15, 0x80010
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v5, 8, s15
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s15, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s14
+; GFX8-NOHSA-NEXT: s_add_u32 s14, s16, 0xf0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s15
+; GFX8-NOHSA-NEXT: s_addc_u32 s15, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NOHSA-NEXT: s_add_u32 s14, s16, 0xe0
+; GFX8-NOHSA-NEXT: v_bfe_i32 v12, v5, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s50
+; GFX8-NOHSA-NEXT: s_addc_u32 s15, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s15
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v19, 8, s12
+; GFX8-NOHSA-NEXT: v_bfe_i32 v12, v17, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s49
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s47
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s14
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s14, s12
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s12, s13
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v18, 8, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s12
+; GFX8-NOHSA-NEXT: s_add_u32 s12, s16, 0xd0
+; GFX8-NOHSA-NEXT: s_addc_u32 s13, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s12
+; GFX8-NOHSA-NEXT: s_add_u32 s12, s16, 0xc0
+; GFX8-NOHSA-NEXT: v_bfe_i32 v12, v18, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s46
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s45
+; GFX8-NOHSA-NEXT: s_addc_u32 s13, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s12
+; GFX8-NOHSA-NEXT: s_add_u32 s12, s16, 0xb0
+; GFX8-NOHSA-NEXT: v_bfe_i32 v12, v19, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s44
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s43
+; GFX8-NOHSA-NEXT: s_addc_u32 s13, s17, 0
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v20, 8, s11
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s11, s11
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s13
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v7, 8, s8
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v6, 8, s4
+; GFX8-NOHSA-NEXT: v_bfe_i32 v12, v20, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s42
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s41
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s12
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s11, s4
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s4, s8
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s8, s10
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v8, 8, s9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s8
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s16, 0xa0
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s12, s9
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v9, 8, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s9
+; GFX8-NOHSA-NEXT: v_bfe_i32 v12, v9, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s40
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s39
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s8
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s16, 0x90
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX8-NOHSA-NEXT: v_bfe_i32 v12, v8, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s38
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s37
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s16, 0x80
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[11:14]
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s17, 0
+; GFX8-NOHSA-NEXT: v_bfe_i32 v12, v7, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s36
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s35
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s9
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s4, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[7:8], v[11:14]
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 0x70
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s8, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s5
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v4, 8, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 0x60
+; GFX8-NOHSA-NEXT: v_bfe_i32 v12, v4, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s34
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s33
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[11:14]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s5
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v2, 8, s6
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s6, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 0x50
+; GFX8-NOHSA-NEXT: v_bfe_i32 v12, v2, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s30
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[11:14]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 64
+; GFX8-NOHSA-NEXT: v_bfe_i32 v12, v0, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s29
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s28
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[11:14]
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v21, 8, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s16, 48
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX8-NOHSA-NEXT: v_bfe_i32 v7, v6, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s27
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s26
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s17, 0
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v10, 8, s3
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s3, s3
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[11:12], v[6:9]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s5
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s16, 32
+; GFX8-NOHSA-NEXT: v_bfe_i32 v10, v10, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s25
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s4
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[9:12]
+; GFX8-NOHSA-NEXT: v_bfe_i32 v5, v21, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s16, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s23
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s22
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s17, 0
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v3, 8, s1
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s1, s1
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NOHSA-NEXT: v_bfe_i32 v3, v3, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s21
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s20
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s0
+; GFX8-NOHSA-NEXT: s_sext_i32_i8 s0, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[2:5]
+; GFX8-NOHSA-NEXT: v_bfe_i32 v1, v1, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s17
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v64i8_to_v64i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @32, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @24
+; EG-NEXT: ALU 40, @33, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @28
+; EG-NEXT: ALU 76, @74, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 72, @151, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T48.XYZW, T50.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T47.XYZW, T49.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T19.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T46.XYZW, T35.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T45.XYZW, T34.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T44.XYZW, T33.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T21.XYZW, T32.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T43.XYZW, T30.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T42.XYZW, T29.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T41.XYZW, T28.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T31.XYZW, T27.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T40.XYZW, T26.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T39.XYZW, T25.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T38.XYZW, T24.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T37.XYZW, T23.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T36.XYZW, T22.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 24:
+; EG-NEXT: VTX_READ_128 T20.XYZW, T21.X, 32, #1
+; EG-NEXT: VTX_READ_128 T19.XYZW, T21.X, 48, #1
+; EG-NEXT: Fetch clause starting at 28:
+; EG-NEXT: VTX_READ_128 T31.XYZW, T21.X, 0, #1
+; EG-NEXT: VTX_READ_128 T21.XYZW, T21.X, 16, #1
+; EG-NEXT: ALU clause starting at 32:
+; EG-NEXT: MOV * T21.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 33:
+; EG-NEXT: LSHR T22.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T23.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T24.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T25.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T26.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T27.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: LSHR T28.X, PV.W, literal.x,
+; EG-NEXT: LSHR T0.Y, T19.W, literal.y,
+; EG-NEXT: LSHR T0.Z, T19.Z, literal.z,
+; EG-NEXT: LSHR * T0.W, T19.W, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,
+; EG-NEXT: 112(1.569454e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T29.X, PV.W, literal.x,
+; EG-NEXT: LSHR T1.Y, T19.Z, literal.y,
+; EG-NEXT: LSHR T1.Z, T19.Y, literal.z,
+; EG-NEXT: LSHR * T1.W, T19.Z, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,
+; EG-NEXT: 128(1.793662e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T30.X, PV.W, literal.x,
+; EG-NEXT: LSHR T2.Y, T19.Y, literal.y,
+; EG-NEXT: LSHR T2.Z, T19.Y, literal.z,
+; EG-NEXT: LSHR T2.W, T19.X, literal.y,
+; EG-NEXT: LSHR * T3.W, T19.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 74:
+; EG-NEXT: LSHR T3.Y, T20.W, literal.x,
+; EG-NEXT: LSHR T3.Z, T20.W, literal.y,
+; EG-NEXT: LSHR T4.W, T20.Z, literal.x,
+; EG-NEXT: ADD_INT * T5.W, KC0[2].Y, literal.z,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: 144(2.017870e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T32.X, PS, literal.x,
+; EG-NEXT: LSHR T4.Y, T20.Z, literal.y,
+; EG-NEXT: LSHR T4.Z, T20.Y, literal.z,
+; EG-NEXT: LSHR T5.W, T20.Y, literal.y,
+; EG-NEXT: ADD_INT * T6.W, KC0[2].Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 24(3.363116e-44)
+; EG-NEXT: 16(2.242078e-44), 160(2.242078e-43)
+; EG-NEXT: LSHR T33.X, PS, literal.x,
+; EG-NEXT: LSHR T5.Y, T20.X, literal.y,
+; EG-NEXT: LSHR T5.Z, T20.X, literal.z,
+; EG-NEXT: LSHR T6.W, T21.W, literal.y,
+; EG-NEXT: ADD_INT * T7.W, KC0[2].Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 176(2.466285e-43)
+; EG-NEXT: LSHR T34.X, PS, literal.x,
+; EG-NEXT: LSHR T6.Y, T21.W, literal.y,
+; EG-NEXT: LSHR T6.Z, T21.Z, literal.z,
+; EG-NEXT: LSHR T7.W, T21.Z, literal.y,
+; EG-NEXT: ADD_INT * T8.W, KC0[2].Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 24(3.363116e-44)
+; EG-NEXT: 16(2.242078e-44), 192(2.690493e-43)
+; EG-NEXT: LSHR T35.X, PS, literal.x,
+; EG-NEXT: LSHR T7.Y, T21.Y, literal.y,
+; EG-NEXT: LSHR T7.Z, T21.Y, literal.z,
+; EG-NEXT: LSHR T8.W, T21.X, literal.y,
+; EG-NEXT: LSHR * T9.W, T21.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T36.X, T31.X, 0.0, literal.x,
+; EG-NEXT: LSHR T8.Y, T31.W, literal.y,
+; EG-NEXT: LSHR T8.Z, T31.W, literal.z,
+; EG-NEXT: LSHR T10.W, T31.Z, literal.y,
+; EG-NEXT: LSHR * T11.W, T31.X, literal.z,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T37.X, T31.Y, 0.0, literal.x,
+; EG-NEXT: LSHR T9.Y, T31.Z, literal.y,
+; EG-NEXT: LSHR T9.Z, T31.Y, literal.y,
+; EG-NEXT: BFE_INT T36.W, PS, 0.0, literal.x,
+; EG-NEXT: LSHR * T11.W, T31.X, literal.z,
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T38.X, T31.Z, 0.0, literal.x,
+; EG-NEXT: LSHR T10.Y, T31.Y, literal.y,
+; EG-NEXT: BFE_INT T36.Z, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T37.W, PV.Z, 0.0, literal.x,
+; EG-NEXT: LSHR * T11.W, T31.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T39.X, T31.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T36.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T37.Z, PV.Y, 0.0, literal.x,
+; EG-NEXT: BFE_INT T38.W, T9.Y, 0.0, literal.x,
+; EG-NEXT: LSHR * T11.W, T31.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T40.X, T21.X, 0.0, literal.x,
+; EG-NEXT: BFE_INT T37.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T38.Z, T10.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T39.W, T8.Z, 0.0, literal.x,
+; EG-NEXT: LSHR * T10.W, T31.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T31.X, T21.Y, 0.0, literal.x,
+; EG-NEXT: BFE_INT T38.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T39.Z, T8.Y, 0.0, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: BFE_INT T40.W, T9.W, 0.0, literal.x,
+; EG-NEXT: LSHR * T9.W, T31.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T41.X, T21.Z, 0.0, literal.x,
+; EG-NEXT: BFE_INT T39.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T40.Z, T8.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT * T31.W, T7.Z, 0.0, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 151:
+; EG-NEXT: LSHR * T8.W, T21.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T42.X, T21.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T40.Y, PV.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T31.Z, T7.Y, 0.0, literal.x,
+; EG-NEXT: BFE_INT T41.W, T7.W, 0.0, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: LSHR * T7.W, T21.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T43.X, T20.X, 0.0, literal.x,
+; EG-NEXT: BFE_INT T31.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T41.Z, T6.Z, 0.0, literal.x,
+; EG-NEXT: BFE_INT T42.W, T6.Y, 0.0, literal.x,
+; EG-NEXT: LSHR * T7.W, T21.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T21.X, T20.Y, 0.0, literal.x,
+; EG-NEXT: BFE_INT T41.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T42.Z, T6.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T43.W, T5.Z, 0.0, literal.x,
+; EG-NEXT: LSHR * T6.W, T21.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T44.X, T20.Z, 0.0, literal.x,
+; EG-NEXT: BFE_INT T42.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T43.Z, T5.Y, 0.0, literal.x,
+; EG-NEXT: BFE_INT T21.W, T5.W, 0.0, literal.x,
+; EG-NEXT: LSHR * T5.W, T20.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T45.X, T20.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T43.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T21.Z, T4.Z, 0.0, literal.x,
+; EG-NEXT: BFE_INT T44.W, T4.Y, 0.0, literal.x,
+; EG-NEXT: LSHR * T5.W, T20.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T46.X, T19.X, 0.0, literal.x,
+; EG-NEXT: BFE_INT T21.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T44.Z, T4.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T45.W, T3.Z, 0.0, literal.x,
+; EG-NEXT: LSHR * T4.W, T20.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T20.X, T19.Y, 0.0, literal.x,
+; EG-NEXT: BFE_INT T44.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T45.Z, T3.Y, 0.0, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: BFE_INT T46.W, T3.W, 0.0, literal.x,
+; EG-NEXT: LSHR * T3.W, T20.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T47.X, T19.Z, 0.0, literal.x,
+; EG-NEXT: BFE_INT T45.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T46.Z, T2.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T20.W, T2.Z, 0.0, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: LSHR * T2.W, T19.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T48.X, T19.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT T46.Y, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T20.Z, T2.Y, 0.0, literal.x,
+; EG-NEXT: BFE_INT T47.W, T1.W, 0.0, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 208(2.914701e-43)
+; EG-NEXT: LSHR T19.X, PS, literal.x,
+; EG-NEXT: BFE_INT T20.Y, T1.Z, 0.0, literal.y,
+; EG-NEXT: BFE_INT T47.Z, T1.Y, 0.0, literal.y,
+; EG-NEXT: BFE_INT T48.W, T0.W, 0.0, literal.y,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
+; EG-NEXT: 224(3.138909e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T49.X, PS, literal.x,
+; EG-NEXT: BFE_INT T47.Y, T0.Z, 0.0, literal.y,
+; EG-NEXT: BFE_INT T48.Z, T0.Y, 0.0, literal.y,
+; EG-NEXT: LSHR T0.W, T19.W, literal.y,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
+; EG-NEXT: 240(3.363116e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T50.X, PS, literal.x,
+; EG-NEXT: BFE_INT * T48.Y, PV.W, 0.0, literal.y,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
%load = load <64 x i8>, ptr addrspace(4) %in
%ext = sext <64 x i8> %load to <64 x i32>
store <64 x i32> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_i8_to_i64:
-; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
-
-; GCN-NOHSA-DAG: buffer_load_ubyte v[[LO:[0-9]+]],
-; GCN-NOHSA: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
-
-; GCN-HSA-DAG: flat_load_ubyte v[[LO:[0-9]+]],
-; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
-
-; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
-; EG: MOV {{.*}}, 0.0
define amdgpu_kernel void @constant_zextload_i8_to_i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_i8_to_i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_i8_to_i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_i8_to_i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, 0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_i8_to_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV * T0.Y, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%a = load i8, ptr addrspace(4) %in
%ext = zext i8 %a to i64
store i64 %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_i8_to_i64:
-; GCN-NOHSA: buffer_load_sbyte v[[LO:[0-9]+]],
-; GCN-HSA: flat_load_sbyte v[[LO:[0-9]+]],
-; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
-
-; GCN-NOHSA: buffer_store_dwordx2 v[[[LO]]:[[HI]]]
-; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[LO]]:[[HI]]]
-
-; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
-; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal
; TODO: Why not 7 ?
-; EG: 31
define amdgpu_kernel void @constant_sextload_i8_to_i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_i8_to_i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_sbyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_i8_to_i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_sbyte v0, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_i8_to_i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_sbyte v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_i8_to_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)
+; EG-NEXT: ASHR * T0.Y, PV.X, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
%a = load i8, ptr addrspace(4) %in
%ext = sext i8 %a to i64
store i64 %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v1i8_to_v1i64:
-
-; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
-; EG: MOV {{.*}}, 0.0
define amdgpu_kernel void @constant_zextload_v1i8_to_v1i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v1i8_to_v1i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v1i8_to_v1i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v1i8_to_v1i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ubyte v0, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v1i8_to_v1i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV * T0.Y, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <1 x i8>, ptr addrspace(4) %in
%ext = zext <1 x i8> %load to <1 x i64>
store <1 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v1i8_to_v1i64:
-
-; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
-; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal
; TODO: Why not 7 ?
-; EG: 31
define amdgpu_kernel void @constant_sextload_v1i8_to_v1i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v1i8_to_v1i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_sbyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v1i8_to_v1i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_sbyte v0, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v1i8_to_v1i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_sbyte v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: v_bfe_i32 v2, v2, 0, 16
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v1i8_to_v1i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T0.X, T0.X, 0.0, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)
+; EG-NEXT: ASHR * T0.Y, PV.X, literal.x,
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
%load = load <1 x i8>, ptr addrspace(4) %in
%ext = sext <1 x i8> %load to <1 x i64>
store <1 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v2i8_to_v2i64:
-
-; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v2i8_to_v2i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v2i8_to_v2i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX6-NOHSA-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v2i8_to_v2i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ushort v0, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX7-HSA-NEXT: v_and_b32_e32 v0, 0xff, v0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v2i8_to_v2i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ushort v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: v_and_b32_e32 v0, 0xff, v2
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e32 v2, 8, v2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v2i8_to_v2i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 14, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T5.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_16 T4.X, T4.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.Y, T2.X,
+; EG-NEXT: MOV * T4.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: AND_INT T0.W, T4.X, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 65535(9.183409e-41), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T2.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: MOV * T1.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT * T4.Z, PV.Y, literal.x, PV.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T4.X, T0.W, literal.x,
+; EG-NEXT: MOV T4.Y, 0.0,
+; EG-NEXT: MOV T4.W, 0.0,
+; EG-NEXT: LSHR * T5.X, KC0[2].Y, literal.y,
+; EG-NEXT: 255(3.573311e-43), 2(2.802597e-45)
%load = load <2 x i8>, ptr addrspace(4) %in
%ext = zext <2 x i8> %load to <2 x i64>
store <2 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v2i8_to_v2i64:
-
-; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_v2i8_to_v2i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v2i8_to_v2i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX6-NOHSA-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX6-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX6-NOHSA-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX6-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v2i8_to_v2i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ushort v0, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: v_lshrrev_b32_e32 v2, 8, v0
+; GFX7-HSA-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX7-HSA-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX7-HSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX7-HSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v2i8_to_v2i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ushort v0, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e32 v2, 8, v0
+; GFX8-NOHSA-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX8-NOHSA-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v1, 31, v0
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v2i8_to_v2i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 15, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T5.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_16 T4.X, T4.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.Y, T2.X,
+; EG-NEXT: MOV * T4.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: AND_INT T0.W, T4.X, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 65535(9.183409e-41), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T2.X, PV.W,
+; EG-NEXT: MOV * T0.Y, PV.X,
+; EG-NEXT: BFE_INT * T4.X, T0.W, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: ASHR T4.Y, PV.X, literal.x,
+; EG-NEXT: LSHR * T0.W, T0.Y, literal.y,
+; EG-NEXT: 31(4.344025e-44), 8(1.121039e-44)
+; EG-NEXT: BFE_INT * T4.Z, PV.W, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T5.X, KC0[2].Y, literal.x,
+; EG-NEXT: ASHR * T4.W, PV.Z, literal.y,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
%load = load <2 x i8>, ptr addrspace(4) %in
%ext = sext <2 x i8> %load to <2 x i64>
store <2 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v4i8_to_v4i64:
-
-; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v4i8_to_v4i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v4i8_to_v4i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_bfe_u32 s5, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_lshr_b32 s6, s4, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s7, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v4i8_to_v4i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_bfe_u32 s4, s2, 0x80008
+; GFX7-HSA-NEXT: s_lshr_b32 s3, s2, 24
+; GFX7-HSA-NEXT: s_and_b32 s5, s2, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s2, s2, 0x80010
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v4i8_to_v4i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s3, s2, 24
+; GFX8-NOHSA-NEXT: s_and_b32 s4, s2, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v6, 8, s2
+; GFX8-NOHSA-NEXT: s_bfe_u32 s2, s2, 0x80010
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v4i8_to_v4i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 17, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T7.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T6.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T4.X, T4.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T4.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T5.X, T4.X, literal.x, PV.W,
+; EG-NEXT: LSHR * T5.Z, T4.X, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T5.Y, 0.0,
+; EG-NEXT: BFE_UINT * T4.Z, T4.X, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T4.X, T4.X, literal.x,
+; EG-NEXT: MOV T4.Y, 0.0,
+; EG-NEXT: MOV T5.W, 0.0,
+; EG-NEXT: MOV * T4.W, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T6.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR * T7.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <4 x i8>, ptr addrspace(4) %in
%ext = zext <4 x i8> %load to <4 x i64>
store <4 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v4i8_to_v4i64:
-
-; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_v4i8_to_v4i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v4i8_to_v4i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s4, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s6, s4, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s8, s4, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s10, s4, 8
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[2:5], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v4i8_to_v4i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s4, s2, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s6, s2, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s8, s2, 8
+; GFX7-HSA-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v4i8_to_v4i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s4, s2, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s6, s2, 24
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s2
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 16
+; GFX8-NOHSA-NEXT: v_bfe_i32 v2, v0, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v4i8_to_v4i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 18, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T7.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T6.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T4.X, T4.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T4.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T5.X, T4.X, 0.0, literal.x,
+; EG-NEXT: ASHR T4.W, T4.X, literal.y,
+; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.z,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ASHR T5.Y, PV.X, literal.x,
+; EG-NEXT: ASHR T4.Z, T4.X, literal.y,
+; EG-NEXT: LSHR T0.W, T4.X, literal.z,
+; EG-NEXT: LSHR * T1.W, T4.X, literal.w,
+; EG-NEXT: 31(4.344025e-44), 24(3.363116e-44)
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T4.X, PS, 0.0, literal.x,
+; EG-NEXT: BFE_INT T5.Z, PV.W, 0.0, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: LSHR T7.X, PV.W, literal.x,
+; EG-NEXT: ASHR T4.Y, PV.X, literal.y,
+; EG-NEXT: ASHR * T5.W, PV.Z, literal.y,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
%load = load <4 x i8>, ptr addrspace(4) %in
%ext = sext <4 x i8> %load to <4 x i64>
store <4 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v8i8_to_v8i64:
-
-; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v8i8_to_v8i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v8i8_to_v8i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s6, s4, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s7, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s8, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_u32 s9, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_and_b32 s10, s4, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s11, s5, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v8i8_to_v8i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s4, s2, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s5, s3, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s6, s3, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s7, s2, 0x80008
+; GFX7-HSA-NEXT: s_and_b32 s8, s2, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s9, s3, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s10, s2, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s2, s3, 0x80010
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v8i8_to_v8i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s4, s3, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s5, s2, 24
+; GFX8-NOHSA-NEXT: s_and_b32 s6, s3, 0xff
+; GFX8-NOHSA-NEXT: s_and_b32 s7, s2, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v7, 8, s2
+; GFX8-NOHSA-NEXT: s_bfe_u32 s8, s2, 0x80010
+; GFX8-NOHSA-NEXT: s_bfe_u32 s2, s3, 0x80010
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v6, 8, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s0, 32
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v7
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v8i8_to_v8i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 34, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T12.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T11.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T10.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T9.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_64 T5.XY, T5.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T5.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T6.X, T5.Y, literal.x, PV.W,
+; EG-NEXT: LSHR * T6.Z, T5.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T6.Y, 0.0,
+; EG-NEXT: BFE_UINT * T7.Z, T5.Y, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T7.X, T5.Y, literal.x,
+; EG-NEXT: MOV * T7.Y, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T8.X, T5.X, literal.x, T0.W,
+; EG-NEXT: LSHR * T8.Z, T5.X, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T8.Y, 0.0,
+; EG-NEXT: BFE_UINT * T5.Z, T5.X, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T5.X, T5.X, literal.x,
+; EG-NEXT: MOV T5.Y, 0.0,
+; EG-NEXT: MOV T6.W, 0.0,
+; EG-NEXT: MOV * T7.W, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: MOV T8.W, 0.0,
+; EG-NEXT: MOV * T5.W, 0.0,
+; EG-NEXT: LSHR T9.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T10.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T11.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR * T12.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <8 x i8>, ptr addrspace(4) %in
%ext = zext <8 x i8> %load to <8 x i64>
store <8 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v8i8_to_v8i64:
-
-; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_v8i8_to_v8i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v8i8_to_v8i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s6, s5, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s8, s5, 8
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s5
+; GFX6-NOHSA-NEXT: s_lshr_b32 s12, s4, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s14, s4, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s16, s4, 8
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[18:19], s[4:5], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
+; GFX6-NOHSA-NEXT: s_ashr_i64 s[4:5], s[4:5], 56
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s18
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v9, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s9
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(1)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s17
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v8i8_to_v8i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s4, s3, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s6, s3, 8
+; GFX7-HSA-NEXT: s_mov_b32 s8, s3
+; GFX7-HSA-NEXT: s_lshr_b32 s10, s2, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s12, s2, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s14, s2, 8
+; GFX7-HSA-NEXT: s_bfe_i64 s[16:17], s[2:3], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GFX7-HSA-NEXT: s_ashr_i64 s[2:3], s[2:3], 56
+; GFX7-HSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v8i8_to_v8i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_mov_b32 s5, 0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s6, s3, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s8, s2, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s10, s2, 24
+; GFX8-NOHSA-NEXT: s_mov_b32 s4, s3
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s2
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s3
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[12:13], s[2:3], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GFX8-NOHSA-NEXT: s_ashr_i64 s[2:3], s[2:3], 56
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[6:7], s[6:7], 0x80000
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NOHSA-NEXT: v_bfe_i32 v2, v1, 0, 8
+; GFX8-NOHSA-NEXT: v_bfe_i32 v6, v0, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s0, 32
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v8i8_to_v8i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 39, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.XYZW, T12.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T9.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XYZW, T8.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T6.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_64 T5.XY, T5.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T5.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T7.X, T5.Y, 0.0, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: LSHR T8.X, PV.W, literal.x,
+; EG-NEXT: ASHR T7.Y, PV.X, literal.y,
+; EG-NEXT: LSHR T0.W, T5.Y, literal.z,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
+; EG-NEXT: 8(1.121039e-44), 32(4.484155e-44)
+; EG-NEXT: LSHR T9.X, PS, literal.x,
+; EG-NEXT: BFE_INT T7.Z, PV.W, 0.0, literal.y,
+; EG-NEXT: ASHR * T10.W, T5.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T11.X, T5.X, 0.0, literal.x,
+; EG-NEXT: ASHR T10.Z, T5.X, literal.y,
+; EG-NEXT: LSHR T0.W, T5.X, literal.z,
+; EG-NEXT: ASHR * T5.W, T5.Y, literal.w,
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: 16(2.242078e-44), 31(4.344025e-44)
+; EG-NEXT: BFE_INT T10.X, PV.W, 0.0, literal.x,
+; EG-NEXT: ASHR T11.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T5.Z, T5.Y, literal.z,
+; EG-NEXT: LSHR T0.W, T5.X, literal.x,
+; EG-NEXT: LSHR * T1.W, T5.Y, literal.w,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 24(3.363116e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T5.X, PS, 0.0, literal.x,
+; EG-NEXT: ASHR T10.Y, PV.X, literal.y,
+; EG-NEXT: BFE_INT T11.Z, PV.W, 0.0, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 48(6.726233e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T12.X, PV.W, literal.x,
+; EG-NEXT: ASHR T5.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T11.W, PV.Z, literal.y,
+; EG-NEXT: ASHR * T7.W, T7.Z, literal.y,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
%load = load <8 x i8>, ptr addrspace(4) %in
%ext = sext <8 x i8> %load to <8 x i64>
store <8 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v16i8_to_v16i64:
-
-; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v16i8_to_v16i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v16i8_to_v16i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s8, s5, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s9, s4, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s10, s7, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s11, s6, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s12, s6, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_u32 s13, s7, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_u32 s14, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_u32 s15, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_and_b32 s16, s5, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s17, s4, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s18, s7, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s19, s6, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s6, s6, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s7, s7, 0x80010
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s12
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:64
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:96
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s17
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:32
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v16i8_to_v16i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s8, s5, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s9, s4, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s10, s7, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s2, s6, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s11, s6, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s12, s7, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s13, s4, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s14, s5, 0x80008
+; GFX7-HSA-NEXT: s_and_b32 s15, s5, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s16, s4, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s17, s7, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s18, s6, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s7, s7, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s3, s6, 0x80010
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x70
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 0x60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: s_add_u32 s0, s0, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX7-HSA-NEXT: s_addc_u32 s1, s1, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v16i8_to_v16i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s8, s5, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s2, s7, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s9, s6, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s10, s4, 24
+; GFX8-NOHSA-NEXT: s_and_b32 s11, s4, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v6, 8, s4
+; GFX8-NOHSA-NEXT: s_and_b32 s12, s5, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v7, 8, s5
+; GFX8-NOHSA-NEXT: s_and_b32 s13, s7, 0xff
+; GFX8-NOHSA-NEXT: s_and_b32 s14, s6, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v9, 8, s6
+; GFX8-NOHSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX8-NOHSA-NEXT: s_bfe_u32 s6, s6, 0x80010
+; GFX8-NOHSA-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX8-NOHSA-NEXT: s_bfe_u32 s3, s7, 0x80010
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 0x70
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 48
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 0x50
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s8
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s9
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 64
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 0x60
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v9
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v8, 8, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 32
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v8
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v16i8_to_v16i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @12
+; EG-NEXT: ALU 68, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XYZW, T22.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T9.XYZW, T21.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T10.XYZW, T20.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T19.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T18.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T17.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T16.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T15.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 12:
+; EG-NEXT: VTX_READ_128 T7.XYZW, T7.X, 0, #1
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: MOV * T7.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 15:
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T8.X, T7.W, literal.x, PV.W,
+; EG-NEXT: LSHR * T8.Z, T7.W, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T8.Y, 0.0,
+; EG-NEXT: BFE_UINT * T9.Z, T7.W, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T9.X, T7.W, literal.x,
+; EG-NEXT: MOV * T9.Y, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T10.X, T7.Z, literal.x, T0.W,
+; EG-NEXT: LSHR * T10.Z, T7.Z, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T10.Y, 0.0,
+; EG-NEXT: BFE_UINT * T11.Z, T7.Z, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T11.X, T7.Z, literal.x,
+; EG-NEXT: MOV * T11.Y, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T12.X, T7.Y, literal.x, T0.W,
+; EG-NEXT: LSHR * T12.Z, T7.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T12.Y, 0.0,
+; EG-NEXT: BFE_UINT * T13.Z, T7.Y, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T13.X, T7.Y, literal.x,
+; EG-NEXT: MOV * T13.Y, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T14.X, T7.X, literal.x, T0.W,
+; EG-NEXT: LSHR * T14.Z, T7.X, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T14.Y, 0.0,
+; EG-NEXT: BFE_UINT * T7.Z, T7.X, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T7.X, T7.X, literal.x,
+; EG-NEXT: MOV T7.Y, 0.0,
+; EG-NEXT: MOV T8.W, 0.0,
+; EG-NEXT: MOV * T9.W, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: MOV T10.W, 0.0,
+; EG-NEXT: MOV * T11.W, 0.0,
+; EG-NEXT: MOV T12.W, 0.0,
+; EG-NEXT: MOV * T13.W, 0.0,
+; EG-NEXT: MOV T14.W, 0.0,
+; EG-NEXT: MOV * T7.W, 0.0,
+; EG-NEXT: LSHR T15.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T16.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T17.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T18.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T19.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T20.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: LSHR T21.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43)
+; EG-NEXT: LSHR * T22.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <16 x i8>, ptr addrspace(4) %in
%ext = zext <16 x i8> %load to <16 x i64>
store <16 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v16i8_to_v16i64:
-
-; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v16i8_to_v16i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s8, s7, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s10, s7, 8
+; GFX6-NOHSA-NEXT: s_mov_b32 s12, s7
+; GFX6-NOHSA-NEXT: s_lshr_b32 s14, s6, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s16, s6, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s18, s6, 8
+; GFX6-NOHSA-NEXT: s_lshr_b32 s20, s5, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s22, s5, 8
+; GFX6-NOHSA-NEXT: s_mov_b32 s24, s5
+; GFX6-NOHSA-NEXT: s_lshr_b32 s26, s4, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s28, s4, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s30, s4, 8
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[34:35], s[4:5], 0x80000
+; GFX6-NOHSA-NEXT: s_ashr_i64 s[4:5], s[4:5], 56
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[36:37], s[6:7], 0x80000
+; GFX6-NOHSA-NEXT: s_ashr_i64 s[6:7], s[6:7], 56
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s36
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v9, s37
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v13, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v14, s24
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v15, s25
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v18, s34
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v19, s35
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:112
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s11
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:96
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(1)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s17
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:80
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s18
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s19
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[0:3], 0 offset:64
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s20
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s21
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[10:13], off, s[0:3], 0 offset:48
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v16, s22
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v17, s23
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[14:17], off, s[0:3], 0 offset:32
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s26
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s27
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s28
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s29
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v20, s30
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v21, s31
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[18:21], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v16i8_to_v16i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s8, s7, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s10, s7, 8
+; GFX7-HSA-NEXT: s_mov_b32 s12, s7
+; GFX7-HSA-NEXT: s_lshr_b32 s14, s6, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s16, s6, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s18, s6, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s20, s5, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s22, s5, 8
+; GFX7-HSA-NEXT: s_mov_b32 s24, s5
+; GFX7-HSA-NEXT: s_lshr_b32 s26, s4, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s28, s4, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s30, s4, 8
+; GFX7-HSA-NEXT: s_bfe_i64 s[2:3], s[4:5], 0x80000
+; GFX7-HSA-NEXT: s_ashr_i64 s[34:35], s[4:5], 56
+; GFX7-HSA-NEXT: s_bfe_i64 s[36:37], s[6:7], 0x80000
+; GFX7-HSA-NEXT: s_ashr_i64 s[38:39], s[6:7], 56
+; GFX7-HSA-NEXT: s_bfe_i64 s[4:5], s[30:31], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[6:7], s[28:29], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[10:11], s[10:11], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[8:9], s[8:9], 0x80000
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: s_add_u32 s8, s0, 0x70
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-HSA-NEXT: s_addc_u32 s9, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s39
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: s_add_u32 s8, s0, 0x60
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s9, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: s_add_u32 s8, s0, 0x50
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s9, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: s_add_u32 s8, s0, 64
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s9, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s37
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: s_add_u32 s8, s0, 48
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s9, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s21
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s35
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: s_add_u32 s8, s0, 32
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s9, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-HSA-NEXT: s_add_u32 s6, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-HSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v16i8_to_v16i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s12, s11, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s14, s10, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s16, s10, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s18, s9, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s20, s8, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s22, s8, 24
+; GFX8-NOHSA-NEXT: s_mov_b32 s24, s11
+; GFX8-NOHSA-NEXT: s_mov_b32 s4, s9
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s11
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s10
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v4, 8, s9
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v2, 8, s8
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[2:3], s[8:9], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[6:7], s[10:11], 0x80000
+; GFX8-NOHSA-NEXT: s_ashr_i64 s[8:9], s[8:9], 56
+; GFX8-NOHSA-NEXT: s_ashr_i64 s[10:11], s[10:11], 56
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v18, s10
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s0, 0x70
+; GFX8-NOHSA-NEXT: v_bfe_i32 v10, v1, 0, 8
+; GFX8-NOHSA-NEXT: v_bfe_i32 v14, v0, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v19, s11
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s11
+; GFX8-NOHSA-NEXT: s_add_u32 s10, s0, 0x50
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
+; GFX8-NOHSA-NEXT: s_addc_u32 s11, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v18, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v19, s17
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s11
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v18, s8
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s0, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v19, s9
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s19
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s0, 16
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s20
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s21
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v18, s22
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v19, s23
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NOHSA-NEXT: s_add_u32 s8, s0, 0x60
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
+; GFX8-NOHSA-NEXT: s_addc_u32 s9, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s25
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s6
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s0, 64
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s7
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: v_bfe_i32 v6, v4, 0, 8
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 32
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v16i8_to_v16i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @12
+; EG-NEXT: ALU 78, @15, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T21.XYZW, T22.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T16.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T15.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T7.XYZW, T12.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T11.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T10.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T9.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T18.XYZW, T8.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 12:
+; EG-NEXT: VTX_READ_128 T7.XYZW, T7.X, 0, #1
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: MOV * T7.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 15:
+; EG-NEXT: LSHR T8.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T9.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T10.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T11.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR * T12.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT * T13.X, T7.W, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T14.X, T7.Y, 0.0, literal.x,
+; EG-NEXT: ASHR T13.Y, PV.X, literal.y,
+; EG-NEXT: LSHR T0.W, T7.W, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 80(1.121039e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T15.X, PS, literal.x,
+; EG-NEXT: ASHR T14.Y, PV.X, literal.y,
+; EG-NEXT: BFE_INT T13.Z, PV.W, 0.0, literal.z,
+; EG-NEXT: LSHR T0.W, T7.Y, literal.z,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
+; EG-NEXT: 8(1.121039e-44), 96(1.345247e-43)
+; EG-NEXT: LSHR T16.X, PS, literal.x,
+; EG-NEXT: BFE_INT T14.Z, PV.W, 0.0, literal.y,
+; EG-NEXT: ASHR * T17.W, T7.X, literal.z,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
+; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T18.X, T7.X, 0.0, literal.x,
+; EG-NEXT: ASHR T17.Z, T7.X, literal.y,
+; EG-NEXT: LSHR T0.W, T7.X, literal.z,
+; EG-NEXT: ASHR * T19.W, T7.Y, literal.w,
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: 16(2.242078e-44), 31(4.344025e-44)
+; EG-NEXT: BFE_INT T17.X, PV.W, 0.0, literal.x,
+; EG-NEXT: ASHR T18.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T19.Z, T7.Y, literal.z,
+; EG-NEXT: LSHR T0.W, T7.X, literal.x,
+; EG-NEXT: LSHR * T1.W, T7.Y, literal.w,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 24(3.363116e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T19.X, PS, 0.0, literal.x,
+; EG-NEXT: ASHR T17.Y, PV.X, literal.y,
+; EG-NEXT: BFE_INT T18.Z, PV.W, 0.0, literal.x,
+; EG-NEXT: ADD_INT T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: ASHR * T20.W, T7.Z, literal.y,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 112(1.569454e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T7.X, T7.Z, 0.0, literal.x,
+; EG-NEXT: ASHR T19.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T20.Z, T7.Z, literal.z,
+; EG-NEXT: LSHR T1.W, T7.Z, literal.w,
+; EG-NEXT: ASHR * T21.W, T7.W, literal.y,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 24(3.363116e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T20.X, PV.W, 0.0, literal.x,
+; EG-NEXT: ASHR T7.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T21.Z, T7.W, literal.z,
+; EG-NEXT: LSHR T1.W, T7.Z, literal.x,
+; EG-NEXT: LSHR * T2.W, T7.W, literal.w,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 24(3.363116e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T21.X, PS, 0.0, literal.x,
+; EG-NEXT: ASHR T20.Y, PV.X, literal.y,
+; EG-NEXT: BFE_INT T7.Z, PV.W, 0.0, literal.x,
+; EG-NEXT: ASHR T18.W, T18.Z, literal.y,
+; EG-NEXT: ASHR * T14.W, T14.Z, literal.y,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: LSHR T22.X, T0.W, literal.x,
+; EG-NEXT: ASHR T21.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T7.W, PV.Z, literal.y,
+; EG-NEXT: ASHR * T13.W, T13.Z, literal.y,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
%load = load <16 x i8>, ptr addrspace(4) %in
%ext = sext <16 x i8> %load to <16 x i64>
store <16 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v32i8_to_v32i64:
-
-; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
-; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
define amdgpu_kernel void @constant_zextload_v32i8_to_v32i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v32i8_to_v32i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s12, s0, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s13, s1, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s14, s2, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s15, s3, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s16, s4, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s17, s5, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s18, s6, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s19, s7, 24
+; GFX6-NOHSA-NEXT: s_bfe_u32 s20, s7, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_u32 s21, s6, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_u32 s22, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_u32 s23, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_u32 s24, s3, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_u32 s25, s2, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_u32 s26, s1, 0x80008
+; GFX6-NOHSA-NEXT: s_bfe_u32 s27, s0, 0x80008
+; GFX6-NOHSA-NEXT: s_and_b32 s28, s0, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s29, s1, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s30, s2, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s31, s3, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s33, s4, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s34, s5, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s35, s6, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s36, s7, 0xff
+; GFX6-NOHSA-NEXT: s_bfe_u32 s0, s0, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s1, s1, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s2, s2, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s3, s3, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s4, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s5, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s7, s7, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_u32 s6, s6, 0x80010
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:240
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:208
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s17
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:176
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s16
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:144
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s3
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:112
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:80
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s12
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s36
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s20
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:224
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s35
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s21
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:192
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s34
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:160
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s33
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s23
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:128
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s31
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s24
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:96
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s25
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:64
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s29
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s26
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s27
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v32i8_to_v32i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s3, s4, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s12, s5, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s13, s6, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s14, s7, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s15, s8, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s16, s9, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s17, s10, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s18, s11, 24
+; GFX7-HSA-NEXT: s_bfe_u32 s19, s11, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s20, s10, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s21, s9, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s22, s8, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s23, s7, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s24, s6, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s25, s5, 0x80008
+; GFX7-HSA-NEXT: s_bfe_u32 s2, s4, 0x80008
+; GFX7-HSA-NEXT: s_and_b32 s26, s4, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s27, s5, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s28, s6, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s29, s7, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s30, s8, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s31, s9, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s33, s10, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s34, s11, 0xff
+; GFX7-HSA-NEXT: s_bfe_u32 s35, s4, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s36, s5, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s6, s6, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s7, s7, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s8, s8, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s9, s9, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s10, s10, 0x80010
+; GFX7-HSA-NEXT: s_bfe_u32 s4, s11, 0x80010
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 0xf0
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 0xd0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 0xb0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 0x90
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 0x70
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 0x50
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 48
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 16
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s35
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 0xe0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 0xc0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s33
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 0xa0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s21
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 0x80
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 0x60
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 64
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: s_add_u32 s4, s0, 32
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s5
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v32i8_to_v32i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, v1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[4:11], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s12, s5, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s13, s7, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s14, s9, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s15, s11, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s16, s10, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s17, s8, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s18, s6, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s19, s4, 24
+; GFX8-NOHSA-NEXT: s_and_b32 s2, s4, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v4, 8, s4
+; GFX8-NOHSA-NEXT: s_and_b32 s3, s5, 0xff
+; GFX8-NOHSA-NEXT: s_and_b32 s20, s6, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v6, 8, s6
+; GFX8-NOHSA-NEXT: s_and_b32 s21, s7, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v7, 8, s7
+; GFX8-NOHSA-NEXT: s_and_b32 s22, s8, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v8, 8, s8
+; GFX8-NOHSA-NEXT: s_and_b32 s23, s9, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v9, 8, s9
+; GFX8-NOHSA-NEXT: s_and_b32 s24, s10, 0xff
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v12, 8, s10
+; GFX8-NOHSA-NEXT: s_and_b32 s25, s11, 0xff
+; GFX8-NOHSA-NEXT: s_bfe_u32 s26, s4, 0x80010
+; GFX8-NOHSA-NEXT: s_bfe_u32 s6, s6, 0x80010
+; GFX8-NOHSA-NEXT: s_bfe_u32 s8, s8, 0x80010
+; GFX8-NOHSA-NEXT: s_bfe_u32 s10, s10, 0x80010
+; GFX8-NOHSA-NEXT: s_bfe_u32 s27, s5, 0x80010
+; GFX8-NOHSA-NEXT: s_bfe_u32 s7, s7, 0x80010
+; GFX8-NOHSA-NEXT: s_bfe_u32 s9, s9, 0x80010
+; GFX8-NOHSA-NEXT: s_bfe_u32 s4, s11, 0x80010
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 0xf0
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v5, 8, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 0xb0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 0x70
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s13
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 0xd0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s27
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s12
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 0x90
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s16
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 0x50
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s17
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s18
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 0xe0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s26
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s19
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v13, 8, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 0xc0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s25
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v13
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 0xa0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v12
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v9
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 0x80
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s23
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[9:10], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 0x60
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s22
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v7
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 64
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s21
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[7:8], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s0, 32
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s20
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s1, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s4
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[5:6], v[0:3]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, v4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v32i8_to_v32i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @26, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @22
+; EG-NEXT: ALU 103, @27, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 33, @131, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T13.XYZW, T42.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T14.XYZW, T41.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T15.XYZW, T40.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T16.XYZW, T39.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T17.XYZW, T38.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T18.XYZW, T37.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T36.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T35.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T34.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T21.XYZW, T33.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T22.XYZW, T32.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T23.XYZW, T31.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T24.XYZW, T30.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T25.XYZW, T29.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T26.XYZW, T28.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T27.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 22:
+; EG-NEXT: VTX_READ_128 T12.XYZW, T11.X, 0, #1
+; EG-NEXT: VTX_READ_128 T11.XYZW, T11.X, 16, #1
+; EG-NEXT: ALU clause starting at 26:
+; EG-NEXT: MOV * T11.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 27:
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T13.X, T11.W, literal.x, PV.W,
+; EG-NEXT: LSHR * T13.Z, T11.W, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T13.Y, 0.0,
+; EG-NEXT: BFE_UINT * T14.Z, T11.W, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T14.X, T11.W, literal.x,
+; EG-NEXT: MOV * T14.Y, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T15.X, T11.Z, literal.x, T0.W,
+; EG-NEXT: LSHR * T15.Z, T11.Z, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T15.Y, 0.0,
+; EG-NEXT: BFE_UINT * T16.Z, T11.Z, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T16.X, T11.Z, literal.x,
+; EG-NEXT: MOV * T16.Y, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T17.X, T11.Y, literal.x, T0.W,
+; EG-NEXT: LSHR * T17.Z, T11.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T17.Y, 0.0,
+; EG-NEXT: BFE_UINT * T18.Z, T11.Y, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T18.X, T11.Y, literal.x,
+; EG-NEXT: MOV * T18.Y, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T19.X, T11.X, literal.x, T0.W,
+; EG-NEXT: LSHR * T19.Z, T11.X, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T19.Y, 0.0,
+; EG-NEXT: BFE_UINT * T11.Z, T11.X, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T11.X, T11.X, literal.x,
+; EG-NEXT: MOV * T11.Y, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T20.X, T12.W, literal.x, T0.W,
+; EG-NEXT: LSHR * T20.Z, T12.W, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T20.Y, 0.0,
+; EG-NEXT: BFE_UINT * T21.Z, T12.W, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T21.X, T12.W, literal.x,
+; EG-NEXT: MOV * T21.Y, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T22.X, T12.Z, literal.x, T0.W,
+; EG-NEXT: LSHR * T22.Z, T12.Z, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T22.Y, 0.0,
+; EG-NEXT: BFE_UINT * T23.Z, T12.Z, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T23.X, T12.Z, literal.x,
+; EG-NEXT: MOV * T23.Y, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T24.X, T12.Y, literal.x, T0.W,
+; EG-NEXT: LSHR * T24.Z, T12.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T24.Y, 0.0,
+; EG-NEXT: BFE_UINT * T25.Z, T12.Y, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T25.X, T12.Y, literal.x,
+; EG-NEXT: MOV * T25.Y, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T26.X, T12.X, literal.x, T0.W,
+; EG-NEXT: LSHR * T26.Z, T12.X, literal.y,
+; EG-NEXT: 16(2.242078e-44), 24(3.363116e-44)
+; EG-NEXT: MOV T26.Y, 0.0,
+; EG-NEXT: BFE_UINT * T12.Z, T12.X, literal.x, T0.W,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T12.X, T12.X, literal.x,
+; EG-NEXT: MOV T12.Y, 0.0,
+; EG-NEXT: MOV T13.W, 0.0,
+; EG-NEXT: MOV * T14.W, 0.0,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: MOV T15.W, 0.0,
+; EG-NEXT: MOV * T16.W, 0.0,
+; EG-NEXT: MOV T17.W, 0.0,
+; EG-NEXT: MOV * T18.W, 0.0,
+; EG-NEXT: MOV T19.W, 0.0,
+; EG-NEXT: MOV * T11.W, 0.0,
+; EG-NEXT: MOV T20.W, 0.0,
+; EG-NEXT: MOV * T21.W, 0.0,
+; EG-NEXT: MOV T22.W, 0.0,
+; EG-NEXT: MOV * T23.W, 0.0,
+; EG-NEXT: MOV T24.W, 0.0,
+; EG-NEXT: MOV * T25.W, 0.0,
+; EG-NEXT: MOV T26.W, 0.0,
+; EG-NEXT: MOV * T12.W, 0.0,
+; EG-NEXT: LSHR T27.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T28.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T29.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T30.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR * T31.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 131:
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 80(1.121039e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T32.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: LSHR T33.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43)
+; EG-NEXT: LSHR T34.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 128(1.793662e-43)
+; EG-NEXT: LSHR T35.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 144(2.017870e-43)
+; EG-NEXT: LSHR T36.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 160(2.242078e-43)
+; EG-NEXT: LSHR T37.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 176(2.466285e-43)
+; EG-NEXT: LSHR T38.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 192(2.690493e-43)
+; EG-NEXT: LSHR T39.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 208(2.914701e-43)
+; EG-NEXT: LSHR T40.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 224(3.138909e-43)
+; EG-NEXT: LSHR T41.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 240(3.363116e-43)
+; EG-NEXT: LSHR * T42.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <32 x i8>, ptr addrspace(4) %in
%ext = zext <32 x i8> %load to <32 x i64>
store <32 x i64> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v32i8_to_v32i64:
-
-; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
-; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v32i8_to_v32i64:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_lshr_b32 s10, s7, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s34, s7, 8
+; GFX6-NOHSA-NEXT: s_mov_b32 s50, s7
+; GFX6-NOHSA-NEXT: s_lshr_b32 s12, s6, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s14, s6, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s16, s6, 8
+; GFX6-NOHSA-NEXT: s_lshr_b32 s18, s5, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s20, s5, 8
+; GFX6-NOHSA-NEXT: s_mov_b32 s48, s5
+; GFX6-NOHSA-NEXT: s_lshr_b32 s22, s4, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s24, s4, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s26, s4, 8
+; GFX6-NOHSA-NEXT: s_lshr_b32 s28, s3, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s30, s3, 8
+; GFX6-NOHSA-NEXT: s_mov_b32 s40, s3
+; GFX6-NOHSA-NEXT: s_lshr_b32 s36, s2, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s38, s2, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s42, s2, 8
+; GFX6-NOHSA-NEXT: s_lshr_b32 s44, s1, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s46, s1, 8
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[52:53], s[48:49], 0x80000
+; GFX6-NOHSA-NEXT: s_mov_b32 s54, s1
+; GFX6-NOHSA-NEXT: s_lshr_b32 s56, s0, 16
+; GFX6-NOHSA-NEXT: s_lshr_b32 s58, s0, 24
+; GFX6-NOHSA-NEXT: s_lshr_b32 s60, s0, 8
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[48:49], s[0:1], 0x80000
+; GFX6-NOHSA-NEXT: s_ashr_i64 s[0:1], s[0:1], 56
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[62:63], s[2:3], 0x80000
+; GFX6-NOHSA-NEXT: s_ashr_i64 s[64:65], s[4:5], 56
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[66:67], s[6:7], 0x80000
+; GFX6-NOHSA-NEXT: s_ashr_i64 s[6:7], s[6:7], 56
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[4:5], s[4:5], 0x80000
+; GFX6-NOHSA-NEXT: s_ashr_i64 s[2:3], s[2:3], 56
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s50
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s51
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s66
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v9, s67
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s64
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v13, s65
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v14, s52
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v15, s53
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v18, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v19, s5
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[4:5], s[10:11], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[34:35], 0x80000
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:240
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[4:5], s[54:55], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[6:7], s[40:41], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[34:35], s[60:61], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[40:41], s[58:59], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[50:51], s[56:57], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[24:25], s[24:25], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[14:15], s[14:15], 0x80000
+; GFX6-NOHSA-NEXT: s_bfe_i64 s[12:13], s[12:13], 0x80000
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:224
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(1)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:208
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s16
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s17
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[8:11], 0 offset:192
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s18
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s19
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[10:13], off, s[8:11], 0 offset:176
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v8, s62
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v9, s63
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v16, s20
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v17, s21
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[14:17], off, s[8:11], 0 offset:160
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(1)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s22
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s23
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s24
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v13, s25
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[10:13], off, s[8:11], 0 offset:144
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v12, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v13, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v20, s26
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v21, s27
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[18:21], off, s[8:11], 0 offset:128
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v14, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v15, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:112
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s48
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s49
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v6, s30
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v7, s31
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[4:7], off, s[8:11], 0 offset:96
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s36
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s37
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s38
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s39
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[2:5], off, s[8:11], 0 offset:80
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s42
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s43
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[8:11], off, s[8:11], 0 offset:64
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v10, s44
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v11, s45
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[10:13], off, s[8:11], 0 offset:48
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v16, s46
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v17, s47
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[14:17], off, s[8:11], 0 offset:32
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s50
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s51
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v4, s40
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v5, s41
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[2:5], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s34
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s35
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v32i8_to_v32i64:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_lshr_b32 s14, s7, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s38, s7, 8
+; GFX7-HSA-NEXT: s_mov_b32 s40, s7
+; GFX7-HSA-NEXT: s_lshr_b32 s42, s6, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s44, s6, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s46, s6, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s48, s5, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s50, s5, 8
+; GFX7-HSA-NEXT: s_mov_b32 s52, s5
+; GFX7-HSA-NEXT: s_lshr_b32 s54, s4, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s56, s4, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s58, s4, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s36, s3, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s30, s3, 8
+; GFX7-HSA-NEXT: s_mov_b32 s34, s3
+; GFX7-HSA-NEXT: s_lshr_b32 s28, s2, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s26, s2, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s22, s2, 8
+; GFX7-HSA-NEXT: s_lshr_b32 s18, s1, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s60, s1, 8
+; GFX7-HSA-NEXT: s_mov_b32 s16, s1
+; GFX7-HSA-NEXT: s_lshr_b32 s62, s0, 16
+; GFX7-HSA-NEXT: s_lshr_b32 s64, s0, 24
+; GFX7-HSA-NEXT: s_lshr_b32 s66, s0, 8
+; GFX7-HSA-NEXT: s_bfe_i64 s[12:13], s[2:3], 0x80000
+; GFX7-HSA-NEXT: s_ashr_i64 s[20:21], s[2:3], 56
+; GFX7-HSA-NEXT: s_bfe_i64 s[24:25], s[4:5], 0x80000
+; GFX7-HSA-NEXT: s_ashr_i64 s[68:69], s[4:5], 56
+; GFX7-HSA-NEXT: s_ashr_i64 s[2:3], s[6:7], 56
+; GFX7-HSA-NEXT: s_bfe_i64 s[4:5], s[14:15], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[10:11], s[0:1], 0x80000
+; GFX7-HSA-NEXT: s_ashr_i64 s[0:1], s[0:1], 56
+; GFX7-HSA-NEXT: s_bfe_i64 s[70:71], s[6:7], 0x80000
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: s_bfe_i64 s[2:3], s[66:67], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[4:5], s[64:65], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[6:7], s[62:63], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[16:17], s[16:17], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[14:15], s[60:61], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[18:19], s[18:19], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[58:59], s[58:59], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[56:57], s[56:57], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[54:55], s[54:55], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[52:53], s[52:53], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[50:51], s[50:51], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[48:49], s[48:49], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x80000
+; GFX7-HSA-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000
+; GFX7-HSA-NEXT: s_add_u32 s60, s8, 0xf0
+; GFX7-HSA-NEXT: s_addc_u32 s61, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s38
+; GFX7-HSA-NEXT: s_add_u32 s38, s8, 0xe0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s39
+; GFX7-HSA-NEXT: s_addc_u32 s39, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v24, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v25, s39
+; GFX7-HSA-NEXT: s_add_u32 s38, s8, 0xd0
+; GFX7-HSA-NEXT: s_addc_u32 s39, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v26, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v27, s39
+; GFX7-HSA-NEXT: s_add_u32 s38, s8, 0xc0
+; GFX7-HSA-NEXT: s_addc_u32 s39, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v28, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v29, s39
+; GFX7-HSA-NEXT: s_add_u32 s38, s8, 0xb0
+; GFX7-HSA-NEXT: s_addc_u32 s39, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v30, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v31, s39
+; GFX7-HSA-NEXT: s_add_u32 s38, s8, 0xa0
+; GFX7-HSA-NEXT: s_addc_u32 s39, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v32, s38
+; GFX7-HSA-NEXT: v_mov_b32_e32 v33, s39
+; GFX7-HSA-NEXT: s_add_u32 s38, s8, 0x90
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s60
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s40
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s41
+; GFX7-HSA-NEXT: s_addc_u32 s39, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s61
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s42
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s43
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s44
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s45
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[24:25], v[4:7]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v12, s70
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s24
+; GFX7-HSA-NEXT: s_add_u32 s24, s8, 0x80
+; GFX7-HSA-NEXT: v_mov_b32_e32 v13, s71
+; GFX7-HSA-NEXT: v_mov_b32_e32 v14, s46
+; GFX7-HSA-NEXT: v_mov_b32_e32 v15, s47
+; GFX7-HSA-NEXT: v_mov_b32_e32 v16, s48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v17, s49
+; GFX7-HSA-NEXT: v_mov_b32_e32 v18, s68
+; GFX7-HSA-NEXT: v_mov_b32_e32 v19, s69
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[22:23], v[0:3]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[26:27], v[8:11]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s56
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s25
+; GFX7-HSA-NEXT: v_mov_b32_e32 v8, s38
+; GFX7-HSA-NEXT: s_addc_u32 s25, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v10, s24
+; GFX7-HSA-NEXT: v_mov_b32_e32 v20, s52
+; GFX7-HSA-NEXT: v_mov_b32_e32 v21, s53
+; GFX7-HSA-NEXT: v_mov_b32_e32 v22, s50
+; GFX7-HSA-NEXT: v_mov_b32_e32 v23, s51
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s54
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s55
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s57
+; GFX7-HSA-NEXT: v_mov_b32_e32 v9, s39
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[28:29], v[12:15]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v6, s58
+; GFX7-HSA-NEXT: v_mov_b32_e32 v7, s59
+; GFX7-HSA-NEXT: v_mov_b32_e32 v11, s25
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[30:31], v[16:19]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[32:33], v[20:23]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[8:9], v[0:3]
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[10:11], v[4:7]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s20
+; GFX7-HSA-NEXT: s_add_u32 s20, s8, 0x70
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s21
+; GFX7-HSA-NEXT: s_addc_u32 s21, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s36
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s37
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s21
+; GFX7-HSA-NEXT: s_add_u32 s20, s8, 0x60
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s21, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s34
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s35
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s30
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s31
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s21
+; GFX7-HSA-NEXT: s_add_u32 s20, s8, 0x50
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_addc_u32 s21, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s28
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s29
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s26
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s27
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s21
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s12
+; GFX7-HSA-NEXT: s_add_u32 s12, s8, 64
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: s_addc_u32 s13, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s22
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s23
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_nop 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-HSA-NEXT: s_add_u32 s0, s8, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: s_add_u32 s0, s8, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: s_add_u32 s0, s8, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s15
+; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v32i8_to_v32i64:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s28, s7, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s30, s6, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s34, s6, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s36, s5, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s38, s4, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s40, s4, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s42, s3, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s44, s2, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s46, s2, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s26, s1, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s22, s0, 16
+; GFX8-NOHSA-NEXT: s_lshr_b32 s20, s0, 24
+; GFX8-NOHSA-NEXT: s_mov_b32 s48, s7
+; GFX8-NOHSA-NEXT: s_mov_b32 s50, s5
+; GFX8-NOHSA-NEXT: s_mov_b32 s52, s3
+; GFX8-NOHSA-NEXT: s_mov_b32 s54, s1
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v5, 8, s7
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v1, 8, s6
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s5
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v4, 8, s4
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v8, 8, s3
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v9, 8, s2
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v6, 8, s1
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v2, 8, s0
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[10:11], s[0:1], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[12:13], s[2:3], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[14:15], s[4:5], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[16:17], s[6:7], 0x80000
+; GFX8-NOHSA-NEXT: s_ashr_i64 s[18:19], s[0:1], 56
+; GFX8-NOHSA-NEXT: s_ashr_i64 s[24:25], s[2:3], 56
+; GFX8-NOHSA-NEXT: s_ashr_i64 s[56:57], s[4:5], 56
+; GFX8-NOHSA-NEXT: s_ashr_i64 s[58:59], s[6:7], 56
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[0:1], s[54:55], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[2:3], s[52:53], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[4:5], s[50:51], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[6:7], s[48:49], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[20:21], s[20:21], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[22:23], s[22:23], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[26:27], s[26:27], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[46:47], s[46:47], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[44:45], s[44:45], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[42:43], s[42:43], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[40:41], s[40:41], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[38:39], s[38:39], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[36:37], s[36:37], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[34:35], s[34:35], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[30:31], s[30:31], 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i64 s[28:29], s[28:29], 0x80000
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s28
+; GFX8-NOHSA-NEXT: s_add_u32 s28, s8, 0xf0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s29
+; GFX8-NOHSA-NEXT: s_addc_u32 s29, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s28
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s58
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s59
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s29
+; GFX8-NOHSA-NEXT: s_add_u32 s28, s8, 0xd0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
+; GFX8-NOHSA-NEXT: s_addc_u32 s29, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s28
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s30
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s31
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s34
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s35
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s29
+; GFX8-NOHSA-NEXT: s_add_u32 s28, s8, 0xb0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
+; GFX8-NOHSA-NEXT: s_addc_u32 s29, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s28
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s36
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s37
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s56
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s57
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s29
+; GFX8-NOHSA-NEXT: s_add_u32 s28, s8, 0x90
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
+; GFX8-NOHSA-NEXT: s_addc_u32 s29, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s28
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s38
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s39
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s40
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s41
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s29
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
+; GFX8-NOHSA-NEXT: v_bfe_i32 v10, v9, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s24
+; GFX8-NOHSA-NEXT: s_add_u32 s24, s8, 0x70
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s25
+; GFX8-NOHSA-NEXT: s_addc_u32 s25, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s42
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s43
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s25
+; GFX8-NOHSA-NEXT: s_add_u32 s24, s8, 0x50
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
+; GFX8-NOHSA-NEXT: s_addc_u32 s25, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s44
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s45
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s46
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s47
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s25
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
+; GFX8-NOHSA-NEXT: v_bfe_i32 v18, v5, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s18
+; GFX8-NOHSA-NEXT: s_add_u32 s18, s8, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s19
+; GFX8-NOHSA-NEXT: s_addc_u32 s19, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s26
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s27
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s19
+; GFX8-NOHSA-NEXT: s_add_u32 s18, s8, 16
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
+; GFX8-NOHSA-NEXT: s_addc_u32 s19, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s22
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s23
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v14, s20
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s21
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s19
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[16:17], v[12:15]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s6
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s8, 0xe0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s7
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s9, 0
+; GFX8-NOHSA-NEXT: v_bfe_i32 v14, v8, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s7
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v19, 31, v18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s6
+; GFX8-NOHSA-NEXT: s_add_u32 s6, s8, 0xc0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[16:19]
+; GFX8-NOHSA-NEXT: v_bfe_i32 v22, v1, 0, 8
+; GFX8-NOHSA-NEXT: v_bfe_i32 v18, v4, 0, 8
+; GFX8-NOHSA-NEXT: s_addc_u32 s7, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s6
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v23, 31, v22
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v20, s16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v21, s17
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s7
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[20:23]
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v19, 31, v18
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v20, s4
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s8, 0xa0
+; GFX8-NOHSA-NEXT: v_bfe_i32 v22, v0, 0, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v21, s5
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v23, 31, v22
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: s_add_u32 s4, s8, 0x80
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[20:23]
+; GFX8-NOHSA-NEXT: s_addc_u32 s5, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v17, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s8, 0x60
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[16:19]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v15, 31, v14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s8, 64
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[12:15]
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v11, 31, v10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s12
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 32
+; GFX8-NOHSA-NEXT: v_bfe_i32 v6, v6, 0, 8
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[8:11]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v7, 31, v6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[0:1], v[4:7]
+; GFX8-NOHSA-NEXT: v_ashrrev_i32_e32 v3, 31, v2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s10
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s11
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v32i8_to_v32i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @26, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @22
+; EG-NEXT: ALU 84, @27, KC0[CB0:0-32], KC1[]
+; EG-NEXT: ALU 71, @112, KC0[], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T41.XYZW, T42.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T26.XYZW, T31.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T40.XYZW, T30.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T11.XYZW, T25.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T39.XYZW, T24.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T27.XYZW, T23.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T22.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T28.XYZW, T21.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T37.XYZW, T20.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T29.XYZW, T19.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T35.XYZW, T18.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T33.XYZW, T17.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T34.XYZW, T16.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T38.XYZW, T15.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T32.XYZW, T14.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T36.XYZW, T13.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 22:
+; EG-NEXT: VTX_READ_128 T12.XYZW, T11.X, 0, #1
+; EG-NEXT: VTX_READ_128 T11.XYZW, T11.X, 16, #1
+; EG-NEXT: ALU clause starting at 26:
+; EG-NEXT: MOV * T11.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 27:
+; EG-NEXT: LSHR T13.X, KC0[2].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 16(2.242078e-44)
+; EG-NEXT: LSHR T14.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 32(4.484155e-44)
+; EG-NEXT: LSHR T15.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 48(6.726233e-44)
+; EG-NEXT: LSHR T16.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 64(8.968310e-44)
+; EG-NEXT: LSHR T17.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 80(1.121039e-43)
+; EG-NEXT: LSHR T18.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 96(1.345247e-43)
+; EG-NEXT: LSHR T19.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 112(1.569454e-43)
+; EG-NEXT: LSHR T20.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 128(1.793662e-43)
+; EG-NEXT: LSHR T21.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 144(2.017870e-43)
+; EG-NEXT: LSHR T22.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 160(2.242078e-43)
+; EG-NEXT: LSHR T23.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 176(2.466285e-43)
+; EG-NEXT: LSHR T24.X, PV.W, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,
+; EG-NEXT: 2(2.802597e-45), 192(2.690493e-43)
+; EG-NEXT: LSHR * T25.X, PV.W, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: BFE_INT * T26.X, T11.W, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T27.X, T11.Y, 0.0, literal.x,
+; EG-NEXT: ASHR T26.Y, PV.X, literal.y,
+; EG-NEXT: LSHR * T0.W, T11.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: BFE_INT T28.X, T11.X, 0.0, literal.x,
+; EG-NEXT: ASHR T27.Y, PV.X, literal.y,
+; EG-NEXT: BFE_INT T26.Z, PV.W, 0.0, literal.x,
+; EG-NEXT: LSHR * T0.W, T11.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: BFE_INT T29.X, T12.W, 0.0, literal.x,
+; EG-NEXT: ASHR T28.Y, PV.X, literal.y,
+; EG-NEXT: BFE_INT T27.Z, PV.W, 0.0, literal.x,
+; EG-NEXT: LSHR T0.W, T11.X, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.z,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 208(2.914701e-43), 0(0.000000e+00)
+; EG-NEXT: LSHR T30.X, PS, literal.x,
+; EG-NEXT: ASHR T29.Y, PV.X, literal.y,
+; EG-NEXT: BFE_INT T28.Z, PV.W, 0.0, literal.z,
+; EG-NEXT: LSHR T0.W, T12.W, literal.z,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
+; EG-NEXT: 8(1.121039e-44), 224(3.138909e-43)
+; EG-NEXT: LSHR T31.X, PS, literal.x,
+; EG-NEXT: BFE_INT T29.Z, PV.W, 0.0, literal.y,
+; EG-NEXT: ADD_INT T0.W, KC0[2].Y, literal.z,
+; EG-NEXT: ASHR * T32.W, T12.X, literal.w,
+; EG-NEXT: 2(2.802597e-45), 8(1.121039e-44)
+; EG-NEXT: 240(3.363116e-43), 31(4.344025e-44)
+; EG-NEXT: BFE_INT T33.X, T12.Z, 0.0, literal.x,
+; EG-NEXT: LSHR T0.Y, T11.Z, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: ASHR T32.Z, T12.X, literal.y,
+; EG-NEXT: LSHR T1.W, T12.X, literal.z,
+; EG-NEXT: ASHR * T34.W, T12.Y, literal.w,
+; EG-NEXT: 8(1.121039e-44), 24(3.363116e-44)
+; EG-NEXT: 16(2.242078e-44), 31(4.344025e-44)
+; EG-NEXT: BFE_INT T32.X, PV.W, 0.0, literal.x,
+; EG-NEXT: ASHR T33.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T34.Z, T12.Y, literal.z,
+; EG-NEXT: LSHR T1.W, T12.Z, literal.x,
+; EG-NEXT: LSHR * T2.W, T12.Y, literal.w,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 24(3.363116e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT * T34.X, PS, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 112:
+; EG-NEXT: ASHR T32.Y, T32.X, literal.x,
+; EG-NEXT: BFE_INT T33.Z, T1.W, 0.0, literal.y,
+; EG-NEXT: LSHR T1.W, T11.W, literal.z, BS:VEC_120/SCL_212
+; EG-NEXT: ASHR * T35.W, T12.Z, literal.x,
+; EG-NEXT: 31(4.344025e-44), 8(1.121039e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T36.X, T12.X, 0.0, literal.x,
+; EG-NEXT: ASHR T34.Y, T34.X, literal.y, BS:VEC_120/SCL_212
+; EG-NEXT: ASHR T35.Z, T12.Z, literal.z,
+; EG-NEXT: LSHR T2.W, T12.Z, literal.w,
+; EG-NEXT: ASHR * T37.W, T12.W, literal.y,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 24(3.363116e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T35.X, PV.W, 0.0, literal.x,
+; EG-NEXT: ASHR T36.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T37.Z, T12.W, literal.z,
+; EG-NEXT: LSHR T2.W, T12.X, literal.x,
+; EG-NEXT: LSHR * T3.W, T12.W, literal.w,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 24(3.363116e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T37.X, PS, 0.0, literal.x,
+; EG-NEXT: ASHR T35.Y, PV.X, literal.y,
+; EG-NEXT: BFE_INT T36.Z, PV.W, 0.0, literal.x,
+; EG-NEXT: LSHR T2.W, T11.Z, literal.z,
+; EG-NEXT: ASHR * T12.W, T11.X, literal.y,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T38.X, T12.Y, 0.0, literal.x,
+; EG-NEXT: ASHR T37.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T12.Z, T11.X, literal.z,
+; EG-NEXT: LSHR T3.W, T11.X, literal.w,
+; EG-NEXT: ASHR * T39.W, T11.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 24(3.363116e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T12.X, PV.W, 0.0, literal.x,
+; EG-NEXT: ASHR T38.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T39.Z, T11.Y, literal.z,
+; EG-NEXT: LSHR T3.W, T12.Y, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: LSHR * T4.W, T11.Y, literal.w,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 24(3.363116e-44), 16(2.242078e-44)
+; EG-NEXT: BFE_INT T39.X, PS, 0.0, literal.x,
+; EG-NEXT: ASHR T12.Y, PV.X, literal.y,
+; EG-NEXT: BFE_INT T38.Z, PV.W, 0.0, literal.x,
+; EG-NEXT: ASHR T36.W, T36.Z, literal.y,
+; EG-NEXT: ASHR * T40.W, T11.Z, literal.y,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: BFE_INT T11.X, T11.Z, 0.0, literal.x,
+; EG-NEXT: ASHR T39.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T40.Z, T11.Z, literal.z,
+; EG-NEXT: ASHR T38.W, PV.Z, literal.y,
+; EG-NEXT: ASHR * T41.W, T11.W, literal.y,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T40.X, T2.W, 0.0, literal.x,
+; EG-NEXT: ASHR T11.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T41.Z, T11.W, literal.z, BS:VEC_120/SCL_212
+; EG-NEXT: ASHR T33.W, T33.Z, literal.y,
+; EG-NEXT: ASHR * T29.W, T29.Z, literal.y,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T41.X, T1.W, 0.0, literal.x,
+; EG-NEXT: ASHR T40.Y, PV.X, literal.y,
+; EG-NEXT: BFE_INT T11.Z, T0.Y, 0.0, literal.x,
+; EG-NEXT: ASHR T28.W, T28.Z, literal.y,
+; EG-NEXT: ASHR * T27.W, T27.Z, literal.y,
+; EG-NEXT: 8(1.121039e-44), 31(4.344025e-44)
+; EG-NEXT: LSHR T42.X, T0.W, literal.x,
+; EG-NEXT: ASHR T41.Y, PV.X, literal.y,
+; EG-NEXT: ASHR T11.W, PV.Z, literal.y,
+; EG-NEXT: ASHR * T26.W, T26.Z, literal.y,
+; EG-NEXT: 2(2.802597e-45), 31(4.344025e-44)
%load = load <32 x i8>, ptr addrspace(4) %in
%ext = sext <32 x i8> %load to <32 x i64>
store <32 x i64> %ext, ptr addrspace(1) %out
@@ -738,212 +7585,3033 @@ define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(ptr addrspace(1) %o
; ret void
; }
-; FUNC-LABEL: {{^}}constant_zextload_i8_to_i16:
-; GCN-NOHSA: buffer_load_ubyte v[[VAL:[0-9]+]],
-; GCN-NOHSA: buffer_store_short v[[VAL]]
-
-; GCN-HSA: flat_load_ubyte v[[VAL:[0-9]+]],
-; GCN-HSA: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[VAL]]
define amdgpu_kernel void @constant_zextload_i8_to_i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_i8_to_i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: buffer_store_short v0, off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_i8_to_i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: flat_store_short v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_i8_to_i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: flat_store_short v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_i8_to_i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: AND_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL T0.X, T0.X, PV.W,
+; EG-NEXT: LSHL * T0.W, literal.x, PV.W,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%a = load i8, ptr addrspace(4) %in
%ext = zext i8 %a to i16
store i16 %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_i8_to_i16:
-; GCN-NOHSA: buffer_load_sbyte v[[VAL:[0-9]+]],
-; GCN-HSA: flat_load_sbyte v[[VAL:[0-9]+]],
-
-; GCN-NOHSA: buffer_store_short v[[VAL]]
-; GCN-HSA: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[VAL]]
-
-; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_i8_to_i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_i8_to_i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_sbyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: buffer_store_short v0, off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_i8_to_i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_sbyte v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: flat_store_short v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_i8_to_i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_sbyte v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: flat_store_short v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_i8_to_i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T0.W, T0.X, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 3(4.203895e-45)
+; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
+; EG-NEXT: LSHL * T1.W, PS, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
+; EG-NEXT: LSHL T0.X, PV.W, PS,
+; EG-NEXT: LSHL * T0.W, literal.x, PS,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%a = load i8, ptr addrspace(4) %in
%ext = sext i8 %a to i16
store i16 %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v1i8_to_v1i16:
define amdgpu_kernel void @constant_zextload_v1i8_to_v1i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v1i8_to_v1i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ubyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: buffer_store_short v0, off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v1i8_to_v1i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: flat_store_short v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v1i8_to_v1i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ubyte v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: flat_store_short v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v1i8_to_v1i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 10, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: AND_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL T0.X, T0.X, PV.W,
+; EG-NEXT: LSHL * T0.W, literal.x, PV.W,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <1 x i8>, ptr addrspace(4) %in
%ext = zext <1 x i8> %load to <1 x i16>
store <1 x i16> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v1i8_to_v1i16:
-
-; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
define amdgpu_kernel void @constant_sextload_v1i8_to_v1i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v1i8_to_v1i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_sbyte v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: buffer_store_short v0, off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v1i8_to_v1i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_sbyte v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: flat_store_short v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v1i8_to_v1i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_sbyte v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: flat_store_short v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v1i8_to_v1i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 12, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_8 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: BFE_INT T0.W, T0.X, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 3(4.203895e-45)
+; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
+; EG-NEXT: LSHL * T1.W, PS, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
+; EG-NEXT: LSHL T0.X, PV.W, PS,
+; EG-NEXT: LSHL * T0.W, literal.x, PS,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <1 x i8>, ptr addrspace(4) %in
%ext = sext <1 x i8> %load to <1 x i16>
store <1 x i16> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v2i8_to_v2i16:
-
-; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v2i8_to_v2i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v2i8_to_v2i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: v_lshlrev_b32_e32 v1, 8, v0
+; GFX6-NOHSA-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NOHSA-NEXT: v_and_b32_e32 v0, 0xff00ff, v0
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v2i8_to_v2i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ushort v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: v_lshlrev_b32_e32 v3, 8, v2
+; GFX7-HSA-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX7-HSA-NEXT: v_and_b32_e32 v2, 0xff00ff, v2
+; GFX7-HSA-NEXT: flat_store_dword v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v2i8_to_v2i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, 0xffff
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ushort v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e32 v4, 8, v2
+; GFX8-NOHSA-NEXT: v_and_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v3, 16, v4
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX8-NOHSA-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v2i8_to_v2i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.X, T6.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_16 T5.X, T5.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T5.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: LSHL * T0.W, T5.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
+; EG-NEXT: AND_INT * T1.W, T5.X, literal.y,
+; EG-NEXT: 16711680(2.341805e-38), 255(3.573311e-43)
+; EG-NEXT: OR_INT T5.X, PS, PV.W,
+; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <2 x i8>, ptr addrspace(4) %in
%ext = zext <2 x i8> %load to <2 x i16>
store <2 x i16> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v2i8_to_v2i16:
-
-; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
define amdgpu_kernel void @constant_sextload_v2i8_to_v2i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v2i8_to_v2i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s6, -1
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, s7
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_mov_b32 s8, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s9, s3
+; GFX6-NOHSA-NEXT: buffer_load_ushort v0, off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_mov_b32 s4, s0
+; GFX6-NOHSA-NEXT: s_mov_b32 s5, s1
+; GFX6-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NOHSA-NEXT: v_bfe_i32 v1, v0, 8, 8
+; GFX6-NOHSA-NEXT: v_bfe_i32 v0, v0, 0, 8
+; GFX6-NOHSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX6-NOHSA-NEXT: v_and_b32_e32 v0, 0xffff, v0
+; GFX6-NOHSA-NEXT: v_or_b32_e32 v0, v0, v1
+; GFX6-NOHSA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v2i8_to_v2i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: flat_load_ushort v2, v[0:1]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt vmcnt(0)
+; GFX7-HSA-NEXT: v_bfe_i32 v3, v2, 8, 8
+; GFX7-HSA-NEXT: v_bfe_i32 v2, v2, 0, 8
+; GFX7-HSA-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX7-HSA-NEXT: v_and_b32_e32 v2, 0xffff, v2
+; GFX7-HSA-NEXT: v_or_b32_e32 v2, v2, v3
+; GFX7-HSA-NEXT: flat_store_dword v[0:1], v2
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v2i8_to_v2i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, 0xffff
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NOHSA-NEXT: flat_load_ushort v2, v[0:1]
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NOHSA-NEXT: v_and_b32_sdwa v3, v3, sext(v2) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e32 v2, 8, v2
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v2, v3, v2
+; GFX8-NOHSA-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v2i8_to_v2i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 16, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T5.X, T6.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_16 T5.X, T5.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.Y, T2.X,
+; EG-NEXT: MOV * T5.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: AND_INT T0.W, T5.X, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 65535(9.183409e-41), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T2.X, PV.W,
+; EG-NEXT: MOV * T0.Y, PV.X,
+; EG-NEXT: LSHR * T1.W, PV.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.Z, T0.W, 0.0, literal.x,
+; EG-NEXT: BFE_INT * T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: LSHL T0.W, PV.W, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Z, literal.y,
+; EG-NEXT: 16(2.242078e-44), 65535(9.183409e-41)
+; EG-NEXT: OR_INT T5.X, PS, PV.W,
+; EG-NEXT: LSHR * T6.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%load = load <2 x i8>, ptr addrspace(4) %in
%ext = sext <2 x i8> %load to <2 x i16>
store <2 x i16> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v4i8_to_v4i16:
-
-; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v4i8_to_v4i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v4i8_to_v4i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s2, 0xff00
+; GFX6-NOHSA-NEXT: s_lshr_b32 s5, s2, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s6, s2, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s2, s2, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s5, s5, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s4, s4, 8
+; GFX6-NOHSA-NEXT: s_or_b32 s5, s6, s5
+; GFX6-NOHSA-NEXT: s_or_b32 s4, s2, s4
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v4i8_to_v4i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_and_b32 s0, s2, 0xff00
+; GFX7-HSA-NEXT: s_lshr_b32 s1, s2, 8
+; GFX7-HSA-NEXT: s_bfe_u32 s3, s2, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s2, s2, 0xff
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xff0000
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 8
+; GFX7-HSA-NEXT: s_or_b32 s1, s3, s1
+; GFX7-HSA-NEXT: s_or_b32 s0, s2, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s1
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v4i8_to_v4i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v2, 8, s2
+; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s2, 24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NOHSA-NEXT: s_and_b32 s1, s2, 0xff
+; GFX8-NOHSA-NEXT: v_alignbit_b32 v3, s0, v3, 16
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NOHSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v3
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v2, s1, v2
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v4i8_to_v4i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 31, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XY, T7.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.Y, T4.X,
+; EG-NEXT: MOV * T7.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: AND_INT T0.W, T7.X, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 255(3.573311e-43), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T0.W, T7.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, T5.X,
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T0.W, T7.X, literal.x, PV.W,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T5.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T7.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: LSHR T7.X, KC0[2].Y, literal.x,
+; EG-NEXT: OR_INT * T8.Y, PV.W, PS,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T5.X, PV.Y,
+; EG-NEXT: MOV * T8.X, T4.X,
%load = load <4 x i8>, ptr addrspace(4) %in
%ext = zext <4 x i8> %load to <4 x i16>
store <4 x i16> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v4i8_to_v4i16:
-
-; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
define amdgpu_kernel void @constant_sextload_v4i8_to_v4i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v4i8_to_v4i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s4, s2, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s5, s2, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s6, s2, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX6-NOHSA-NEXT: s_lshl_b32 s4, s4, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s5, s5, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s6, s6, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX6-NOHSA-NEXT: s_or_b32 s4, s5, s4
+; GFX6-NOHSA-NEXT: s_or_b32 s5, s2, s6
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s4
+; GFX6-NOHSA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v4i8_to_v4i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s0, s2, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s1, s2, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s3, s2, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX7-HSA-NEXT: s_lshl_b32 s3, s3, 16
+; GFX7-HSA-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s0, s1, s0
+; GFX7-HSA-NEXT: s_or_b32 s1, s2, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX7-HSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v4i8_to_v4i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dword s2, s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s2, 16
+; GFX8-NOHSA-NEXT: s_ashr_i32 s1, s2, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s0, 0x80000
+; GFX8-NOHSA-NEXT: s_bfe_i32 s3, s2, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v2, 8, s2
+; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s1, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: s_and_b32 s2, 0xffff, s3
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NOHSA-NEXT: s_or_b32 s0, s0, s1
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v2, s2, v2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v4i8_to_v4i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 37, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T8.XY, T7.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T7.X, T7.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.Y, T4.X,
+; EG-NEXT: MOV * T7.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: BFE_INT * T0.W, T7.X, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 65535(9.183409e-41), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T7.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, T5.X,
+; EG-NEXT: LSHR * T0.W, T7.X, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T5.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T7.X, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: LSHR T7.X, KC0[2].Y, literal.x,
+; EG-NEXT: OR_INT * T8.Y, PV.W, PS,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T5.X, PV.Y,
+; EG-NEXT: MOV * T8.X, T4.X,
%load = load <4 x i8>, ptr addrspace(4) %in
%ext = sext <4 x i8> %load to <4 x i16>
store <4 x i16> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v8i8_to_v8i16:
-
-; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v8i8_to_v8i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v8i8_to_v8i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_and_b32 s2, s4, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s6, s5, 0xff00
+; GFX6-NOHSA-NEXT: s_lshr_b32 s7, s5, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s8, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s5, s5, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s9, s4, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s10, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s7, s7, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s6, s6, 8
+; GFX6-NOHSA-NEXT: s_and_b32 s9, s9, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s2, s2, 8
+; GFX6-NOHSA-NEXT: s_or_b32 s7, s8, s7
+; GFX6-NOHSA-NEXT: s_or_b32 s5, s5, s6
+; GFX6-NOHSA-NEXT: s_or_b32 s6, s10, s9
+; GFX6-NOHSA-NEXT: s_or_b32 s4, s4, s2
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v8i8_to_v8i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_and_b32 s1, s3, 0xff00
+; GFX7-HSA-NEXT: s_lshr_b32 s4, s3, 8
+; GFX7-HSA-NEXT: s_bfe_u32 s5, s3, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s3, s3, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s1, 8
+; GFX7-HSA-NEXT: s_and_b32 s0, s2, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s4, s4, 0xff0000
+; GFX7-HSA-NEXT: s_or_b32 s1, s3, s1
+; GFX7-HSA-NEXT: s_lshr_b32 s3, s2, 8
+; GFX7-HSA-NEXT: s_or_b32 s4, s5, s4
+; GFX7-HSA-NEXT: s_and_b32 s3, s3, 0xff0000
+; GFX7-HSA-NEXT: s_bfe_u32 s5, s2, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s2, s2, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 8
+; GFX7-HSA-NEXT: s_or_b32 s3, s5, s3
+; GFX7-HSA-NEXT: s_or_b32 s0, s2, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s4
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v8i8_to_v8i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s2, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s1, s3, 24
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v3, 8, s2
+; GFX8-NOHSA-NEXT: s_bfe_u32 s4, s3, 0x80010
+; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s1, 16
+; GFX8-NOHSA-NEXT: v_alignbit_b32 v0, s0, v0, 16
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v2, 8, s3
+; GFX8-NOHSA-NEXT: s_or_b32 s0, s4, s1
+; GFX8-NOHSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v0
+; GFX8-NOHSA-NEXT: s_and_b32 s1, s2, 0xff
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v0, 16, v3
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v0, s1, v0
+; GFX8-NOHSA-NEXT: s_and_b32 s1, s3, 0xff
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v2, s1, v2
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v8i8_to_v8i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 61, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T11.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T11.XY, T11.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.Y, T8.X,
+; EG-NEXT: MOV * T11.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: AND_INT T0.W, T11.X, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 255(3.573311e-43), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T8.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T0.W, T11.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV T8.X, PV.W,
+; EG-NEXT: MOV T0.Y, T9.X,
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T1.W, T11.X, literal.x, PV.W,
+; EG-NEXT: AND_INT * T2.W, PV.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), -65536(nan)
+; EG-NEXT: OR_INT * T1.W, PS, PV.W,
+; EG-NEXT: MOV * T9.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T1.W, T11.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T12.Y, PV.W, PS,
+; EG-NEXT: MOV T9.X, PV.Y,
+; EG-NEXT: MOV * T0.Y, T4.X,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T2.W, T11.Y, literal.y,
+; EG-NEXT: -65536(nan), 255(3.573311e-43)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV * T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T1.W, T11.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, T5.X,
+; EG-NEXT: BFE_UINT * T0.W, T11.Y, literal.x, T0.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, PV.W, T0.W,
+; EG-NEXT: MOV * T5.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T11.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: LSHR T11.X, KC0[2].Y, literal.x,
+; EG-NEXT: OR_INT * T12.W, PV.W, PS,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T5.X, PV.W,
+; EG-NEXT: MOV * T12.X, T8.X,
+; EG-NEXT: MOV * T12.Z, T4.X,
%load = load <8 x i8>, ptr addrspace(4) %in
%ext = zext <8 x i8> %load to <8 x i16>
store <8 x i16> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v8i8_to_v8i16:
-
-; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-
define amdgpu_kernel void @constant_sextload_v8i8_to_v8i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v8i8_to_v8i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s2, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s6, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s7, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX6-NOHSA-NEXT: s_ashr_i32 s8, s4, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s9, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s10, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX6-NOHSA-NEXT: s_lshl_b32 s2, s2, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s6, s6, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s7, s7, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s5, s5, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s8, s8, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s9, s9, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s10, s10, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xffff
+; GFX6-NOHSA-NEXT: s_or_b32 s6, s6, s2
+; GFX6-NOHSA-NEXT: s_or_b32 s5, s5, s7
+; GFX6-NOHSA-NEXT: s_or_b32 s7, s9, s8
+; GFX6-NOHSA-NEXT: s_or_b32 s4, s4, s10
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s6
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v8i8_to_v8i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s0, s3, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s1, s3, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s4, s3, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s3, s3
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX7-HSA-NEXT: s_lshl_b32 s4, s4, 16
+; GFX7-HSA-NEXT: s_and_b32 s3, s3, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s0, s1, s0
+; GFX7-HSA-NEXT: s_or_b32 s1, s3, s4
+; GFX7-HSA-NEXT: s_ashr_i32 s3, s2, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s4, s2, 0x80010
+; GFX7-HSA-NEXT: s_lshl_b32 s3, s3, 16
+; GFX7-HSA-NEXT: s_and_b32 s4, s4, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s3, s4, s3
+; GFX7-HSA-NEXT: s_bfe_i32 s4, s2, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX7-HSA-NEXT: s_lshl_b32 s4, s4, 16
+; GFX7-HSA-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s2, s2, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v8i8_to_v8i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_bfe_i32 s6, s2, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v0, 8, s2
+; GFX8-NOHSA-NEXT: s_ashr_i64 s[0:1], s[2:3], 56
+; GFX8-NOHSA-NEXT: s_lshr_b32 s5, s3, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s1, 0xffff, s6
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v0, s1, v0
+; GFX8-NOHSA-NEXT: s_bfe_i32 s1, s5, 0x80000
+; GFX8-NOHSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX8-NOHSA-NEXT: s_or_b32 s0, s1, s0
+; GFX8-NOHSA-NEXT: s_bfe_i32 s1, s3, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v1, 8, s3
+; GFX8-NOHSA-NEXT: s_lshr_b32 s4, s2, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v2, s1, v1
+; GFX8-NOHSA-NEXT: s_ashr_i32 s1, s2, 24
+; GFX8-NOHSA-NEXT: s_bfe_i32 s2, s4, 0x80000
+; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s1, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s2, 0xffff, s2
+; GFX8-NOHSA-NEXT: s_or_b32 s1, s2, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v8i8_to_v8i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 74, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T12.XYZW, T11.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T11.XY, T11.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.Y, T8.X,
+; EG-NEXT: MOV * T11.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: BFE_INT * T0.W, T11.X, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 65535(9.183409e-41), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T8.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T11.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T8.X, PV.W,
+; EG-NEXT: MOV T0.Y, T9.X,
+; EG-NEXT: LSHR * T0.W, T11.X, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T9.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T11.X, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: OR_INT * T12.Y, PV.W, PS,
+; EG-NEXT: MOV T9.X, PV.Y,
+; EG-NEXT: MOV T0.Y, T4.X,
+; EG-NEXT: BFE_INT * T0.W, T11.Y, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: -65536(nan), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV * T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T11.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, T5.X,
+; EG-NEXT: LSHR * T0.W, T11.Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T5.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T11.Y, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: LSHR T11.X, KC0[2].Y, literal.x,
+; EG-NEXT: OR_INT * T12.W, PV.W, PS,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T5.X, PV.W,
+; EG-NEXT: MOV * T12.X, T8.X,
+; EG-NEXT: MOV * T12.Z, T4.X,
%load = load <8 x i8>, ptr addrspace(4) %in
%ext = sext <8 x i8> %load to <8 x i16>
store <8 x i16> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v16i8_to_v16i16:
-
-; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v16i8_to_v16i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v16i8_to_v16i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_and_b32 s8, s6, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s9, s7, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s10, s4, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s11, s5, 0xff00
+; GFX6-NOHSA-NEXT: s_lshr_b32 s12, s5, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s13, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s5, s5, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s14, s4, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s15, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s16, s7, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s17, s7, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s7, s7, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s18, s6, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s19, s6, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s6, s6, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s12, s12, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s11, s11, 8
+; GFX6-NOHSA-NEXT: s_and_b32 s14, s14, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s10, s10, 8
+; GFX6-NOHSA-NEXT: s_and_b32 s16, s16, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s9, s9, 8
+; GFX6-NOHSA-NEXT: s_and_b32 s18, s18, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s8, s8, 8
+; GFX6-NOHSA-NEXT: s_or_b32 s12, s13, s12
+; GFX6-NOHSA-NEXT: s_or_b32 s5, s5, s11
+; GFX6-NOHSA-NEXT: s_or_b32 s11, s15, s14
+; GFX6-NOHSA-NEXT: s_or_b32 s13, s17, s16
+; GFX6-NOHSA-NEXT: s_or_b32 s7, s7, s9
+; GFX6-NOHSA-NEXT: s_or_b32 s9, s19, s18
+; GFX6-NOHSA-NEXT: s_or_b32 s6, s6, s8
+; GFX6-NOHSA-NEXT: s_or_b32 s4, s4, s10
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s13
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v16i8_to_v16i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_and_b32 s9, s5, 0xff00
+; GFX7-HSA-NEXT: s_lshr_b32 s10, s5, 8
+; GFX7-HSA-NEXT: s_bfe_u32 s11, s5, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s5, s5, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s9, s9, 8
+; GFX7-HSA-NEXT: s_and_b32 s8, s4, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s10, s10, 0xff0000
+; GFX7-HSA-NEXT: s_or_b32 s5, s5, s9
+; GFX7-HSA-NEXT: s_lshr_b32 s9, s4, 8
+; GFX7-HSA-NEXT: s_and_b32 s3, s7, 0xff00
+; GFX7-HSA-NEXT: s_or_b32 s10, s11, s10
+; GFX7-HSA-NEXT: s_and_b32 s9, s9, 0xff0000
+; GFX7-HSA-NEXT: s_bfe_u32 s11, s4, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s4, s4, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s8, s8, 8
+; GFX7-HSA-NEXT: s_or_b32 s9, s11, s9
+; GFX7-HSA-NEXT: s_or_b32 s4, s4, s8
+; GFX7-HSA-NEXT: s_lshr_b32 s8, s7, 8
+; GFX7-HSA-NEXT: s_bfe_u32 s11, s7, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s7, s7, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s3, s3, 8
+; GFX7-HSA-NEXT: s_and_b32 s2, s6, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s8, s8, 0xff0000
+; GFX7-HSA-NEXT: s_or_b32 s3, s7, s3
+; GFX7-HSA-NEXT: s_lshr_b32 s7, s6, 8
+; GFX7-HSA-NEXT: s_or_b32 s8, s11, s8
+; GFX7-HSA-NEXT: s_and_b32 s7, s7, 0xff0000
+; GFX7-HSA-NEXT: s_bfe_u32 s11, s6, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s6, s6, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s2, s2, 8
+; GFX7-HSA-NEXT: s_or_b32 s7, s11, s7
+; GFX7-HSA-NEXT: s_or_b32 s2, s6, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v16i8_to_v16i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s4
+; GFX8-NOHSA-NEXT: s_lshr_b32 s3, s4, 24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s4
+; GFX8-NOHSA-NEXT: v_alignbit_b32 v1, s3, v1, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s3, s4, 0xff
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v0, s3, v0
+; GFX8-NOHSA-NEXT: s_lshr_b32 s3, s7, 24
+; GFX8-NOHSA-NEXT: s_lshl_b32 s3, s3, 16
+; GFX8-NOHSA-NEXT: s_bfe_u32 s4, s7, 0x80010
+; GFX8-NOHSA-NEXT: s_lshr_b32 s8, s5, 24
+; GFX8-NOHSA-NEXT: s_bfe_u32 s9, s5, 0x80010
+; GFX8-NOHSA-NEXT: s_and_b32 s10, s5, 0xff
+; GFX8-NOHSA-NEXT: s_lshl_b32 s5, s5, 8
+; GFX8-NOHSA-NEXT: s_or_b32 s3, s4, s3
+; GFX8-NOHSA-NEXT: s_and_b32 s4, s7, 0xff
+; GFX8-NOHSA-NEXT: s_lshl_b32 s7, s7, 8
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v2, 8, s6
+; GFX8-NOHSA-NEXT: s_lshr_b32 s2, s6, 24
+; GFX8-NOHSA-NEXT: s_lshl_b32 s8, s8, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s5, s5, 0xff0000
+; GFX8-NOHSA-NEXT: s_and_b32 s7, s7, 0xff0000
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s6
+; GFX8-NOHSA-NEXT: s_or_b32 s8, s9, s8
+; GFX8-NOHSA-NEXT: s_or_b32 s5, s10, s5
+; GFX8-NOHSA-NEXT: s_or_b32 s4, s4, s7
+; GFX8-NOHSA-NEXT: v_alignbit_b32 v3, s2, v3, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s2, s6, 0xff
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v2, s2, v2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s3
+; GFX8-NOHSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s4
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[2:5]
+; GFX8-NOHSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v16i8_to_v16i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 103, @12, KC0[], KC1[]
+; EG-NEXT: ALU 20, @116, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T22.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T21.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T19.XYZW, T19.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T0.Y, T16.X,
+; EG-NEXT: MOV * T19.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: AND_INT T0.W, T19.X, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 255(3.573311e-43), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T16.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T0.W, T19.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV T16.X, PV.W,
+; EG-NEXT: MOV T0.Y, T17.X,
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T1.W, T19.X, literal.x, PV.W,
+; EG-NEXT: AND_INT * T2.W, PV.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), -65536(nan)
+; EG-NEXT: OR_INT * T1.W, PS, PV.W,
+; EG-NEXT: MOV * T17.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T1.W, T19.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T20.Y, PV.W, PS,
+; EG-NEXT: MOV T17.X, PV.Y,
+; EG-NEXT: MOV * T0.Y, T12.X,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T2.W, T19.Y, literal.y,
+; EG-NEXT: -65536(nan), 255(3.573311e-43)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV * T12.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T1.W, T19.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV T12.X, PV.W,
+; EG-NEXT: MOV T0.Y, T13.X,
+; EG-NEXT: BFE_UINT * T1.W, T19.Y, literal.x, T0.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, PV.W, T1.W,
+; EG-NEXT: MOV * T13.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T1.W, T19.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T20.W, PV.W, PS,
+; EG-NEXT: MOV T13.X, PV.W,
+; EG-NEXT: MOV * T0.Y, T8.X,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T2.W, T19.Z, literal.y,
+; EG-NEXT: -65536(nan), 255(3.573311e-43)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV * T8.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T1.W, T19.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV T8.X, PV.W,
+; EG-NEXT: MOV T0.Y, T9.X,
+; EG-NEXT: BFE_UINT * T1.W, T19.Z, literal.x, T0.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, PV.W, T1.W,
+; EG-NEXT: MOV * T9.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T1.W, T19.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T19.Y, PV.W, PS,
+; EG-NEXT: MOV T9.X, PV.Y,
+; EG-NEXT: MOV * T0.Y, T4.X,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T2.W, T19.W, literal.y,
+; EG-NEXT: -65536(nan), 255(3.573311e-43)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV * T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T1.W, T19.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, T5.X,
+; EG-NEXT: BFE_UINT * T0.W, T19.W, literal.x, T0.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 116:
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, PV.W, T0.W,
+; EG-NEXT: MOV * T5.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR T0.W, T19.W, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 16(2.242078e-44)
+; EG-NEXT: LSHR T21.X, PS, literal.x,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.y,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.z,
+; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41)
+; EG-NEXT: 16711680(2.341805e-38), 0(0.000000e+00)
+; EG-NEXT: LSHR T22.X, KC0[2].Y, literal.x,
+; EG-NEXT: OR_INT * T19.W, PV.W, PS,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T5.X, PV.W,
+; EG-NEXT: MOV * T20.X, T16.X,
+; EG-NEXT: MOV * T20.Z, T12.X,
+; EG-NEXT: MOV T19.X, T8.X,
+; EG-NEXT: MOV * T19.Z, T4.X, BS:VEC_120/SCL_212
%load = load <16 x i8>, ptr addrspace(4) %in
%ext = zext <16 x i8> %load to <16 x i16>
store <16 x i16> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v16i8_to_v16i16:
-
-; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
define amdgpu_kernel void @constant_sextload_v16i8_to_v16i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v16i8_to_v16i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s2, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s8, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s9, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s10, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX6-NOHSA-NEXT: s_ashr_i32 s11, s4, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s12, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s13, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX6-NOHSA-NEXT: s_ashr_i32 s14, s7, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s15, s7, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s16, s7, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX6-NOHSA-NEXT: s_ashr_i32 s17, s6, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s18, s6, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s19, s6, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s6, s6
+; GFX6-NOHSA-NEXT: s_lshl_b32 s8, s8, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s9, s9, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s10, s10, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s5, s5, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s11, s11, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s12, s12, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s13, s13, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s14, s14, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s15, s15, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s16, s16, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s7, s7, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s17, s17, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s18, s18, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s19, s19, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s6, s6, 0xffff
+; GFX6-NOHSA-NEXT: s_or_b32 s8, s9, s8
+; GFX6-NOHSA-NEXT: s_or_b32 s5, s5, s10
+; GFX6-NOHSA-NEXT: s_or_b32 s9, s12, s11
+; GFX6-NOHSA-NEXT: s_or_b32 s10, s15, s14
+; GFX6-NOHSA-NEXT: s_or_b32 s7, s7, s16
+; GFX6-NOHSA-NEXT: s_or_b32 s11, s18, s17
+; GFX6-NOHSA-NEXT: s_or_b32 s6, s6, s19
+; GFX6-NOHSA-NEXT: s_or_b32 s4, s4, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s11
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s10
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s9
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s8
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v16i8_to_v16i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s2, s5, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s3, s5, 0x80010
+; GFX7-HSA-NEXT: s_lshl_b32 s2, s2, 16
+; GFX7-HSA-NEXT: s_and_b32 s3, s3, 0xffff
+; GFX7-HSA-NEXT: s_bfe_i32 s8, s5, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX7-HSA-NEXT: s_ashr_i32 s9, s4, 24
+; GFX7-HSA-NEXT: s_or_b32 s10, s3, s2
+; GFX7-HSA-NEXT: s_bfe_i32 s3, s4, 0x80010
+; GFX7-HSA-NEXT: s_lshl_b32 s8, s8, 16
+; GFX7-HSA-NEXT: s_and_b32 s5, s5, 0xffff
+; GFX7-HSA-NEXT: s_lshl_b32 s2, s9, 16
+; GFX7-HSA-NEXT: s_and_b32 s3, s3, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s5, s5, s8
+; GFX7-HSA-NEXT: s_or_b32 s8, s3, s2
+; GFX7-HSA-NEXT: s_bfe_i32 s2, s4, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s3, s4
+; GFX7-HSA-NEXT: s_lshl_b32 s2, s2, 16
+; GFX7-HSA-NEXT: s_and_b32 s3, s3, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s4, s3, s2
+; GFX7-HSA-NEXT: s_ashr_i32 s2, s7, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s3, s7, 0x80010
+; GFX7-HSA-NEXT: s_lshl_b32 s2, s2, 16
+; GFX7-HSA-NEXT: s_and_b32 s3, s3, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s2, s3, s2
+; GFX7-HSA-NEXT: s_bfe_i32 s3, s7, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX7-HSA-NEXT: s_lshl_b32 s3, s3, 16
+; GFX7-HSA-NEXT: s_and_b32 s7, s7, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s3, s7, s3
+; GFX7-HSA-NEXT: s_ashr_i32 s7, s6, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s9, s6, 0x80010
+; GFX7-HSA-NEXT: s_lshl_b32 s7, s7, 16
+; GFX7-HSA-NEXT: s_and_b32 s9, s9, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s7, s9, s7
+; GFX7-HSA-NEXT: s_bfe_i32 s9, s6, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s6, s6
+; GFX7-HSA-NEXT: s_lshl_b32 s9, s9, 16
+; GFX7-HSA-NEXT: s_and_b32 s6, s6, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s6, s6, s9
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-HSA-NEXT: s_add_u32 s2, s0, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s2
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v16i8_to_v16i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[4:7], s[2:3], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_bfe_i32 s10, s5, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v0, 8, s5
+; GFX8-NOHSA-NEXT: s_lshr_b32 s3, s5, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s10, 0xffff, s10
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NOHSA-NEXT: s_lshr_b32 s2, s4, 16
+; GFX8-NOHSA-NEXT: s_bfe_i32 s5, s4, 0x80000
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v2, s10, v0
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v0, 8, s4
+; GFX8-NOHSA-NEXT: s_bfe_i32 s4, s3, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v1, 8, s3
+; GFX8-NOHSA-NEXT: s_and_b32 s4, 0xffff, s4
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v3, s4, v1
+; GFX8-NOHSA-NEXT: s_bfe_i32 s3, s2, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v1, 8, s2
+; GFX8-NOHSA-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NOHSA-NEXT: s_lshr_b32 s9, s7, 16
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v1, s3, v1
+; GFX8-NOHSA-NEXT: s_ashr_i64 s[2:3], s[6:7], 56
+; GFX8-NOHSA-NEXT: s_bfe_i32 s3, s9, 0x80000
+; GFX8-NOHSA-NEXT: s_lshl_b32 s2, s2, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-NOHSA-NEXT: s_or_b32 s2, s3, s2
+; GFX8-NOHSA-NEXT: s_bfe_i32 s3, s7, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v4, 8, s7
+; GFX8-NOHSA-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v6, s3, v4
+; GFX8-NOHSA-NEXT: s_bfe_i32 s3, s6, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v4, 8, s6
+; GFX8-NOHSA-NEXT: s_lshr_b32 s8, s6, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v4, s3, v4
+; GFX8-NOHSA-NEXT: s_bfe_i32 s3, s8, 0x80000
+; GFX8-NOHSA-NEXT: s_and_b32 s5, 0xffff, s5
+; GFX8-NOHSA-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v5, 8, s8
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s2
+; GFX8-NOHSA-NEXT: s_add_u32 s2, s0, 16
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v5, s3, v5
+; GFX8-NOHSA-NEXT: s_addc_u32 s3, s1, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s2
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v0, s5, v0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v16i8_to_v16i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 104, @12, KC0[], KC1[]
+; EG-NEXT: ALU 46, @117, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T20.XYZW, T22.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T19.XYZW, T21.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_128 T19.XYZW, T19.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T0.Y, T16.X,
+; EG-NEXT: MOV * T19.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: BFE_INT * T0.W, T19.X, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 65535(9.183409e-41), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T16.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T19.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T16.X, PV.W,
+; EG-NEXT: MOV T0.Y, T17.X,
+; EG-NEXT: LSHR * T0.W, T19.X, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T17.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T19.X, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: OR_INT * T20.Y, PV.W, PS,
+; EG-NEXT: MOV T17.X, PV.Y,
+; EG-NEXT: MOV T0.Y, T12.X,
+; EG-NEXT: BFE_INT * T0.W, T19.Y, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: -65536(nan), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV * T12.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T19.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T12.X, PV.W,
+; EG-NEXT: MOV T0.Y, T13.X,
+; EG-NEXT: LSHR * T0.W, T19.Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T13.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T19.Y, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: OR_INT * T20.W, PV.W, PS,
+; EG-NEXT: MOV T13.X, PV.W,
+; EG-NEXT: MOV T0.Y, T8.X,
+; EG-NEXT: BFE_INT * T0.W, T19.Z, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: -65536(nan), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV * T8.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T19.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T8.X, PV.W,
+; EG-NEXT: MOV T0.Y, T9.X,
+; EG-NEXT: LSHR * T0.W, T19.Z, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T9.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T19.Z, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: ALU clause starting at 117:
+; EG-NEXT: OR_INT * T19.Y, T1.W, T0.W,
+; EG-NEXT: MOV T9.X, PV.Y,
+; EG-NEXT: MOV T0.Y, T4.X,
+; EG-NEXT: BFE_INT * T0.W, T19.W, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: -65536(nan), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV * T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T19.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, T5.X,
+; EG-NEXT: LSHR * T0.W, T19.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T5.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR T0.W, T19.W, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 24(3.363116e-44), 16(2.242078e-44)
+; EG-NEXT: LSHR T21.X, PS, literal.x,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.y,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.z,
+; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41)
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T22.X, KC0[2].Y, literal.x,
+; EG-NEXT: OR_INT * T19.W, PV.W, PS,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T5.X, PV.W,
+; EG-NEXT: MOV * T20.X, T16.X,
+; EG-NEXT: MOV * T20.Z, T12.X,
+; EG-NEXT: MOV T19.X, T8.X,
+; EG-NEXT: MOV * T19.Z, T4.X, BS:VEC_120/SCL_212
%load = load <16 x i8>, ptr addrspace(4) %in
%ext = sext <16 x i8> %load to <16 x i16>
store <16 x i16> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_zextload_v32i8_to_v32i16:
-
-; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
-; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
define amdgpu_kernel void @constant_zextload_v32i8_to_v32i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_zextload_v32i8_to_v32i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_and_b32 s12, s6, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s13, s7, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s14, s4, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s15, s5, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s16, s2, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s17, s3, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s18, s0, 0xff00
+; GFX6-NOHSA-NEXT: s_and_b32 s19, s1, 0xff00
+; GFX6-NOHSA-NEXT: s_lshr_b32 s20, s1, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s21, s1, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s1, s1, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s22, s0, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s23, s0, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s0, s0, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s24, s3, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s25, s3, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s3, s3, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s26, s2, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s27, s2, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s2, s2, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s28, s5, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s29, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s5, s5, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s30, s4, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s31, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s33, s7, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s34, s7, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s7, s7, 0xff
+; GFX6-NOHSA-NEXT: s_lshr_b32 s35, s6, 8
+; GFX6-NOHSA-NEXT: s_bfe_u32 s36, s6, 0x80010
+; GFX6-NOHSA-NEXT: s_and_b32 s6, s6, 0xff
+; GFX6-NOHSA-NEXT: s_and_b32 s20, s20, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s19, s19, 8
+; GFX6-NOHSA-NEXT: s_and_b32 s22, s22, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s18, s18, 8
+; GFX6-NOHSA-NEXT: s_and_b32 s24, s24, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s17, s17, 8
+; GFX6-NOHSA-NEXT: s_and_b32 s26, s26, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s16, s16, 8
+; GFX6-NOHSA-NEXT: s_and_b32 s28, s28, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s15, s15, 8
+; GFX6-NOHSA-NEXT: s_and_b32 s30, s30, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s14, s14, 8
+; GFX6-NOHSA-NEXT: s_and_b32 s33, s33, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s13, s13, 8
+; GFX6-NOHSA-NEXT: s_and_b32 s35, s35, 0xff0000
+; GFX6-NOHSA-NEXT: s_lshl_b32 s12, s12, 8
+; GFX6-NOHSA-NEXT: s_or_b32 s20, s21, s20
+; GFX6-NOHSA-NEXT: s_or_b32 s1, s1, s19
+; GFX6-NOHSA-NEXT: s_or_b32 s19, s23, s22
+; GFX6-NOHSA-NEXT: s_or_b32 s0, s0, s18
+; GFX6-NOHSA-NEXT: s_or_b32 s18, s25, s24
+; GFX6-NOHSA-NEXT: s_or_b32 s3, s3, s17
+; GFX6-NOHSA-NEXT: s_or_b32 s17, s27, s26
+; GFX6-NOHSA-NEXT: s_or_b32 s2, s2, s16
+; GFX6-NOHSA-NEXT: s_or_b32 s16, s29, s28
+; GFX6-NOHSA-NEXT: s_or_b32 s5, s5, s15
+; GFX6-NOHSA-NEXT: s_or_b32 s15, s31, s30
+; GFX6-NOHSA-NEXT: s_or_b32 s21, s34, s33
+; GFX6-NOHSA-NEXT: s_or_b32 s7, s7, s13
+; GFX6-NOHSA-NEXT: s_or_b32 s13, s36, s35
+; GFX6-NOHSA-NEXT: s_or_b32 s6, s6, s12
+; GFX6-NOHSA-NEXT: s_or_b32 s4, s4, s14
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s21
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s16
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s20
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_zextload_v32i8_to_v32i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_and_b32 s17, s1, 0xff00
+; GFX7-HSA-NEXT: s_lshr_b32 s18, s1, 8
+; GFX7-HSA-NEXT: s_bfe_u32 s19, s1, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s17, s17, 8
+; GFX7-HSA-NEXT: s_and_b32 s18, s18, 0xff0000
+; GFX7-HSA-NEXT: s_or_b32 s17, s1, s17
+; GFX7-HSA-NEXT: s_lshr_b32 s1, s0, 8
+; GFX7-HSA-NEXT: s_and_b32 s16, s0, 0xff00
+; GFX7-HSA-NEXT: s_or_b32 s18, s19, s18
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xff0000
+; GFX7-HSA-NEXT: s_bfe_u32 s19, s0, 0x80010
+; GFX7-HSA-NEXT: s_or_b32 s19, s19, s1
+; GFX7-HSA-NEXT: s_and_b32 s0, s0, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s16, 8
+; GFX7-HSA-NEXT: s_or_b32 s16, s0, s1
+; GFX7-HSA-NEXT: s_lshr_b32 s0, s3, 8
+; GFX7-HSA-NEXT: s_and_b32 s15, s3, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s0, s0, 0xff0000
+; GFX7-HSA-NEXT: s_bfe_u32 s1, s3, 0x80010
+; GFX7-HSA-NEXT: s_or_b32 s20, s1, s0
+; GFX7-HSA-NEXT: s_and_b32 s0, s3, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s15, 8
+; GFX7-HSA-NEXT: s_or_b32 s3, s0, s1
+; GFX7-HSA-NEXT: s_lshr_b32 s0, s2, 8
+; GFX7-HSA-NEXT: s_and_b32 s14, s2, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s0, s0, 0xff0000
+; GFX7-HSA-NEXT: s_bfe_u32 s1, s2, 0x80010
+; GFX7-HSA-NEXT: s_or_b32 s15, s1, s0
+; GFX7-HSA-NEXT: s_and_b32 s0, s2, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s14, 8
+; GFX7-HSA-NEXT: s_or_b32 s2, s0, s1
+; GFX7-HSA-NEXT: s_lshr_b32 s0, s5, 8
+; GFX7-HSA-NEXT: s_and_b32 s13, s5, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s0, s0, 0xff0000
+; GFX7-HSA-NEXT: s_bfe_u32 s1, s5, 0x80010
+; GFX7-HSA-NEXT: s_or_b32 s14, s1, s0
+; GFX7-HSA-NEXT: s_and_b32 s0, s5, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s13, 8
+; GFX7-HSA-NEXT: s_or_b32 s5, s0, s1
+; GFX7-HSA-NEXT: s_lshr_b32 s0, s4, 8
+; GFX7-HSA-NEXT: s_and_b32 s12, s4, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s0, s0, 0xff0000
+; GFX7-HSA-NEXT: s_bfe_u32 s1, s4, 0x80010
+; GFX7-HSA-NEXT: s_or_b32 s13, s1, s0
+; GFX7-HSA-NEXT: s_and_b32 s0, s4, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s12, 8
+; GFX7-HSA-NEXT: s_or_b32 s4, s0, s1
+; GFX7-HSA-NEXT: s_lshr_b32 s0, s7, 8
+; GFX7-HSA-NEXT: s_and_b32 s11, s7, 0xff00
+; GFX7-HSA-NEXT: s_and_b32 s0, s0, 0xff0000
+; GFX7-HSA-NEXT: s_bfe_u32 s1, s7, 0x80010
+; GFX7-HSA-NEXT: s_or_b32 s0, s1, s0
+; GFX7-HSA-NEXT: s_and_b32 s1, s7, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s7, s11, 8
+; GFX7-HSA-NEXT: s_and_b32 s10, s6, 0xff00
+; GFX7-HSA-NEXT: s_or_b32 s1, s1, s7
+; GFX7-HSA-NEXT: s_lshr_b32 s7, s6, 8
+; GFX7-HSA-NEXT: s_and_b32 s7, s7, 0xff0000
+; GFX7-HSA-NEXT: s_bfe_u32 s11, s6, 0x80010
+; GFX7-HSA-NEXT: s_and_b32 s6, s6, 0xff
+; GFX7-HSA-NEXT: s_lshl_b32 s10, s10, 8
+; GFX7-HSA-NEXT: s_or_b32 s7, s11, s7
+; GFX7-HSA-NEXT: s_or_b32 s6, s6, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX7-HSA-NEXT: s_add_u32 s0, s8, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: s_add_u32 s0, s8, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: s_add_u32 s0, s8, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s20
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_zextload_v32i8_to_v32i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_lshr_b32 s14, s1, 24
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v0, 8, s0
+; GFX8-NOHSA-NEXT: s_lshl_b32 s14, s14, 16
+; GFX8-NOHSA-NEXT: s_bfe_u32 s15, s1, 0x80010
+; GFX8-NOHSA-NEXT: s_lshr_b32 s13, s0, 24
+; GFX8-NOHSA-NEXT: s_or_b32 s14, s15, s14
+; GFX8-NOHSA-NEXT: s_and_b32 s15, s1, 0xff
+; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s1, 8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v1, s0
+; GFX8-NOHSA-NEXT: s_and_b32 s0, s0, 0xff
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NOHSA-NEXT: s_and_b32 s1, s1, 0xff0000
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v0, s0, v0
+; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s3, 24
+; GFX8-NOHSA-NEXT: s_or_b32 s15, s15, s1
+; GFX8-NOHSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX8-NOHSA-NEXT: s_bfe_u32 s1, s3, 0x80010
+; GFX8-NOHSA-NEXT: v_alignbit_b32 v1, s13, v1, 16
+; GFX8-NOHSA-NEXT: s_or_b32 s13, s1, s0
+; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s3, 8
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v2, 8, s2
+; GFX8-NOHSA-NEXT: s_and_b32 s0, s3, 0xff
+; GFX8-NOHSA-NEXT: s_and_b32 s1, s1, 0xff0000
+; GFX8-NOHSA-NEXT: s_or_b32 s3, s0, s1
+; GFX8-NOHSA-NEXT: s_and_b32 s0, s2, 0xff
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v2, s0, v2
+; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s5, 24
+; GFX8-NOHSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX8-NOHSA-NEXT: s_bfe_u32 s1, s5, 0x80010
+; GFX8-NOHSA-NEXT: s_lshr_b32 s12, s2, 24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s2
+; GFX8-NOHSA-NEXT: s_or_b32 s2, s1, s0
+; GFX8-NOHSA-NEXT: s_lshl_b32 s1, s5, 8
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v4, 8, s4
+; GFX8-NOHSA-NEXT: s_and_b32 s0, s5, 0xff
+; GFX8-NOHSA-NEXT: s_and_b32 s1, s1, 0xff0000
+; GFX8-NOHSA-NEXT: s_or_b32 s5, s0, s1
+; GFX8-NOHSA-NEXT: s_and_b32 s0, s4, 0xff
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v4, s0, v4
+; GFX8-NOHSA-NEXT: s_lshr_b32 s0, s7, 24
+; GFX8-NOHSA-NEXT: s_lshr_b32 s11, s4, 24
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s4
+; GFX8-NOHSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX8-NOHSA-NEXT: s_bfe_u32 s1, s7, 0x80010
+; GFX8-NOHSA-NEXT: s_lshl_b32 s4, s7, 8
+; GFX8-NOHSA-NEXT: s_or_b32 s0, s1, s0
+; GFX8-NOHSA-NEXT: s_and_b32 s1, s7, 0xff
+; GFX8-NOHSA-NEXT: s_and_b32 s4, s4, 0xff0000
+; GFX8-NOHSA-NEXT: s_lshr_b32 s10, s6, 24
+; GFX8-NOHSA-NEXT: s_or_b32 s1, s1, s4
+; GFX8-NOHSA-NEXT: s_and_b32 s4, s6, 0xff
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 48
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s1
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: v_lshrrev_b16_e64 v6, 8, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s1
+; GFX8-NOHSA-NEXT: v_alignbit_b32 v7, s10, v7, 16
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v10, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 32
+; GFX8-NOHSA-NEXT: v_and_b32_e32 v7, 0xff00ff, v7
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v6, s4, v6
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[10:11], v[6:9]
+; GFX8-NOHSA-NEXT: v_alignbit_b32 v5, s11, v5, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 16
+; GFX8-NOHSA-NEXT: v_and_b32_e32 v5, 0xff00ff, v5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s5
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s2
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: v_alignbit_b32 v3, s12, v3, 16
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NOHSA-NEXT: v_and_b32_e32 v3, 0xff00ff, v3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v7, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s3
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s13
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v6, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[6:7], v[2:5]
+; GFX8-NOHSA-NEXT: v_and_b32_e32 v1, 0xff00ff, v1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v2, s15
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_zextload_v32i8_to_v32i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @10
+; EG-NEXT: ALU 103, @16, KC0[], KC1[]
+; EG-NEXT: ALU 104, @120, KC0[], KC1[]
+; EG-NEXT: ALU 41, @225, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T37.XYZW, T42.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T36.XYZW, T41.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T38.XYZW, T40.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T35.XYZW, T39.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 10:
+; EG-NEXT: VTX_READ_128 T36.XYZW, T35.X, 16, #1
+; EG-NEXT: VTX_READ_128 T35.XYZW, T35.X, 0, #1
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: MOV * T0.Y, T16.X,
+; EG-NEXT: MOV * T35.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 16:
+; EG-NEXT: AND_INT T0.W, T36.X, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 255(3.573311e-43), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T16.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T0.W, T36.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV T16.X, PV.W,
+; EG-NEXT: MOV T0.Y, T17.X,
+; EG-NEXT: MOV * T0.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_UINT T1.W, T36.X, literal.x, PV.W,
+; EG-NEXT: AND_INT * T2.W, PV.Y, literal.y,
+; EG-NEXT: 16(2.242078e-44), -65536(nan)
+; EG-NEXT: OR_INT * T1.W, PS, PV.W,
+; EG-NEXT: MOV * T17.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T1.W, T36.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T37.Y, PV.W, PS,
+; EG-NEXT: MOV T17.X, PV.Y,
+; EG-NEXT: MOV * T0.Y, T12.X,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T2.W, T36.Y, literal.y,
+; EG-NEXT: -65536(nan), 255(3.573311e-43)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV * T12.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T1.W, T36.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV T12.X, PV.W,
+; EG-NEXT: MOV T0.Y, T13.X,
+; EG-NEXT: BFE_UINT * T1.W, T36.Y, literal.x, T0.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, PV.W, T1.W,
+; EG-NEXT: MOV * T13.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T1.W, T36.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T37.W, PV.W, PS,
+; EG-NEXT: MOV T13.X, PV.W,
+; EG-NEXT: MOV * T0.Y, T8.X,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T2.W, T36.Z, literal.y,
+; EG-NEXT: -65536(nan), 255(3.573311e-43)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV * T8.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T1.W, T36.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV T8.X, PV.W,
+; EG-NEXT: MOV T0.Y, T9.X,
+; EG-NEXT: BFE_UINT * T1.W, T36.Z, literal.x, T0.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, PV.W, T1.W,
+; EG-NEXT: MOV * T9.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T1.W, T36.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T36.Y, PV.W, PS,
+; EG-NEXT: MOV T9.X, PV.Y,
+; EG-NEXT: MOV * T0.Y, T4.X,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T2.W, T36.W, literal.y,
+; EG-NEXT: -65536(nan), 255(3.573311e-43)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV * T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T1.W, T36.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, T5.X,
+; EG-NEXT: BFE_UINT * T1.W, T36.W, literal.x, T0.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 120:
+; EG-NEXT: AND_INT * T2.W, T0.Y, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, PV.W, T1.W,
+; EG-NEXT: MOV * T5.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T1.W, T36.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T36.W, PV.W, PS,
+; EG-NEXT: MOV T5.X, PV.W,
+; EG-NEXT: MOV * T0.Y, T32.X,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T2.W, T35.X, literal.y,
+; EG-NEXT: -65536(nan), 255(3.573311e-43)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV * T32.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T1.W, T35.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV T32.X, PV.W,
+; EG-NEXT: MOV T0.Y, T33.X,
+; EG-NEXT: BFE_UINT * T1.W, T35.X, literal.x, T0.W, BS:VEC_120/SCL_212
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, PV.W, T1.W,
+; EG-NEXT: MOV * T33.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T1.W, T35.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T38.Y, PV.W, PS,
+; EG-NEXT: MOV T33.X, PV.Y,
+; EG-NEXT: MOV * T0.Y, T28.X,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T2.W, T35.Y, literal.y,
+; EG-NEXT: -65536(nan), 255(3.573311e-43)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV * T28.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T1.W, T35.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV T28.X, PV.W,
+; EG-NEXT: MOV T0.Y, T29.X,
+; EG-NEXT: BFE_UINT * T1.W, T35.Y, literal.x, T0.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, PV.W, T1.W,
+; EG-NEXT: MOV * T29.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T1.W, T35.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T38.W, PV.W, PS,
+; EG-NEXT: MOV T29.X, PV.W,
+; EG-NEXT: MOV * T0.Y, T24.X,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T2.W, T35.Z, literal.y,
+; EG-NEXT: -65536(nan), 255(3.573311e-43)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV * T24.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHL * T1.W, T35.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV T24.X, PV.W,
+; EG-NEXT: MOV T0.Y, T25.X,
+; EG-NEXT: BFE_UINT * T1.W, T35.Z, literal.x, T0.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT * T2.W, PV.Y, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.W, PV.W, T1.W,
+; EG-NEXT: MOV * T25.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T1.W, T35.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T35.Y, PV.W, PS,
+; EG-NEXT: MOV T25.X, PV.Y,
+; EG-NEXT: MOV * T0.Y, T20.X,
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T2.W, T35.W, literal.y,
+; EG-NEXT: -65536(nan), 255(3.573311e-43)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV * T20.X, PV.W,
+; EG-NEXT: ALU clause starting at 225:
+; EG-NEXT: MOV T0.Y, T20.X,
+; EG-NEXT: LSHL * T1.W, T35.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T2.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16711680(2.341805e-38)
+; EG-NEXT: OR_INT * T1.W, PV.W, PS,
+; EG-NEXT: MOV T20.X, PV.W,
+; EG-NEXT: MOV T0.Y, T21.X,
+; EG-NEXT: BFE_UINT * T0.W, T35.W, literal.x, T0.W,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x,
+; EG-NEXT: -65536(nan), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, PV.W, T0.W,
+; EG-NEXT: MOV * T21.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T39.X, PV.W, literal.x,
+; EG-NEXT: LSHR * T40.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: LSHR T0.W, T35.W, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 48(6.726233e-44)
+; EG-NEXT: LSHR T41.X, PS, literal.x,
+; EG-NEXT: AND_INT T0.Z, T0.Y, literal.y,
+; EG-NEXT: AND_INT T0.W, PV.W, literal.z,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41)
+; EG-NEXT: 16711680(2.341805e-38), 32(4.484155e-44)
+; EG-NEXT: LSHR T42.X, PS, literal.x,
+; EG-NEXT: OR_INT * T35.W, PV.Z, PV.W,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T21.X, PV.W,
+; EG-NEXT: MOV * T37.X, T16.X,
+; EG-NEXT: MOV * T37.Z, T12.X,
+; EG-NEXT: MOV T36.X, T8.X,
+; EG-NEXT: MOV T36.Z, T4.X, BS:VEC_120/SCL_212
+; EG-NEXT: MOV * T38.X, T32.X,
+; EG-NEXT: MOV * T38.Z, T28.X,
+; EG-NEXT: MOV T35.X, T24.X,
+; EG-NEXT: MOV * T35.Z, T20.X, BS:VEC_120/SCL_212
%load = load <32 x i8>, ptr addrspace(4) %in
%ext = zext <32 x i8> %load to <32 x i16>
store <32 x i16> %ext, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}constant_sextload_v32i8_to_v32i16:
-
-; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
-; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
-; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
define amdgpu_kernel void @constant_sextload_v32i8_to_v32i16(ptr addrspace(1) %out, ptr addrspace(4) %in) #0 {
+; GFX6-NOHSA-LABEL: constant_sextload_v32i8_to_v32i16:
+; GFX6-NOHSA: ; %bb.0:
+; GFX6-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-NOHSA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NOHSA-NEXT: s_mov_b32 s10, -1
+; GFX6-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NOHSA-NEXT: s_ashr_i32 s12, s1, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s13, s1, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s14, s1, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s1, s1
+; GFX6-NOHSA-NEXT: s_ashr_i32 s15, s0, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s16, s0, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s17, s0, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s0, s0
+; GFX6-NOHSA-NEXT: s_ashr_i32 s18, s3, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s19, s3, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s20, s3, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s3, s3
+; GFX6-NOHSA-NEXT: s_ashr_i32 s21, s2, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s22, s2, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s23, s2, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s2, s2
+; GFX6-NOHSA-NEXT: s_ashr_i32 s24, s5, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s25, s5, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s26, s5, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s5, s5
+; GFX6-NOHSA-NEXT: s_ashr_i32 s27, s4, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s28, s4, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s29, s4, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s4, s4
+; GFX6-NOHSA-NEXT: s_ashr_i32 s30, s7, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s31, s7, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s33, s7, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX6-NOHSA-NEXT: s_ashr_i32 s34, s6, 24
+; GFX6-NOHSA-NEXT: s_bfe_i32 s35, s6, 0x80010
+; GFX6-NOHSA-NEXT: s_bfe_i32 s36, s6, 0x80008
+; GFX6-NOHSA-NEXT: s_sext_i32_i8 s6, s6
+; GFX6-NOHSA-NEXT: s_lshl_b32 s12, s12, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s13, s13, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s14, s14, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s15, s15, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s16, s16, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s17, s17, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s0, s0, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s18, s18, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s19, s19, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s20, s20, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s3, s3, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s21, s21, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s22, s22, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s23, s23, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s24, s24, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s25, s25, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s26, s26, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s5, s5, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s27, s27, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s28, s28, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s29, s29, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s4, s4, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s30, s30, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s31, s31, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s33, s33, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s7, s7, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s34, s34, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s35, s35, 0xffff
+; GFX6-NOHSA-NEXT: s_lshl_b32 s36, s36, 16
+; GFX6-NOHSA-NEXT: s_and_b32 s6, s6, 0xffff
+; GFX6-NOHSA-NEXT: s_or_b32 s12, s13, s12
+; GFX6-NOHSA-NEXT: s_or_b32 s1, s1, s14
+; GFX6-NOHSA-NEXT: s_or_b32 s13, s16, s15
+; GFX6-NOHSA-NEXT: s_or_b32 s0, s0, s17
+; GFX6-NOHSA-NEXT: s_or_b32 s14, s19, s18
+; GFX6-NOHSA-NEXT: s_or_b32 s3, s3, s20
+; GFX6-NOHSA-NEXT: s_or_b32 s15, s22, s21
+; GFX6-NOHSA-NEXT: s_or_b32 s2, s2, s23
+; GFX6-NOHSA-NEXT: s_or_b32 s16, s25, s24
+; GFX6-NOHSA-NEXT: s_or_b32 s5, s5, s26
+; GFX6-NOHSA-NEXT: s_or_b32 s17, s28, s27
+; GFX6-NOHSA-NEXT: s_or_b32 s18, s31, s30
+; GFX6-NOHSA-NEXT: s_or_b32 s7, s7, s33
+; GFX6-NOHSA-NEXT: s_or_b32 s19, s35, s34
+; GFX6-NOHSA-NEXT: s_or_b32 s6, s6, s36
+; GFX6-NOHSA-NEXT: s_or_b32 s4, s4, s29
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s19
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s7
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s18
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:48
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s16
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:32
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0 offset:16
+; GFX6-NOHSA-NEXT: s_waitcnt expcnt(0)
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v1, s13
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-NOHSA-NEXT: v_mov_b32_e32 v3, s12
+; GFX6-NOHSA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NOHSA-NEXT: s_endpgm
+;
+; GFX7-HSA-LABEL: constant_sextload_v32i8_to_v32i16:
+; GFX7-HSA: ; %bb.0:
+; GFX7-HSA-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX7-HSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-HSA-NEXT: s_ashr_i32 s10, s1, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s11, s1, 0x80010
+; GFX7-HSA-NEXT: s_bfe_i32 s12, s1, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s1, s1
+; GFX7-HSA-NEXT: s_lshl_b32 s10, s10, 16
+; GFX7-HSA-NEXT: s_and_b32 s11, s11, 0xffff
+; GFX7-HSA-NEXT: s_lshl_b32 s12, s12, 16
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX7-HSA-NEXT: s_ashr_i32 s13, s0, 24
+; GFX7-HSA-NEXT: s_or_b32 s10, s11, s10
+; GFX7-HSA-NEXT: s_or_b32 s11, s1, s12
+; GFX7-HSA-NEXT: s_bfe_i32 s12, s0, 0x80010
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s13, 16
+; GFX7-HSA-NEXT: s_and_b32 s12, s12, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s12, s12, s1
+; GFX7-HSA-NEXT: s_bfe_i32 s1, s0, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s0, s0
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s1, 16
+; GFX7-HSA-NEXT: s_and_b32 s0, s0, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s13, s0, s1
+; GFX7-HSA-NEXT: s_ashr_i32 s0, s3, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s1, s3, 0x80010
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s14, s1, s0
+; GFX7-HSA-NEXT: s_bfe_i32 s0, s3, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s1, s3
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s3, s1, s0
+; GFX7-HSA-NEXT: s_ashr_i32 s0, s2, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s1, s2, 0x80010
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s15, s1, s0
+; GFX7-HSA-NEXT: s_bfe_i32 s0, s2, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s1, s2
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s2, s1, s0
+; GFX7-HSA-NEXT: s_ashr_i32 s0, s5, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s1, s5, 0x80010
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s16, s1, s0
+; GFX7-HSA-NEXT: s_bfe_i32 s0, s5, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s1, s5
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s5, s1, s0
+; GFX7-HSA-NEXT: s_ashr_i32 s0, s4, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s1, s4, 0x80010
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s17, s1, s0
+; GFX7-HSA-NEXT: s_bfe_i32 s0, s4, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s1, s4
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s4, s1, s0
+; GFX7-HSA-NEXT: s_ashr_i32 s0, s7, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s1, s7, 0x80010
+; GFX7-HSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX7-HSA-NEXT: s_and_b32 s1, s1, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s0, s1, s0
+; GFX7-HSA-NEXT: s_bfe_i32 s1, s7, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s7, s7
+; GFX7-HSA-NEXT: s_lshl_b32 s1, s1, 16
+; GFX7-HSA-NEXT: s_and_b32 s7, s7, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s1, s7, s1
+; GFX7-HSA-NEXT: s_ashr_i32 s7, s6, 24
+; GFX7-HSA-NEXT: s_bfe_i32 s18, s6, 0x80010
+; GFX7-HSA-NEXT: s_lshl_b32 s7, s7, 16
+; GFX7-HSA-NEXT: s_and_b32 s18, s18, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s7, s18, s7
+; GFX7-HSA-NEXT: s_bfe_i32 s18, s6, 0x80008
+; GFX7-HSA-NEXT: s_sext_i32_i8 s6, s6
+; GFX7-HSA-NEXT: s_lshl_b32 s18, s18, 16
+; GFX7-HSA-NEXT: s_and_b32 s6, s6, 0xffff
+; GFX7-HSA-NEXT: s_or_b32 s6, s6, s18
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s0
+; GFX7-HSA-NEXT: s_add_u32 s0, s8, 48
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: s_add_u32 s0, s8, 32
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: s_add_u32 s0, s8, 16
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s17
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s16
+; GFX7-HSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s1
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s15
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s3
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s14
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s0
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX7-HSA-NEXT: v_mov_b32_e32 v0, s13
+; GFX7-HSA-NEXT: v_mov_b32_e32 v1, s12
+; GFX7-HSA-NEXT: v_mov_b32_e32 v2, s11
+; GFX7-HSA-NEXT: v_mov_b32_e32 v3, s10
+; GFX7-HSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX7-HSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX7-HSA-NEXT: s_endpgm
+;
+; GFX8-NOHSA-LABEL: constant_sextload_v32i8_to_v32i16:
+; GFX8-NOHSA: ; %bb.0:
+; GFX8-NOHSA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NOHSA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NOHSA-NEXT: s_bfe_i32 s18, s1, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v0, 8, s1
+; GFX8-NOHSA-NEXT: s_lshr_b32 s17, s1, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s18, 0xffff, s18
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NOHSA-NEXT: s_lshr_b32 s16, s0, 16
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v2, s18, v0
+; GFX8-NOHSA-NEXT: s_bfe_i32 s1, s0, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v0, 8, s0
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s17, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v1, 8, s17
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v3, s0, v1
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s16, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v1, 8, s16
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v1, s0, v1
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s3, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v4, 8, s3
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v6, s0, v4
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s2, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v4, 8, s2
+; GFX8-NOHSA-NEXT: s_lshr_b32 s15, s3, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v4, s0, v4
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s15, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v5, 8, s15
+; GFX8-NOHSA-NEXT: s_lshr_b32 s14, s2, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v7, s0, v5
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s14, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v5, 8, s14
+; GFX8-NOHSA-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX8-NOHSA-NEXT: s_lshr_b32 s13, s5, 16
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v0, s1, v0
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v5, s0, v5
+; GFX8-NOHSA-NEXT: s_ashr_i64 s[0:1], s[4:5], 56
+; GFX8-NOHSA-NEXT: s_bfe_i32 s1, s13, 0x80000
+; GFX8-NOHSA-NEXT: s_lshl_b32 s0, s0, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s1, 0xffff, s1
+; GFX8-NOHSA-NEXT: s_or_b32 s2, s1, s0
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s5, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v8, 8, s5
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v10, s0, v8
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s4, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v8, 8, s4
+; GFX8-NOHSA-NEXT: s_lshr_b32 s12, s4, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v8, s0, v8
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s12, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v9, 8, s12
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v9, s0, v9
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s7, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v11, 8, s7
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v13, s0, v11
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s6, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v11, 8, s6
+; GFX8-NOHSA-NEXT: s_lshr_b32 s11, s7, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v11, 16, v11
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v11, s0, v11
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s11, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v12, 8, s11
+; GFX8-NOHSA-NEXT: s_lshr_b32 s10, s6, 16
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v14, s0, v12
+; GFX8-NOHSA-NEXT: s_bfe_i32 s0, s10, 0x80000
+; GFX8-NOHSA-NEXT: v_ashrrev_i16_e64 v12, 8, s10
+; GFX8-NOHSA-NEXT: s_and_b32 s0, 0xffff, s0
+; GFX8-NOHSA-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX8-NOHSA-NEXT: v_or_b32_e32 v12, s0, v12
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 48
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v16, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v15, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 32
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[15:16], v[11:14]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v13, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v12, s0
+; GFX8-NOHSA-NEXT: s_add_u32 s0, s8, 16
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v11, s2
+; GFX8-NOHSA-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[12:13], v[8:11]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v9, s1
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v8, s0
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
+; GFX8-NOHSA-NEXT: s_nop 0
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NOHSA-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NOHSA-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NOHSA-NEXT: s_endpgm
+;
+; EG-LABEL: constant_sextload_v32i8_to_v32i16:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @10
+; EG-NEXT: ALU 104, @16, KC0[], KC1[]
+; EG-NEXT: ALU 104, @121, KC0[], KC1[]
+; EG-NEXT: ALU 95, @226, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T36.XYZW, T42.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T37.XYZW, T41.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T38.XYZW, T40.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T35.XYZW, T39.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: Fetch clause starting at 10:
+; EG-NEXT: VTX_READ_128 T37.XYZW, T35.X, 16, #1
+; EG-NEXT: VTX_READ_128 T35.XYZW, T35.X, 0, #1
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: MOV * T0.Y, T16.X,
+; EG-NEXT: MOV * T35.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 16:
+; EG-NEXT: BFE_INT * T0.W, T37.X, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T0.W, PV.W, literal.x,
+; EG-NEXT: AND_INT * T1.W, T0.Y, literal.y,
+; EG-NEXT: 65535(9.183409e-41), -65536(nan)
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: MOV * T16.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T37.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T16.X, PV.W,
+; EG-NEXT: MOV T0.Y, T17.X,
+; EG-NEXT: LSHR * T0.W, T37.X, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T17.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T37.X, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: OR_INT * T36.Y, PV.W, PS,
+; EG-NEXT: MOV T17.X, PV.Y,
+; EG-NEXT: MOV T0.Y, T12.X,
+; EG-NEXT: BFE_INT * T0.W, T37.Y, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: -65536(nan), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV * T12.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T37.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T12.X, PV.W,
+; EG-NEXT: MOV T0.Y, T13.X,
+; EG-NEXT: LSHR * T0.W, T37.Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T13.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T37.Y, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: OR_INT * T36.W, PV.W, PS,
+; EG-NEXT: MOV T13.X, PV.W,
+; EG-NEXT: MOV T0.Y, T8.X,
+; EG-NEXT: BFE_INT * T0.W, T37.Z, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: -65536(nan), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV * T8.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T37.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T8.X, PV.W,
+; EG-NEXT: MOV T0.Y, T9.X,
+; EG-NEXT: LSHR * T0.W, T37.Z, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T9.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T37.Z, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: ALU clause starting at 121:
+; EG-NEXT: OR_INT * T37.Y, T1.W, T0.W,
+; EG-NEXT: MOV T9.X, PV.Y,
+; EG-NEXT: MOV T0.Y, T4.X,
+; EG-NEXT: BFE_INT * T0.W, T37.W, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: -65536(nan), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV * T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T37.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T4.X, PV.W,
+; EG-NEXT: MOV T0.Y, T5.X,
+; EG-NEXT: LSHR * T0.W, T37.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T5.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T37.W, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: OR_INT * T37.W, PV.W, PS,
+; EG-NEXT: MOV T5.X, PV.W,
+; EG-NEXT: MOV T0.Y, T32.X,
+; EG-NEXT: BFE_INT * T0.W, T35.X, 0.0, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: -65536(nan), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV * T32.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T35.X, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T32.X, PV.W,
+; EG-NEXT: MOV T0.Y, T33.X,
+; EG-NEXT: LSHR * T0.W, T35.X, literal.x, BS:VEC_120/SCL_212
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T33.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T35.X, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: OR_INT * T38.Y, PV.W, PS,
+; EG-NEXT: MOV T33.X, PV.Y,
+; EG-NEXT: MOV T0.Y, T28.X,
+; EG-NEXT: BFE_INT * T0.W, T35.Y, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: -65536(nan), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV * T28.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T35.Y, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T28.X, PV.W,
+; EG-NEXT: MOV T0.Y, T29.X,
+; EG-NEXT: LSHR * T0.W, T35.Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T29.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T35.Y, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: ALU clause starting at 226:
+; EG-NEXT: AND_INT T1.W, T0.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, T0.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: OR_INT * T38.W, PV.W, PS,
+; EG-NEXT: MOV T29.X, PV.W,
+; EG-NEXT: MOV T0.Y, T24.X,
+; EG-NEXT: BFE_INT * T0.W, T35.Z, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: -65536(nan), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV * T24.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T35.Z, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T24.X, PV.W,
+; EG-NEXT: MOV T0.Y, T25.X,
+; EG-NEXT: LSHR * T0.W, T35.Z, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T25.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ASHR * T0.W, T35.Z, literal.x,
+; EG-NEXT: 24(3.363116e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: LSHL * T0.W, PV.W, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 16(2.242078e-44)
+; EG-NEXT: OR_INT * T35.Y, PV.W, PS,
+; EG-NEXT: MOV T25.X, PV.Y,
+; EG-NEXT: MOV T0.Y, T20.X,
+; EG-NEXT: BFE_INT * T0.W, T35.W, 0.0, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: AND_INT T1.W, PV.Y, literal.x,
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.y,
+; EG-NEXT: -65536(nan), 65535(9.183409e-41)
+; EG-NEXT: OR_INT * T0.W, PV.W, PS,
+; EG-NEXT: MOV * T20.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: LSHR * T0.W, T35.W, literal.x,
+; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 65535(9.183409e-41)
+; EG-NEXT: LSHL * T0.W, PV.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV T20.X, PV.W,
+; EG-NEXT: MOV T0.Y, T21.X,
+; EG-NEXT: LSHR * T0.W, T35.W, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: BFE_INT T0.W, PV.W, 0.0, literal.x,
+; EG-NEXT: AND_INT * T1.W, PV.Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), -65536(nan)
+; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,
+; EG-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T0.W, T1.W, PV.W,
+; EG-NEXT: MOV * T21.X, PV.W,
+; EG-NEXT: MOV T0.Y, PV.X,
+; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
+; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
+; EG-NEXT: LSHR T39.X, PV.W, literal.x,
+; EG-NEXT: LSHR * T40.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: ASHR T0.W, T35.W, literal.x,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.y,
+; EG-NEXT: 24(3.363116e-44), 48(6.726233e-44)
+; EG-NEXT: LSHR T41.X, PS, literal.x,
+; EG-NEXT: AND_INT T0.Z, T0.Y, literal.y,
+; EG-NEXT: LSHL T0.W, PV.W, literal.z,
+; EG-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.w,
+; EG-NEXT: 2(2.802597e-45), 65535(9.183409e-41)
+; EG-NEXT: 16(2.242078e-44), 32(4.484155e-44)
+; EG-NEXT: LSHR T42.X, PS, literal.x,
+; EG-NEXT: OR_INT * T35.W, PV.Z, PV.W,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: MOV T21.X, PV.W,
+; EG-NEXT: MOV * T36.X, T16.X,
+; EG-NEXT: MOV * T36.Z, T12.X,
+; EG-NEXT: MOV T37.X, T8.X,
+; EG-NEXT: MOV T37.Z, T4.X, BS:VEC_120/SCL_212
+; EG-NEXT: MOV * T38.X, T32.X,
+; EG-NEXT: MOV * T38.Z, T28.X,
+; EG-NEXT: MOV T35.X, T24.X,
+; EG-NEXT: MOV * T35.Z, T20.X, BS:VEC_120/SCL_212
%load = load <32 x i8>, ptr addrspace(4) %in
%ext = sext <32 x i8> %load to <32 x i16>
store <32 x i16> %ext, ptr addrspace(1) %out
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