[llvm] da7892f - [MC] Use regunits instead of MCRegUnitIterator. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 16 04:21:38 PDT 2023
Author: Jay Foad
Date: 2023-06-16T12:21:32+01:00
New Revision: da7892f7295f31b46486418e2abf15334db96cbb
URL: https://github.com/llvm/llvm-project/commit/da7892f7295f31b46486418e2abf15334db96cbb
DIFF: https://github.com/llvm/llvm-project/commit/da7892f7295f31b46486418e2abf15334db96cbb.diff
LOG: [MC] Use regunits instead of MCRegUnitIterator. NFC.
Differential Revision: https://reviews.llvm.org/D153122
Added:
Modified:
llvm/lib/CodeGen/MachineCopyPropagation.cpp
llvm/lib/CodeGen/RDFRegisters.cpp
llvm/lib/CodeGen/RegAllocFast.cpp
llvm/lib/MC/MCRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
index d443b895d1b81..26110a1f2c233 100644
--- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp
+++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp
@@ -228,16 +228,16 @@ class CopyTracker {
return nullptr;
if (CI->second.DefRegs.size() != 1)
return nullptr;
- MCRegUnitIterator RUI(CI->second.DefRegs[0], &TRI);
- return findCopyForUnit(*RUI, TRI, true);
+ MCRegUnit RU = *TRI.regunits(CI->second.DefRegs[0]).begin();
+ return findCopyForUnit(RU, TRI, true);
}
MachineInstr *findAvailBackwardCopy(MachineInstr &I, MCRegister Reg,
const TargetRegisterInfo &TRI,
const TargetInstrInfo &TII,
bool UseCopyInstr) {
- MCRegUnitIterator RUI(Reg, &TRI);
- MachineInstr *AvailCopy = findCopyDefViaUnit(*RUI, TRI);
+ MCRegUnit RU = *TRI.regunits(Reg).begin();
+ MachineInstr *AvailCopy = findCopyDefViaUnit(RU, TRI);
if (!AvailCopy)
return nullptr;
@@ -265,9 +265,9 @@ class CopyTracker {
const TargetInstrInfo &TII, bool UseCopyInstr) {
// We check the first RegUnit here, since we'll only be interested in the
// copy if it copies the entire register anyway.
- MCRegUnitIterator RUI(Reg, &TRI);
+ MCRegUnit RU = *TRI.regunits(Reg).begin();
MachineInstr *AvailCopy =
- findCopyForUnit(*RUI, TRI, /*MustBeAvailable=*/true);
+ findCopyForUnit(RU, TRI, /*MustBeAvailable=*/true);
if (!AvailCopy)
return nullptr;
@@ -297,8 +297,8 @@ class CopyTracker {
const TargetRegisterInfo &TRI,
const TargetInstrInfo &TII,
bool UseCopyInstr) {
- MCRegUnitIterator RUI(Reg, &TRI);
- auto CI = Copies.find(*RUI);
+ MCRegUnit RU = *TRI.regunits(Reg).begin();
+ auto CI = Copies.find(RU);
if (CI == Copies.end() || !CI->second.Avail)
return nullptr;
@@ -326,8 +326,8 @@ class CopyTracker {
// Find last COPY that uses Reg.
MachineInstr *findLastSeenUseInCopy(MCRegister Reg,
const TargetRegisterInfo &TRI) {
- MCRegUnitIterator RUI(Reg, &TRI);
- auto CI = Copies.find(*RUI);
+ MCRegUnit RU = *TRI.regunits(Reg).begin();
+ auto CI = Copies.find(RU);
if (CI == Copies.end())
return nullptr;
return CI->second.LastSeenUseInCopy;
diff --git a/llvm/lib/CodeGen/RDFRegisters.cpp b/llvm/lib/CodeGen/RDFRegisters.cpp
index 8f2a12ac20b08..90520c4c3c71e 100644
--- a/llvm/lib/CodeGen/RDFRegisters.cpp
+++ b/llvm/lib/CodeGen/RDFRegisters.cpp
@@ -161,8 +161,8 @@ std::set<RegisterId> PhysicalRegisterInfo::getUnits(RegisterRef RR) const {
while (C != 0) {
unsigned T = llvm::countr_zero(C);
unsigned CR = 32 * I + T; // Clobbered reg
- for (MCRegUnitIterator U(CR, &TRI); U.isValid(); ++U)
- Units.insert(*U);
+ for (MCRegUnit U : TRI.regunits(CR))
+ Units.insert(U);
C &= ~(1u << T);
}
}
diff --git a/llvm/lib/CodeGen/RegAllocFast.cpp b/llvm/lib/CodeGen/RegAllocFast.cpp
index d9029f070a3b4..864beb8720f43 100644
--- a/llvm/lib/CodeGen/RegAllocFast.cpp
+++ b/llvm/lib/CodeGen/RegAllocFast.cpp
@@ -554,7 +554,7 @@ void RegAllocFast::reloadAtBegin(MachineBasicBlock &MBB) {
if (PhysReg == 0)
continue;
- MCRegister FirstUnit = *MCRegUnitIterator(PhysReg, TRI);
+ MCRegister FirstUnit = *TRI->regunits(PhysReg).begin();
if (RegUnitStates[FirstUnit] == regLiveIn)
continue;
@@ -624,7 +624,7 @@ bool RegAllocFast::displacePhysReg(MachineInstr &MI, MCPhysReg PhysReg) {
void RegAllocFast::freePhysReg(MCPhysReg PhysReg) {
LLVM_DEBUG(dbgs() << "Freeing " << printReg(PhysReg, TRI) << ':');
- MCRegister FirstUnit = *MCRegUnitIterator(PhysReg, TRI);
+ MCRegister FirstUnit = *TRI->regunits(PhysReg).begin();
switch (unsigned VirtReg = RegUnitStates[FirstUnit]) {
case regFree:
LLVM_DEBUG(dbgs() << '\n');
diff --git a/llvm/lib/MC/MCRegisterInfo.cpp b/llvm/lib/MC/MCRegisterInfo.cpp
index f344027d75f2b..a2c1737e2964f 100644
--- a/llvm/lib/MC/MCRegisterInfo.cpp
+++ b/llvm/lib/MC/MCRegisterInfo.cpp
@@ -134,11 +134,13 @@ int MCRegisterInfo::getCodeViewRegNum(MCRegister RegNum) const {
bool MCRegisterInfo::regsOverlap(MCRegister RegA, MCRegister RegB) const {
// Regunits are numerically ordered. Find a common unit.
- MCRegUnitIterator RUA(RegA, this);
- MCRegUnitIterator RUB(RegB, this);
+ auto RangeA = regunits(RegA);
+ MCRegUnitIterator IA = RangeA.begin(), EA = RangeA.end();
+ auto RangeB = regunits(RegB);
+ MCRegUnitIterator IB = RangeB.begin(), EB = RangeB.end();
do {
- if (*RUA == *RUB)
+ if (*IA == *IB)
return true;
- } while (*RUA < *RUB ? (++RUA).isValid() : (++RUB).isValid());
+ } while (*IA < *IB ? ++IA != EA : ++IB != EB);
return false;
}
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index ce4c0ac95c575..d63ccf426a9c6 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -329,10 +329,9 @@ SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST)
"getNumCoveredRegs() will not work with generated subreg masks!");
RegPressureIgnoredUnits.resize(getNumRegUnits());
- RegPressureIgnoredUnits.set(
- *MCRegUnitIterator(MCRegister::from(AMDGPU::M0), this));
+ RegPressureIgnoredUnits.set(*regunits(MCRegister::from(AMDGPU::M0)).begin());
for (auto Reg : AMDGPU::VGPR_HI16RegClass)
- RegPressureIgnoredUnits.set(*MCRegUnitIterator(Reg, this));
+ RegPressureIgnoredUnits.set(*regunits(Reg).begin());
// HACK: Until this is fully tablegen'd.
static llvm::once_flag InitializeRegSplitPartsFlag;
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index 92099605d04c3..3143d437e3709 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -1136,7 +1136,7 @@ MachineBasicBlock::iterator SIWholeQuadMode::prepareInsertion(
return PreferLast ? Last : First;
LiveRange &LR =
- LIS->getRegUnit(*MCRegUnitIterator(MCRegister::from(AMDGPU::SCC), TRI));
+ LIS->getRegUnit(*TRI->regunits(MCRegister::from(AMDGPU::SCC)).begin());
auto MBBE = MBB.end();
SlotIndex FirstIdx = First != MBBE ? LIS->getInstructionIndex(*First)
: LIS->getMBBEndIdx(&MBB);
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index 2b9210f102de4..ac8c395f9064f 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -1014,17 +1014,16 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
unsigned Opcode = MI.getOpcode();
// Check CC liveness if new instruction introduces a dead def of CC.
- MCRegUnitIterator CCUnit(MCRegister::from(SystemZ::CC), TRI);
SlotIndex MISlot = SlotIndex();
LiveRange *CCLiveRange = nullptr;
bool CCLiveAtMI = true;
if (LIS) {
MISlot = LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
- CCLiveRange = &LIS->getRegUnit(*CCUnit);
+ auto CCUnits = TRI->regunits(MCRegister::from(SystemZ::CC));
+ assert(range_size(CCUnits) == 1 && "CC only has one reg unit.");
+ CCLiveRange = &LIS->getRegUnit(*CCUnits.begin());
CCLiveAtMI = CCLiveRange->liveAt(MISlot);
}
- ++CCUnit;
- assert(!CCUnit.isValid() && "CC only has one reg unit.");
if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
if (!CCLiveAtMI && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
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