[PATCH] D153049: [AArch64] Try to convert vector shift operation into vector add operation

Fri Jun 16 02:44:15 PDT 2023

jaykang10 added a comment.

Thanks for kind comments. @efriedma

> I'm a little concerned this could run into issues along the lines of https://github.com/llvm/llvm-project/issues/49812 ... but I guess we currently don't try to model freeze post-isel, so it's not too likely you'll run into issues.

As far as I understand, the AArch64 target uses the default `SelectionDAGISel` code for `ISD::FREEZE` so the `ISD::FREEZE` is mapped to the `TargetOpcode::COPY`. The `ISD::UNDEF` is mapped to `TargetOpcode::IMPLICIT_DEF`. The `ProcessImplicitDefs` pass removes the `IMPLICIT_DEF` and mark the add's operands with `undef`. The register allocator assigns same register to the add's operands because it uses same virtual register. Therefore, I think both `x << 1` and `x + x` guarantees even number output.

> Oh, also, please verify we have testcases to make sure these patterns don't interfere with the formation of sshll/ushll

Yep, let me check the test cases more.

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Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:7030
+
+def : ShiftToADDPat<v16i8, FPR128, AArch64vshl>;
+def : ShiftToADDPat<v8i16, FPR128, AArch64vshl>;
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dmgreen wrote:
> AArch64vshl can be used directly in the Pat, if it is always the same, 
Yep, let me update it.

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  https://reviews.llvm.org/D153049/new/

https://reviews.llvm.org/D153049