[llvm] 4024193 - [LoongArch] Some cleanup and readability improvements to LoongArchISelLowering.cpp, NFC
Weining Lu via llvm-commits
llvm-commits at lists.llvm.org
Fri Jun 16 01:32:35 PDT 2023
Author: Weining Lu
Date: 2023-06-16T16:31:48+08:00
New Revision: 40241935e92377dab4ae966c9e4fc9f5d458b956
URL: https://github.com/llvm/llvm-project/commit/40241935e92377dab4ae966c9e4fc9f5d458b956
DIFF: https://github.com/llvm/llvm-project/commit/40241935e92377dab4ae966c9e4fc9f5d458b956.diff
LOG: [LoongArch] Some cleanup and readability improvements to LoongArchISelLowering.cpp, NFC
Added:
Modified:
llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
llvm/test/CodeGen/LoongArch/intrinsic-error.ll
llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index a714db1b049a6..d750d64b6b8b5 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -595,13 +595,12 @@ LoongArchTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
}
}
-// Helper function that emits error message for intrinsics with chain.
+// Helper function that emits error message for intrinsics with chain and return
+// merge values of a UNDEF and the chain.
static SDValue emitIntrinsicWithChainErrorMessage(SDValue Op,
StringRef ErrorMsg,
SelectionDAG &DAG) {
-
- DAG.getContext()->emitError("argument to '" + Op->getOperationName(0) + "' " +
- ErrorMsg);
+ DAG.getContext()->emitError(Op->getOperationName(0) + ": " + ErrorMsg + ".");
return DAG.getMergeValues({DAG.getUNDEF(Op.getValueType()), Op.getOperand(0)},
SDLoc(Op));
}
@@ -611,9 +610,11 @@ LoongArchTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
MVT GRLenVT = Subtarget.getGRLenVT();
- SDValue Op0 = Op.getOperand(0);
- std::string Name = Op->getOperationName(0);
- const StringRef ErrorMsgOOR = "out of range";
+ EVT VT = Op.getValueType();
+ SDValue Chain = Op.getOperand(0);
+ const StringRef ErrorMsgOOR = "argument out of range";
+ const StringRef ErrorMsgReqLA64 = "requires loongarch64";
+ const StringRef ErrorMsgReqF = "requires basic 'f' target feature";
switch (Op.getConstantOperandVal(1)) {
default:
@@ -625,115 +626,95 @@ LoongArchTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
case Intrinsic::loongarch_crcc_w_b_w:
case Intrinsic::loongarch_crcc_w_h_w:
case Intrinsic::loongarch_crcc_w_w_w:
- case Intrinsic::loongarch_crcc_w_d_w: {
- std::string Name = Op->getOperationName(0);
- DAG.getContext()->emitError(Name + " requires target: loongarch64");
- return DAG.getMergeValues({DAG.getUNDEF(Op.getValueType()), Op0}, DL);
- }
+ case Intrinsic::loongarch_crcc_w_d_w:
+ return emitIntrinsicWithChainErrorMessage(Op, ErrorMsgReqLA64, DAG);
case Intrinsic::loongarch_csrrd_w:
case Intrinsic::loongarch_csrrd_d: {
unsigned Imm = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
- if (!isUInt<14>(Imm))
- return emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG);
- return DAG.getMergeValues(
- {DAG.getNode(LoongArchISD::CSRRD, DL, GRLenVT, Op0,
- DAG.getConstant(Imm, DL, GRLenVT)),
- Op0},
- DL);
+ return !isUInt<14>(Imm)
+ ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
+ : DAG.getMergeValues(
+ {DAG.getNode(LoongArchISD::CSRRD, DL, GRLenVT, Chain,
+ DAG.getConstant(Imm, DL, GRLenVT)),
+ Chain},
+ DL);
}
case Intrinsic::loongarch_csrwr_w:
case Intrinsic::loongarch_csrwr_d: {
unsigned Imm = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
- if (!isUInt<14>(Imm))
- return emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG);
- return DAG.getMergeValues(
- {DAG.getNode(LoongArchISD::CSRWR, DL, GRLenVT, Op0, Op.getOperand(2),
- DAG.getConstant(Imm, DL, GRLenVT)),
- Op0},
- DL);
+ return !isUInt<14>(Imm)
+ ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
+ : DAG.getMergeValues(
+ {DAG.getNode(LoongArchISD::CSRWR, DL, GRLenVT, Chain,
+ Op.getOperand(2),
+ DAG.getConstant(Imm, DL, GRLenVT)),
+ Chain},
+ DL);
}
case Intrinsic::loongarch_csrxchg_w:
case Intrinsic::loongarch_csrxchg_d: {
unsigned Imm = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
- if (!isUInt<14>(Imm))
- return emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG);
- return DAG.getMergeValues(
- {DAG.getNode(LoongArchISD::CSRXCHG, DL, GRLenVT, Op0, Op.getOperand(2),
- Op.getOperand(3), DAG.getConstant(Imm, DL, GRLenVT)),
- Op0},
- DL);
+ return !isUInt<14>(Imm)
+ ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
+ : DAG.getMergeValues(
+ {DAG.getNode(LoongArchISD::CSRXCHG, DL, GRLenVT, Chain,
+ Op.getOperand(2), Op.getOperand(3),
+ DAG.getConstant(Imm, DL, GRLenVT)),
+ Chain},
+ DL);
}
case Intrinsic::loongarch_iocsrrd_d: {
- if (Subtarget.is64Bit())
- return DAG.getMergeValues(
- {DAG.getNode(
- LoongArchISD::IOCSRRD_D, DL, GRLenVT, Op0,
- DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(2))),
- Op0},
- DL);
- else {
- DAG.getContext()->emitError(
- "llvm.loongarch.crc.w.d.w requires target: loongarch64");
- return DAG.getMergeValues({DAG.getUNDEF(Op.getValueType()), Op0}, DL);
- }
+ return DAG.getMergeValues(
+ {DAG.getNode(
+ LoongArchISD::IOCSRRD_D, DL, GRLenVT, Chain,
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(2))),
+ Chain},
+ DL);
}
#define IOCSRRD_CASE(NAME, NODE) \
case Intrinsic::loongarch_##NAME: { \
- return DAG.getMergeValues( \
- {DAG.getNode(LoongArchISD::NODE, DL, GRLenVT, Op0, Op.getOperand(2)), \
- Op0}, \
- DL); \
+ return DAG.getMergeValues({DAG.getNode(LoongArchISD::NODE, DL, GRLenVT, \
+ Chain, Op.getOperand(2)), \
+ Chain}, \
+ DL); \
}
IOCSRRD_CASE(iocsrrd_b, IOCSRRD_B);
IOCSRRD_CASE(iocsrrd_h, IOCSRRD_H);
IOCSRRD_CASE(iocsrrd_w, IOCSRRD_W);
#undef IOCSRRD_CASE
case Intrinsic::loongarch_cpucfg: {
- return DAG.getMergeValues(
- {DAG.getNode(LoongArchISD::CPUCFG, DL, GRLenVT, Op0, Op.getOperand(2)),
- Op0},
- DL);
+ return DAG.getMergeValues({DAG.getNode(LoongArchISD::CPUCFG, DL, GRLenVT,
+ Chain, Op.getOperand(2)),
+ Chain},
+ DL);
}
case Intrinsic::loongarch_lddir_d: {
unsigned Imm = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
- if (!isUInt<8>(Imm)) {
- DAG.getContext()->emitError("argument to '" + Op->getOperationName(0) +
- "' out of range");
- return DAG.getMergeValues({DAG.getUNDEF(Op.getValueType()), Op0}, DL);
- }
-
- return Op;
+ return !isUInt<8>(Imm)
+ ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
+ : Op;
}
case Intrinsic::loongarch_movfcsr2gr: {
- if (!Subtarget.hasBasicF()) {
- DAG.getContext()->emitError(
- "llvm.loongarch.movfcsr2gr expects basic f target feature");
- return DAG.getMergeValues(
- {DAG.getUNDEF(Op.getValueType()), Op.getOperand(0)}, SDLoc(Op));
- }
+ if (!Subtarget.hasBasicF())
+ return emitIntrinsicWithChainErrorMessage(Op, ErrorMsgReqF, DAG);
unsigned Imm = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
- if (!isUInt<2>(Imm)) {
- DAG.getContext()->emitError("argument to '" + Op->getOperationName(0) +
- "' " + ErrorMsgOOR);
- return DAG.getMergeValues(
- {DAG.getUNDEF(Op.getValueType()), Op.getOperand(0)}, SDLoc(Op));
- }
- return DAG.getMergeValues(
- {DAG.getNode(LoongArchISD::MOVFCSR2GR, DL, Op.getValueType(),
- DAG.getConstant(Imm, DL, GRLenVT)),
- Op.getOperand(0)},
- DL);
+ return !isUInt<2>(Imm)
+ ? emitIntrinsicWithChainErrorMessage(Op, ErrorMsgOOR, DAG)
+ : DAG.getMergeValues(
+ {DAG.getNode(LoongArchISD::MOVFCSR2GR, DL, VT,
+ DAG.getConstant(Imm, DL, GRLenVT)),
+ Chain},
+ DL);
}
}
}
// Helper function that emits error message for intrinsics with void return
-// value.
+// value and return the chain.
static SDValue emitIntrinsicErrorMessage(SDValue Op, StringRef ErrorMsg,
SelectionDAG &DAG) {
- DAG.getContext()->emitError("argument to '" + Op->getOperationName(0) + "' " +
- ErrorMsg);
+ DAG.getContext()->emitError(Op->getOperationName(0) + ": " + ErrorMsg + ".");
return Op.getOperand(0);
}
@@ -741,10 +722,13 @@ SDValue LoongArchTargetLowering::lowerINTRINSIC_VOID(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
MVT GRLenVT = Subtarget.getGRLenVT();
- SDValue Op0 = Op.getOperand(0);
+ SDValue Chain = Op.getOperand(0);
uint64_t IntrinsicEnum = Op.getConstantOperandVal(1);
SDValue Op2 = Op.getOperand(2);
- const StringRef ErrorMsgOOR = "out of range";
+ const StringRef ErrorMsgOOR = "argument out of range";
+ const StringRef ErrorMsgReqLA64 = "requires loongarch64";
+ const StringRef ErrorMsgReqLA32 = "requires loongarch32";
+ const StringRef ErrorMsgReqF = "requires basic 'f' target feature";
switch (IntrinsicEnum) {
default:
@@ -752,122 +736,93 @@ SDValue LoongArchTargetLowering::lowerINTRINSIC_VOID(SDValue Op,
return SDValue();
case Intrinsic::loongarch_cacop_d:
case Intrinsic::loongarch_cacop_w: {
- if (IntrinsicEnum == Intrinsic::loongarch_cacop_d && !Subtarget.is64Bit()) {
- DAG.getContext()->emitError(
- "llvm.loongarch.cacop.d requires target: loongarch64");
- return Op.getOperand(0);
- }
- if (IntrinsicEnum == Intrinsic::loongarch_cacop_w && Subtarget.is64Bit()) {
- DAG.getContext()->emitError(
- "llvm.loongarch.cacop.w requires target: loongarch32");
- return Op.getOperand(0);
- }
+ if (IntrinsicEnum == Intrinsic::loongarch_cacop_d && !Subtarget.is64Bit())
+ return emitIntrinsicErrorMessage(Op, ErrorMsgReqLA64, DAG);
+ if (IntrinsicEnum == Intrinsic::loongarch_cacop_w && Subtarget.is64Bit())
+ return emitIntrinsicErrorMessage(Op, ErrorMsgReqLA32, DAG);
// call void @llvm.loongarch.cacop.[d/w](uimm5, rj, simm12)
unsigned Imm1 = cast<ConstantSDNode>(Op2)->getZExtValue();
- if (!isUInt<5>(Imm1))
+ int Imm2 = cast<ConstantSDNode>(Op.getOperand(4))->getSExtValue();
+ if (!isUInt<5>(Imm1) || !isInt<12>(Imm2))
return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
- SDValue Op4 = Op.getOperand(4);
- int Imm2 = cast<ConstantSDNode>(Op4)->getSExtValue();
- if (!isInt<12>(Imm2))
- return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
-
return Op;
}
-
case Intrinsic::loongarch_dbar: {
unsigned Imm = cast<ConstantSDNode>(Op2)->getZExtValue();
- if (!isUInt<15>(Imm))
- return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
-
- return DAG.getNode(LoongArchISD::DBAR, DL, MVT::Other, Op0,
- DAG.getConstant(Imm, DL, GRLenVT));
+ return !isUInt<15>(Imm)
+ ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
+ : DAG.getNode(LoongArchISD::DBAR, DL, MVT::Other, Chain,
+ DAG.getConstant(Imm, DL, GRLenVT));
}
case Intrinsic::loongarch_ibar: {
unsigned Imm = cast<ConstantSDNode>(Op2)->getZExtValue();
- if (!isUInt<15>(Imm))
- return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
-
- return DAG.getNode(LoongArchISD::IBAR, DL, MVT::Other, Op0,
- DAG.getConstant(Imm, DL, GRLenVT));
+ return !isUInt<15>(Imm)
+ ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
+ : DAG.getNode(LoongArchISD::IBAR, DL, MVT::Other, Chain,
+ DAG.getConstant(Imm, DL, GRLenVT));
}
case Intrinsic::loongarch_break: {
unsigned Imm = cast<ConstantSDNode>(Op2)->getZExtValue();
- if (!isUInt<15>(Imm))
- return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
-
- return DAG.getNode(LoongArchISD::BREAK, DL, MVT::Other, Op0,
- DAG.getConstant(Imm, DL, GRLenVT));
+ return !isUInt<15>(Imm)
+ ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
+ : DAG.getNode(LoongArchISD::BREAK, DL, MVT::Other, Chain,
+ DAG.getConstant(Imm, DL, GRLenVT));
}
case Intrinsic::loongarch_movgr2fcsr: {
- if (!Subtarget.hasBasicF()) {
- DAG.getContext()->emitError(
- "llvm.loongarch.movgr2fcsr expects basic f target feature");
- return Op0;
- }
+ if (!Subtarget.hasBasicF())
+ return emitIntrinsicErrorMessage(Op, ErrorMsgReqF, DAG);
unsigned Imm = cast<ConstantSDNode>(Op2)->getZExtValue();
- if (!isUInt<2>(Imm))
- return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
-
- return DAG.getNode(
- LoongArchISD::MOVGR2FCSR, DL, MVT::Other, Op0,
- DAG.getConstant(Imm, DL, GRLenVT),
- DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT, Op.getOperand(3)));
+ return !isUInt<2>(Imm)
+ ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
+ : DAG.getNode(LoongArchISD::MOVGR2FCSR, DL, MVT::Other, Chain,
+ DAG.getConstant(Imm, DL, GRLenVT),
+ DAG.getNode(ISD::ANY_EXTEND, DL, GRLenVT,
+ Op.getOperand(3)));
}
case Intrinsic::loongarch_syscall: {
unsigned Imm = cast<ConstantSDNode>(Op2)->getZExtValue();
- if (!isUInt<15>(Imm))
- return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
-
- return DAG.getNode(LoongArchISD::SYSCALL, DL, MVT::Other, Op0,
- DAG.getConstant(Imm, DL, GRLenVT));
+ return !isUInt<15>(Imm)
+ ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
+ : DAG.getNode(LoongArchISD::SYSCALL, DL, MVT::Other, Chain,
+ DAG.getConstant(Imm, DL, GRLenVT));
}
#define IOCSRWR_CASE(NAME, NODE) \
case Intrinsic::loongarch_##NAME: { \
SDValue Op3 = Op.getOperand(3); \
- if (Subtarget.is64Bit()) \
- return DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Op0, \
- DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), \
- DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3)); \
- else \
- return DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Op0, Op2, Op3); \
+ return Subtarget.is64Bit() \
+ ? DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Chain, \
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), \
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op3)) \
+ : DAG.getNode(LoongArchISD::NODE, DL, MVT::Other, Chain, Op2, \
+ Op3); \
}
IOCSRWR_CASE(iocsrwr_b, IOCSRWR_B);
IOCSRWR_CASE(iocsrwr_h, IOCSRWR_H);
IOCSRWR_CASE(iocsrwr_w, IOCSRWR_W);
#undef IOCSRWR_CASE
case Intrinsic::loongarch_iocsrwr_d: {
- if (Subtarget.is64Bit())
- return DAG.getNode(
- LoongArchISD::IOCSRWR_D, DL, MVT::Other, Op0, Op2,
- DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op.getOperand(3)));
- else {
- DAG.getContext()->emitError(
- "llvm.loongarch.iocsrwr.d requires target: loongarch64");
- return Op.getOperand(0);
- }
+ return !Subtarget.is64Bit()
+ ? emitIntrinsicErrorMessage(Op, ErrorMsgReqLA64, DAG)
+ : DAG.getNode(LoongArchISD::IOCSRWR_D, DL, MVT::Other, Chain,
+ Op2,
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64,
+ Op.getOperand(3)));
}
#define ASRT_LE_GT_CASE(NAME) \
case Intrinsic::loongarch_##NAME: { \
- if (!Subtarget.is64Bit()) { \
- DAG.getContext()->emitError(Op->getOperationName(0) + \
- " requires target: loongarch64"); \
- return Op.getOperand(0); \
- } \
- return Op; \
+ return !Subtarget.is64Bit() \
+ ? emitIntrinsicErrorMessage(Op, ErrorMsgReqLA64, DAG) \
+ : Op; \
}
ASRT_LE_GT_CASE(asrtle_d)
ASRT_LE_GT_CASE(asrtgt_d)
#undef ASRT_LE_GT_CASE
case Intrinsic::loongarch_ldpte_d: {
unsigned Imm = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
- if (!isUInt<8>(Imm))
- return emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG);
- if (!Subtarget.is64Bit()) {
- DAG.getContext()->emitError(Op->getOperationName(0) +
- " requires target: loongarch64");
- return Op.getOperand(0);
- }
- return Op;
+ return !Subtarget.is64Bit()
+ ? emitIntrinsicErrorMessage(Op, ErrorMsgReqLA64, DAG)
+ : !isUInt<8>(Imm) ? emitIntrinsicErrorMessage(Op, ErrorMsgOOR, DAG)
+ : Op;
}
}
}
@@ -1020,6 +975,16 @@ static SDValue customLegalizeToWOp(SDNode *N, SelectionDAG &DAG, int NumOp,
return DAG.getNode(ISD::TRUNCATE, DL, N->getValueType(0), NewRes);
}
+// Helper function that emits error message for intrinsics with chain and return
+// a UNDEF and the chain as the results.
+static void emitErrorAndReplaceIntrinsicWithChainResults(
+ SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG,
+ StringRef ErrorMsg) {
+ DAG.getContext()->emitError(N->getOperationName(0) + ": " + ErrorMsg + ".");
+ Results.push_back(DAG.getUNDEF(N->getValueType(0)));
+ Results.push_back(N->getOperand(0));
+}
+
void LoongArchTargetLowering::ReplaceNodeResults(
SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
SDLoc DL(N);
@@ -1140,41 +1105,35 @@ void LoongArchTargetLowering::ReplaceNodeResults(
break;
}
case ISD::INTRINSIC_W_CHAIN: {
- SDValue Op0 = N->getOperand(0);
- EVT VT = N->getValueType(0);
- uint64_t Op1 = N->getConstantOperandVal(1);
+ SDValue Chain = N->getOperand(0);
+ SDValue Op2 = N->getOperand(2);
MVT GRLenVT = Subtarget.getGRLenVT();
- if (Op1 == Intrinsic::loongarch_movfcsr2gr) {
+ const StringRef ErrorMsgOOR = "argument out of range";
+ const StringRef ErrorMsgReqLA64 = "requires loongarch64";
+ const StringRef ErrorMsgReqF = "requires basic 'f' target feature";
+
+ switch (N->getConstantOperandVal(1)) {
+ default:
+ llvm_unreachable("Unexpected Intrinsic.");
+ case Intrinsic::loongarch_movfcsr2gr: {
if (!Subtarget.hasBasicF()) {
- DAG.getContext()->emitError(
- "llvm.loongarch.movfcsr2gr expects basic f target feature");
- Results.push_back(DAG.getMergeValues(
- {DAG.getUNDEF(N->getValueType(0)), N->getOperand(0)}, SDLoc(N)));
- Results.push_back(N->getOperand(0));
+ emitErrorAndReplaceIntrinsicWithChainResults(N, Results, DAG,
+ ErrorMsgReqF);
return;
}
- unsigned Imm = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
+ unsigned Imm = cast<ConstantSDNode>(Op2)->getZExtValue();
if (!isUInt<2>(Imm)) {
- DAG.getContext()->emitError("argument to '" + N->getOperationName(0) +
- "' " + "out of range");
- Results.push_back(DAG.getMergeValues(
- {DAG.getUNDEF(N->getValueType(0)), N->getOperand(0)}, SDLoc(N)));
- Results.push_back(N->getOperand(0));
+ emitErrorAndReplaceIntrinsicWithChainResults(N, Results, DAG,
+ ErrorMsgOOR);
return;
}
Results.push_back(
DAG.getNode(ISD::TRUNCATE, DL, VT,
DAG.getNode(LoongArchISD::MOVFCSR2GR, SDLoc(N), MVT::i64,
DAG.getConstant(Imm, DL, GRLenVT))));
- Results.push_back(N->getOperand(0));
- return;
+ Results.push_back(Chain);
+ break;
}
- SDValue Op2 = N->getOperand(2);
- std::string Name = N->getOperationName(0);
-
- switch (Op1) {
- default:
- llvm_unreachable("Unexpected Intrinsic.");
#define CRC_CASE_EXT_BINARYOP(NAME, NODE) \
case Intrinsic::loongarch_##NAME: { \
Results.push_back(DAG.getNode( \
@@ -1183,7 +1142,7 @@ void LoongArchTargetLowering::ReplaceNodeResults(
LoongArchISD::NODE, DL, MVT::i64, \
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2), \
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3))))); \
- Results.push_back(N->getOperand(0)); \
+ Results.push_back(Chain); \
break; \
}
CRC_CASE_EXT_BINARYOP(crc_w_b_w, CRC_W_B_W)
@@ -1201,7 +1160,7 @@ void LoongArchTargetLowering::ReplaceNodeResults(
DAG.getNode(LoongArchISD::NODE, DL, MVT::i64, Op2, \
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, \
N->getOperand(3))))); \
- Results.push_back(N->getOperand(0)); \
+ Results.push_back(Chain); \
break; \
}
CRC_CASE_EXT_UNARYOP(crc_w_d_w, CRC_W_D_W)
@@ -1209,11 +1168,9 @@ void LoongArchTargetLowering::ReplaceNodeResults(
#undef CRC_CASE_EXT_UNARYOP
#define CSR_CASE(ID) \
case Intrinsic::loongarch_##ID: { \
- if (!Subtarget.is64Bit()) { \
- DAG.getContext()->emitError(Name + " requires target: loongarch64"); \
- Results.push_back(DAG.getUNDEF(VT)); \
- Results.push_back(N->getOperand(0)); \
- } \
+ if (!Subtarget.is64Bit()) \
+ emitErrorAndReplaceIntrinsicWithChainResults(N, Results, DAG, \
+ ErrorMsgReqLA64); \
break; \
}
CSR_CASE(csrrd_d);
@@ -1224,62 +1181,56 @@ void LoongArchTargetLowering::ReplaceNodeResults(
case Intrinsic::loongarch_csrrd_w: {
unsigned Imm = cast<ConstantSDNode>(Op2)->getZExtValue();
if (!isUInt<14>(Imm)) {
- DAG.getContext()->emitError("argument to '" + Name + "' out of range");
- Results.push_back(DAG.getUNDEF(VT));
- Results.push_back(N->getOperand(0));
- break;
+ emitErrorAndReplaceIntrinsicWithChainResults(N, Results, DAG,
+ ErrorMsgOOR);
+ return;
}
-
Results.push_back(
DAG.getNode(ISD::TRUNCATE, DL, VT,
- DAG.getNode(LoongArchISD::CSRRD, DL, GRLenVT, Op0,
+ DAG.getNode(LoongArchISD::CSRRD, DL, GRLenVT, Chain,
DAG.getConstant(Imm, DL, GRLenVT))));
- Results.push_back(N->getOperand(0));
+ Results.push_back(Chain);
break;
}
case Intrinsic::loongarch_csrwr_w: {
unsigned Imm = cast<ConstantSDNode>(N->getOperand(3))->getZExtValue();
if (!isUInt<14>(Imm)) {
- DAG.getContext()->emitError("argument to '" + Name + "' out of range");
- Results.push_back(DAG.getUNDEF(VT));
- Results.push_back(N->getOperand(0));
- break;
+ emitErrorAndReplaceIntrinsicWithChainResults(N, Results, DAG,
+ ErrorMsgOOR);
+ return;
}
-
Results.push_back(DAG.getNode(
ISD::TRUNCATE, DL, VT,
- DAG.getNode(LoongArchISD::CSRWR, DL, GRLenVT, Op0,
+ DAG.getNode(LoongArchISD::CSRWR, DL, GRLenVT, Chain,
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),
DAG.getConstant(Imm, DL, GRLenVT))));
- Results.push_back(N->getOperand(0));
+ Results.push_back(Chain);
break;
}
case Intrinsic::loongarch_csrxchg_w: {
unsigned Imm = cast<ConstantSDNode>(N->getOperand(4))->getZExtValue();
if (!isUInt<14>(Imm)) {
- DAG.getContext()->emitError("argument to '" + Name + "' out of range");
- Results.push_back(DAG.getUNDEF(VT));
- Results.push_back(N->getOperand(0));
- break;
+ emitErrorAndReplaceIntrinsicWithChainResults(N, Results, DAG,
+ ErrorMsgOOR);
+ return;
}
-
Results.push_back(DAG.getNode(
ISD::TRUNCATE, DL, VT,
DAG.getNode(
- LoongArchISD::CSRXCHG, DL, GRLenVT, Op0,
+ LoongArchISD::CSRXCHG, DL, GRLenVT, Chain,
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2),
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(3)),
DAG.getConstant(Imm, DL, GRLenVT))));
- Results.push_back(N->getOperand(0));
+ Results.push_back(Chain);
break;
}
#define IOCSRRD_CASE(NAME, NODE) \
case Intrinsic::loongarch_##NAME: { \
Results.push_back(DAG.getNode( \
- ISD::TRUNCATE, DL, N->getValueType(0), \
- DAG.getNode(LoongArchISD::NODE, DL, MVT::i64, Op0, \
+ ISD::TRUNCATE, DL, VT, \
+ DAG.getNode(LoongArchISD::NODE, DL, MVT::i64, Chain, \
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2)))); \
- Results.push_back(N->getOperand(0)); \
+ Results.push_back(Chain); \
break; \
}
IOCSRRD_CASE(iocsrrd_b, IOCSRRD_B);
@@ -1289,18 +1240,16 @@ void LoongArchTargetLowering::ReplaceNodeResults(
case Intrinsic::loongarch_cpucfg: {
Results.push_back(DAG.getNode(
ISD::TRUNCATE, DL, VT,
- DAG.getNode(LoongArchISD::CPUCFG, DL, GRLenVT, Op0,
+ DAG.getNode(LoongArchISD::CPUCFG, DL, GRLenVT, Chain,
DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op2))));
- Results.push_back(Op0);
+ Results.push_back(Chain);
break;
}
case Intrinsic::loongarch_lddir_d: {
if (!Subtarget.is64Bit()) {
- DAG.getContext()->emitError(N->getOperationName(0) +
- " requires target: loongarch64");
- Results.push_back(DAG.getUNDEF(VT));
- Results.push_back(Op0);
- break;
+ emitErrorAndReplaceIntrinsicWithChainResults(N, Results, DAG,
+ ErrorMsgReqLA64);
+ return;
}
break;
}
diff --git a/llvm/test/CodeGen/LoongArch/intrinsic-error.ll b/llvm/test/CodeGen/LoongArch/intrinsic-error.ll
index 882e7f693d0a7..a839ab149c333 100644
--- a/llvm/test/CodeGen/LoongArch/intrinsic-error.ll
+++ b/llvm/test/CodeGen/LoongArch/intrinsic-error.ll
@@ -1,4 +1,3 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: not llc --mtriple=loongarch32 < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 < %s 2>&1 | FileCheck %s
@@ -13,140 +12,140 @@ declare i32 @llvm.loongarch.csrwr.w(i32, i32 immarg)
declare i32 @llvm.loongarch.csrxchg.w(i32, i32, i32 immarg)
define void @dbar_imm_out_of_hi_range() #0 {
-; CHECK: argument to 'llvm.loongarch.dbar' out of range
+; CHECK: llvm.loongarch.dbar: argument out of range.
entry:
call void @llvm.loongarch.dbar(i32 32769)
ret void
}
define void @dbar_imm_out_of_lo_range() #0 {
-; CHECK: argument to 'llvm.loongarch.dbar' out of range
+; CHECK: llvm.loongarch.dbar: argument out of range.
entry:
call void @llvm.loongarch.dbar(i32 -1)
ret void
}
define void @ibar_imm_out_of_hi_range() #0 {
-; CHECK: argument to 'llvm.loongarch.ibar' out of range
+; CHECK: llvm.loongarch.ibar: argument out of range.
entry:
call void @llvm.loongarch.ibar(i32 32769)
ret void
}
define void @ibar_imm_out_of_lo_range() #0 {
-; CHECK: argument to 'llvm.loongarch.ibar' out of range
+; CHECK: llvm.loongarch.ibar: argument out of range.
entry:
call void @llvm.loongarch.ibar(i32 -1)
ret void
}
define void @break_imm_out_of_hi_range() #0 {
-; CHECK: argument to 'llvm.loongarch.break' out of range
+; CHECK: llvm.loongarch.break: argument out of range.
entry:
call void @llvm.loongarch.break(i32 32769)
ret void
}
define void @break_imm_out_of_lo_range() #0 {
-; CHECK: argument to 'llvm.loongarch.break' out of range
+; CHECK: llvm.loongarch.break: argument out of range.
entry:
call void @llvm.loongarch.break(i32 -1)
ret void
}
define void @movgr2fcsr(i32 %a) nounwind {
-; CHECK: llvm.loongarch.movgr2fcsr expects basic f target feature
+; CHECK: llvm.loongarch.movgr2fcsr: requires basic 'f' target feature.
entry:
call void @llvm.loongarch.movgr2fcsr(i32 1, i32 %a)
ret void
}
define void @movgr2fcsr_imm_out_of_hi_range(i32 %a) #0 {
-; CHECK: argument to 'llvm.loongarch.movgr2fcsr' out of range
+; CHECK: llvm.loongarch.movgr2fcsr: argument out of range.
entry:
call void @llvm.loongarch.movgr2fcsr(i32 32, i32 %a)
ret void
}
define void @movgr2fcsr_imm_out_of_lo_range(i32 %a) #0 {
-; CHECK: argument to 'llvm.loongarch.movgr2fcsr' out of range
+; CHECK: llvm.loongarch.movgr2fcsr: argument out of range.
entry:
call void @llvm.loongarch.movgr2fcsr(i32 -1, i32 %a)
ret void
}
define i32 @movfcsr2gr() nounwind {
-; CHECK: llvm.loongarch.movfcsr2gr expects basic f target feature
+; CHECK: llvm.loongarch.movfcsr2gr: requires basic 'f' target feature.
entry:
%res = call i32 @llvm.loongarch.movfcsr2gr(i32 1)
ret i32 %res
}
define i32 @movfcsr2gr_imm_out_of_hi_range() #0 {
-; CHECK: argument to 'llvm.loongarch.movfcsr2gr' out of range
+; CHECK: llvm.loongarch.movfcsr2gr: argument out of range.
entry:
%res = call i32 @llvm.loongarch.movfcsr2gr(i32 32)
ret i32 %res
}
define i32 @movfcsr2gr_imm_out_of_lo_range() #0 {
-; CHECK: argument to 'llvm.loongarch.movfcsr2gr' out of range
+; CHECK: llvm.loongarch.movfcsr2gr: argument out of range.
entry:
%res = call i32 @llvm.loongarch.movfcsr2gr(i32 -1)
ret i32 %res
}
define void @syscall_imm_out_of_hi_range() #0 {
-; CHECK: argument to 'llvm.loongarch.syscall' out of range
+; CHECK: llvm.loongarch.syscall: argument out of range.
entry:
call void @llvm.loongarch.syscall(i32 32769)
ret void
}
define void @syscall_imm_out_of_lo_range() #0 {
-; CHECK: argument to 'llvm.loongarch.syscall' out of range
+; CHECK: llvm.loongarch.syscall: argument out of range.
entry:
call void @llvm.loongarch.syscall(i32 -1)
ret void
}
define i32 @csrrd_w_imm_out_of_hi_range() #0 {
-; CHECK: argument to 'llvm.loongarch.csrrd.w' out of range
+; CHECK: llvm.loongarch.csrrd.w: argument out of range.
entry:
%0 = call i32 @llvm.loongarch.csrrd.w(i32 16384)
ret i32 %0
}
define i32 @csrrd_w_imm_out_of_lo_range() #0 {
-; CHECK: argument to 'llvm.loongarch.csrrd.w' out of range
+; CHECK: llvm.loongarch.csrrd.w: argument out of range.
entry:
%0 = call i32 @llvm.loongarch.csrrd.w(i32 -1)
ret i32 %0
}
define i32 @csrwr_w_imm_out_of_hi_range(i32 %a) #0 {
-; CHECK: argument to 'llvm.loongarch.csrwr.w' out of range
+; CHECK: llvm.loongarch.csrwr.w: argument out of range.
entry:
%0 = call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 16384)
ret i32 %0
}
define i32 @csrwr_w_imm_out_of_lo_range(i32 %a) #0 {
-; CHECK: argument to 'llvm.loongarch.csrwr.w' out of range
+; CHECK: llvm.loongarch.csrwr.w: argument out of range.
entry:
%0 = call i32 @llvm.loongarch.csrwr.w(i32 %a, i32 -1)
ret i32 %0
}
define i32 @csrxchg_w_imm_out_of_hi_range(i32 %a, i32 %b) #0 {
-; CHECK: argument to 'llvm.loongarch.csrxchg.w' out of range
+; CHECK: llvm.loongarch.csrxchg.w: argument out of range.
entry:
%0 = call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 16384)
ret i32 %0
}
define i32 @csrxchg_w_imm_out_of_lo_range(i32 %a, i32 %b) #0 {
-; CHECK: argument to 'llvm.loongarch.csrxchg.w' out of range
+; CHECK: llvm.loongarch.csrxchg.w: argument out of range.
entry:
%0 = call i32 @llvm.loongarch.csrxchg.w(i32 %a, i32 %b, i32 -1)
ret i32 %0
diff --git a/llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll b/llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
index c91516149b6d8..5302ba558940c 100644
--- a/llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
+++ b/llvm/test/CodeGen/LoongArch/intrinsic-la32-error.ll
@@ -20,147 +20,147 @@ declare i64 @llvm.loongarch.lddir.d(i64, i64 immarg)
declare void @llvm.loongarch.ldpte.d(i64, i64 immarg)
define void @cacop_arg0_out_of_hi_range(i32 %a) nounwind {
-; CHECK: argument to 'llvm.loongarch.cacop.w' out of range
+; CHECK: llvm.loongarch.cacop.w: argument out of range
entry:
call void @llvm.loongarch.cacop.w(i32 32, i32 %a, i32 1024)
ret void
}
define void @cacop_arg0_out_of_lo_range(i32 %a) nounwind {
-; CHECK: argument to 'llvm.loongarch.cacop.w' out of range
+; CHECK: llvm.loongarch.cacop.w: argument out of range
entry:
call void @llvm.loongarch.cacop.w(i32 -1, i32 %a, i32 1024)
ret void
}
define void @cacop_arg2_out_of_hi_range(i32 %a) nounwind {
-; CHECK: argument to 'llvm.loongarch.cacop.w' out of range
+; CHECK: llvm.loongarch.cacop.w: argument out of range
entry:
call void @llvm.loongarch.cacop.w(i32 1, i32 %a, i32 4096)
ret void
}
define void @cacop_arg2_out_of_lo_range(i32 %a) nounwind {
-; CHECK: argument to 'llvm.loongarch.cacop.w' out of range
+; CHECK: llvm.loongarch.cacop.w: argument out of range
entry:
call void @llvm.loongarch.cacop.w(i32 1, i32 %a, i32 -4096)
ret void
}
define i32 @crc_w_b_w(i32 %a, i32 %b) nounwind {
-; CHECK: llvm.loongarch.crc.w.b.w requires target: loongarch64
+; CHECK: llvm.loongarch.crc.w.b.w: requires loongarch64
entry:
%res = call i32 @llvm.loongarch.crc.w.b.w(i32 %a, i32 %b)
ret i32 %res
}
define i32 @crc_w_h_w(i32 %a, i32 %b) nounwind {
-; CHECK: llvm.loongarch.crc.w.h.w requires target: loongarch64
+; CHECK: llvm.loongarch.crc.w.h.w: requires loongarch64
entry:
%res = call i32 @llvm.loongarch.crc.w.h.w(i32 %a, i32 %b)
ret i32 %res
}
define i32 @crc_w_w_w(i32 %a, i32 %b) nounwind {
-; CHECK: llvm.loongarch.crc.w.w.w requires target: loongarch64
+; CHECK: llvm.loongarch.crc.w.w.w: requires loongarch64
entry:
%res = call i32 @llvm.loongarch.crc.w.w.w(i32 %a, i32 %b)
ret i32 %res
}
define i32 @crc_w_d_w(i64 %a, i32 %b) nounwind {
-; CHECK: llvm.loongarch.crc.w.d.w requires target: loongarch64
+; CHECK: llvm.loongarch.crc.w.d.w: requires loongarch64
entry:
%res = call i32 @llvm.loongarch.crc.w.d.w(i64 %a, i32 %b)
ret i32 %res
}
define i32 @crcc_w_b_w(i32 %a, i32 %b) nounwind {
-; CHECK: llvm.loongarch.crcc.w.b.w requires target: loongarch64
+; CHECK: llvm.loongarch.crcc.w.b.w: requires loongarch64
entry:
%res = call i32 @llvm.loongarch.crcc.w.b.w(i32 %a, i32 %b)
ret i32 %res
}
define i32 @crcc_w_h_w(i32 %a, i32 %b) nounwind {
-; CHECK: llvm.loongarch.crcc.w.h.w requires target: loongarch64
+; CHECK: llvm.loongarch.crcc.w.h.w: requires loongarch64
entry:
%res = call i32 @llvm.loongarch.crcc.w.h.w(i32 %a, i32 %b)
ret i32 %res
}
define i32 @crcc_w_w_w(i32 %a, i32 %b) nounwind {
-; CHECK: llvm.loongarch.crcc.w.w.w requires target: loongarch64
+; CHECK: llvm.loongarch.crcc.w.w.w: requires loongarch64
entry:
%res = call i32 @llvm.loongarch.crcc.w.w.w(i32 %a, i32 %b)
ret i32 %res
}
define i32 @crcc_w_d_w(i64 %a, i32 %b) nounwind {
-; CHECK: llvm.loongarch.crcc.w.d.w requires target: loongarch64
+; CHECK: llvm.loongarch.crcc.w.d.w: requires loongarch64
entry:
%res = call i32 @llvm.loongarch.crcc.w.d.w(i64 %a, i32 %b)
ret i32 %res
}
define i64 @csrrd_d() {
-; CHECK: llvm.loongarch.csrrd.d requires target: loongarch64
+; CHECK: llvm.loongarch.csrrd.d: requires loongarch64
entry:
%0 = tail call i64 @llvm.loongarch.csrrd.d(i32 1)
ret i64 %0
}
define i64 @csrwr_d(i64 %a) {
-; CHECK: llvm.loongarch.csrwr.d requires target: loongarch64
+; CHECK: llvm.loongarch.csrwr.d: requires loongarch64
entry:
%0 = tail call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 1)
ret i64 %0
}
define i64 @csrxchg_d(i64 %a, i64 %b) {
-; CHECK: llvm.loongarch.csrxchg.d requires target: loongarch64
+; CHECK: llvm.loongarch.csrxchg.d: requires loongarch64
entry:
%0 = tail call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 1)
ret i64 %0
}
define i64 @iocsrrd_d(i32 %a) {
-; CHECK: llvm.loongarch.iocsrrd.d requires target: loongarch64
+; CHECK: llvm.loongarch.iocsrrd.d: requires loongarch64
entry:
%0 = tail call i64 @llvm.loongarch.iocsrrd.d(i32 %a)
ret i64 %0
}
define void @iocsrwr_d(i64 %a, i32 signext %b) {
-; CHECK: llvm.loongarch.iocsrwr.d requires target: loongarch64
+; CHECK: llvm.loongarch.iocsrwr.d: requires loongarch64
entry:
tail call void @llvm.loongarch.iocsrwr.d(i64 %a, i32 %b)
ret void
}
define void @asrtle_d(i64 %a, i64 %b) {
-; CHECK: llvm.loongarch.asrtle.d requires target: loongarch64
+; CHECK: llvm.loongarch.asrtle.d: requires loongarch64
entry:
tail call void @llvm.loongarch.asrtle.d(i64 %a, i64 %b)
ret void
}
define void @asrtgt_d(i64 %a, i64 %b) {
-; CHECK: llvm.loongarch.asrtgt.d requires target: loongarch64
+; CHECK: llvm.loongarch.asrtgt.d: requires loongarch64
entry:
tail call void @llvm.loongarch.asrtgt.d(i64 %a, i64 %b)
ret void
}
define i64 @lddir_d(i64 %a) {
-; CHECK: llvm.loongarch.lddir.d requires target: loongarch64
+; CHECK: llvm.loongarch.lddir.d: requires loongarch64
entry:
%0 = tail call i64 @llvm.loongarch.lddir.d(i64 %a, i64 1)
ret i64 %0
}
define void @ldpte_d(i64 %a) {
-; CHECK: llvm.loongarch.ldpte.d requires target: loongarch64
+; CHECK: llvm.loongarch.ldpte.d: requires loongarch64
entry:
tail call void @llvm.loongarch.ldpte.d(i64 %a, i64 1)
ret void
diff --git a/llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll b/llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
index 51f6c445309ab..4716d401d9fdf 100644
--- a/llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
+++ b/llvm/test/CodeGen/LoongArch/intrinsic-la64-error.ll
@@ -8,76 +8,76 @@ declare i64 @llvm.loongarch.csrwr.d(i64, i32 immarg)
declare i64 @llvm.loongarch.csrxchg.d(i64, i64, i32 immarg)
define i64 @csrrd_d_imm_out_of_hi_range() nounwind {
-; CHECK: argument to 'llvm.loongarch.csrrd.d' out of range
+; CHECK: llvm.loongarch.csrrd.d: argument out of range
entry:
%0 = call i64 @llvm.loongarch.csrrd.d(i32 16384)
ret i64 %0
}
define i64 @csrrd_d_imm_out_of_lo_range() nounwind {
-; CHECK: argument to 'llvm.loongarch.csrrd.d' out of range
+; CHECK: llvm.loongarch.csrrd.d: argument out of range
entry:
%0 = call i64 @llvm.loongarch.csrrd.d(i32 -1)
ret i64 %0
}
define i64 @csrwr_d_imm_out_of_hi_range(i64 %a) nounwind {
-; CHECK: argument to 'llvm.loongarch.csrwr.d' out of range
+; CHECK: llvm.loongarch.csrwr.d: argument out of range
entry:
%0 = call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 16384)
ret i64 %0
}
define i64 @csrwr_d_imm_out_of_lo_range(i64 %a) nounwind {
-; CHECK: argument to 'llvm.loongarch.csrwr.d' out of range
+; CHECK: llvm.loongarch.csrwr.d: argument out of range
entry:
%0 = call i64 @llvm.loongarch.csrwr.d(i64 %a, i32 -1)
ret i64 %0
}
define i64 @csrxchg_d_imm_out_of_hi_range(i64 %a, i64 %b) nounwind {
-; CHECK: argument to 'llvm.loongarch.csrxchg.d' out of range
+; CHECK: llvm.loongarch.csrxchg.d: argument out of range
entry:
%0 = call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 16384)
ret i64 %0
}
define i64 @csrxchg_d_imm_out_of_lo_range(i64 %a, i64 %b) nounwind {
-; CHECK: argument to 'llvm.loongarch.csrxchg.d' out of range
+; CHECK: llvm.loongarch.csrxchg.d: argument out of range
entry:
%0 = call i64 @llvm.loongarch.csrxchg.d(i64 %a, i64 %b, i32 -1)
ret i64 %0
}
define void @cacop_w(i32 %a) nounwind {
-; CHECK: llvm.loongarch.cacop.w requires target: loongarch32
+; CHECK: llvm.loongarch.cacop.w: requires loongarch32
call void @llvm.loongarch.cacop.w(i32 1, i32 %a, i32 4)
ret void
}
define void @cacop_arg0_out_of_hi_range(i64 %a) nounwind {
-; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+; CHECK: llvm.loongarch.cacop.d: argument out of range
entry:
call void @llvm.loongarch.cacop.d(i64 32, i64 %a, i64 1024)
ret void
}
define void @cacop_arg0_out_of_lo_range(i64 %a) nounwind {
-; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+; CHECK: llvm.loongarch.cacop.d: argument out of range
entry:
call void @llvm.loongarch.cacop.d(i64 -1, i64 %a, i64 1024)
ret void
}
define void @cacop_arg2_out_of_hi_range(i64 %a) nounwind {
-; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+; CHECK: llvm.loongarch.cacop.d: argument out of range
entry:
call void @llvm.loongarch.cacop.d(i64 1, i64 %a, i64 4096)
ret void
}
define void @cacop_arg2_out_of_lo_range(i64 %a) nounwind {
-; CHECK: argument to 'llvm.loongarch.cacop.d' out of range
+; CHECK: llvm.loongarch.cacop.d: argument out of range
entry:
call void @llvm.loongarch.cacop.d(i64 1, i64 %a, i64 -4096)
ret void
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