[PATCH] D153110: [RISCV] Use GPR register class for RV64 ZDInx. Remove GPRF64 register class.

[Craig Topper via Phabricator via llvm-commits]

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The GPRF64 has the same spill size as GPR and is only used for RV64.
There's no real reason to have it as a separate class other than
for type inference for isel patterns in tablegen.

This patch adds f64 to the GPR register class when XLen=64. I use
f32 when XLen=32 even though we don't make use of it just to avoid
the oddity.

isel patterns have been updated to fix the lack of type infererence.

I might do similar for GPRF16 and GPRF32 or I might change them to
use an optimized spill size instead of always using XLen.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D153110

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoA.td
  llvm/lib/Target/RISCV/RISCVInstrInfoD.td
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXVentana.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZk.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td

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