[PATCH] D152669: [AIX][TLS] Generate 32-bit local-exec access code sequence

Amy Kwan via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Jun 15 13:37:15 PDT 2023


amyk marked 2 inline comments as done.
amyk added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCInstrInfo.td:3157
+let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
+    Defs = [R0,LR] in
+def GETtlsTpointer32AIX : PPCEmitTimePseudo<(outs gprc:$rD), (ins),
----------------
amyk wrote:
> Double check if these defines are correct.
We should just list LR, and potentially R3. 
I don't believe R0 is needed here.


================
Comment at: llvm/lib/Target/PowerPC/PPCTLSDynamicCall.cpp:66
             MI.getOpcode() != PPC::TLSGDAIX &&
-            MI.getOpcode() != PPC::TLSGDAIX8 && !IsPCREL) {
+            MI.getOpcode() != PPC::TLSGDAIX8 && IsNotTLSTPRelMI && !IsPCREL) {
           // Although we create ADJCALLSTACKDOWN and ADJCALLSTACKUP
----------------
kamaub wrote:
> for me personally `!IsTLSTPRelMI` less confusing.
I'll update this, thank you.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D152669/new/

https://reviews.llvm.org/D152669



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