[PATCH] D152963: [RISCV] Don't assume tail undefined if there's no policy op

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

These are pretty serious regressions. Are we always using a masked compare now?

Is the "tail agnostic" state on a compare usable by software? For mask results the spec allows undisturbed, all ones, or whatever would have been calculated if hardware ignored VL.



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Comment at: llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll:475
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
+; CHECK-NEXT:    vsetvli zero, a0, e32, m1, tu, ma
 ; CHECK-NEXT:    vadd.vv v8, v9, v10
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Was something other than compares affected that changed this test?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152963/new/

https://reviews.llvm.org/D152963