[PATCH] D152963: [RISCV] Don't assume tail undefined if there's no policy op

[Luke Lau via Phabricator via llvm-commits]

luke created this revision.
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A masked pseudo without a policy operand implicitly has a tail
undisturbed, masked undisturbed policy. Previously, doPeepholeMaskedRVV
assumed that without the policy op it was tail undefined, and discarded
the merge operand.

This patch addresses this by using tail undisturbed by default, and then
only when the merge operand is IMPLICIT_DEF can it relax it to tail
undefined.

We don't need to check if the policy operand was tail agnostic anymore,
as we can only relax this to tail undefined if IMPLICIT_DEF is set
anyway.

This fixes miscompiles for pseudos like PseudoVMFLT_*_MASK where there 
isn't a tail undefined _TU variant because the instruction is always tail 
agnostic, and so can't currently be represented. We could fix the 
regressions in the test diff by adding a pseudo to represent these.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152963

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rvv/allone-masked-to-unmasked.ll
  llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fceil-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ffloor-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fnearbyint-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround-costrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fround.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-froundeven.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ftrunc-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-nearbyint-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-peephole-vmerge-vops.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-rint-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/floor-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fnearbyint-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fnearbyint-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/frint-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fround-costrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fround-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/froundeven-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/froundeven-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ftrunc-constrained-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/ftrunc-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/half-round-conv.ll
  llvm/test/CodeGen/RISCV/rvv/nearbyint-vp.ll
  llvm/test/CodeGen/RISCV/rvv/rint-vp.ll
  llvm/test/CodeGen/RISCV/rvv/round-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll
  llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll
  llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll