[llvm] 552ee85 - [NFC] Regenerate CodeGen/AArch64/sve-streaming-mode-fixed-length-*.ll
Amaury Séchet via llvm-commits
llvm-commits at lists.llvm.org
Wed Jun 14 09:38:28 PDT 2023
Author: Amaury Séchet
Date: 2023-06-14T16:38:18Z
New Revision: 552ee85eb84bc2b44124c486f18e1af5ac749fef
URL: https://github.com/llvm/llvm-project/commit/552ee85eb84bc2b44124c486f18e1af5ac749fef
DIFF: https://github.com/llvm/llvm-project/commit/552ee85eb84bc2b44124c486f18e1af5ac749fef.diff
LOG: [NFC] Regenerate CodeGen/AArch64/sve-streaming-mode-fixed-length-*.ll
Added:
Modified:
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
index e61105361247c..c9b42e1651c8f 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-build-vector.ll
@@ -6,7 +6,7 @@ target triple = "aarch64-unknown-linux-gnu"
define void @build_vector_7_inc1_v4i1(ptr %a) #0 {
; CHECK-LABEL: build_vector_7_inc1_v4i1:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov w8, #5 // =0x5
; CHECK-NEXT: strb w8, [x0]
; CHECK-NEXT: ret
store <4 x i1> <i1 true, i1 false, i1 true, i1 false>, ptr %a, align 1
@@ -55,7 +55,7 @@ define void @build_vector_0_dec3_v8i32(ptr %a) #0 {
define void @build_vector_minus2_dec32_v4i64(ptr %a) #0 {
; CHECK-LABEL: build_vector_minus2_dec32_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #-32
+; CHECK-NEXT: mov x8, #-32 // =0xffffffffffffffe0
; CHECK-NEXT: mov z0.d, #-66 // =0xffffffffffffffbe
; CHECK-NEXT: mov z2.d, #-2 // =0xfffffffffffffffe
; CHECK-NEXT: index z1.d, #0, x8
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
index c04534390e8c3..9d59c4a0dd528 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fcopysign.ll
@@ -235,7 +235,7 @@ define void @test_copysign_v2f64_v2f32(ptr %ap, ptr %bp) #0 {
define void @test_copysign_v4f64_v4f32(ptr %ap, ptr %bp) #0 {
; CHECK-LABEL: test_copysign_v4f64_v4f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #2
+; CHECK-NEXT: mov x8, #2 // =0x2
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ld1w { z2.d }, p0/z, [x1, x8, lsl #2]
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
index a1d17ba3b94b9..ec6448f60227e 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-extend-trunc.ll
@@ -113,7 +113,7 @@ define void @fcvt_v4f16_v4f32(ptr %a, ptr %b) #0 {
define void @fcvt_v8f16_v8f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v8f16_v8f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #4
+; CHECK-NEXT: mov x8, #4 // =0x4
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0]
@@ -130,10 +130,10 @@ define void @fcvt_v8f16_v8f32(ptr %a, ptr %b) #0 {
define void @fcvt_v16f16_v16f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v16f16_v16f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #8
-; CHECK-NEXT: mov x9, #12
+; CHECK-NEXT: mov x8, #8 // =0x8
+; CHECK-NEXT: mov x9, #12 // =0xc
; CHECK-NEXT: ptrue p0.s, vl4
-; CHECK-NEXT: mov x10, #4
+; CHECK-NEXT: mov x10, #4 // =0x4
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0, x9, lsl #1]
; CHECK-NEXT: ld1h { z2.s }, p0/z, [x0, x10, lsl #1]
@@ -187,7 +187,7 @@ define void @fcvt_v2f16_v2f64(ptr %a, ptr %b) #0 {
define void @fcvt_v4f16_v4f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v4f16_v4f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #2
+; CHECK-NEXT: mov x8, #2 // =0x2
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0]
@@ -204,10 +204,10 @@ define void @fcvt_v4f16_v4f64(ptr %a, ptr %b) #0 {
define void @fcvt_v8f16_v8f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v8f16_v8f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #4
-; CHECK-NEXT: mov x9, #6
+; CHECK-NEXT: mov x8, #4 // =0x4
+; CHECK-NEXT: mov x9, #6 // =0x6
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: mov x10, #2
+; CHECK-NEXT: mov x10, #2 // =0x2
; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0, x9, lsl #1]
; CHECK-NEXT: ld1h { z2.d }, p0/z, [x0, x10, lsl #1]
@@ -230,16 +230,16 @@ define void @fcvt_v8f16_v8f64(ptr %a, ptr %b) #0 {
define void @fcvt_v16f16_v16f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v16f16_v16f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x9, #14
-; CHECK-NEXT: mov x10, #12
+; CHECK-NEXT: mov x9, #14 // =0xe
+; CHECK-NEXT: mov x10, #12 // =0xc
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: mov x8, #2
-; CHECK-NEXT: mov x11, #6
-; CHECK-NEXT: mov x12, #4
+; CHECK-NEXT: mov x8, #2 // =0x2
+; CHECK-NEXT: mov x11, #6 // =0x6
+; CHECK-NEXT: mov x12, #4 // =0x4
; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0, x9, lsl #1]
; CHECK-NEXT: ld1h { z1.d }, p0/z, [x0, x10, lsl #1]
-; CHECK-NEXT: mov x9, #8
-; CHECK-NEXT: mov x10, #10
+; CHECK-NEXT: mov x9, #8 // =0x8
+; CHECK-NEXT: mov x10, #10 // =0xa
; CHECK-NEXT: ld1h { z2.d }, p0/z, [x0, x8, lsl #1]
; CHECK-NEXT: ld1h { z3.d }, p0/z, [x0, x11, lsl #1]
; CHECK-NEXT: ld1h { z5.d }, p0/z, [x0, x12, lsl #1]
@@ -305,7 +305,7 @@ define void @fcvt_v2f32_v2f64(ptr %a, ptr %b) #0 {
define void @fcvt_v4f32_v4f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v4f32_v4f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #2
+; CHECK-NEXT: mov x8, #2 // =0x2
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, x8, lsl #2]
; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0]
@@ -322,10 +322,10 @@ define void @fcvt_v4f32_v4f64(ptr %a, ptr %b) #0 {
define void @fcvt_v8f32_v8f64(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v8f32_v8f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov x8, #4
-; CHECK-NEXT: mov x9, #6
+; CHECK-NEXT: mov x8, #4 // =0x4
+; CHECK-NEXT: mov x9, #6 // =0x6
; CHECK-NEXT: ptrue p0.d, vl2
-; CHECK-NEXT: mov x10, #2
+; CHECK-NEXT: mov x10, #2 // =0x2
; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0, x8, lsl #2]
; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0, x9, lsl #2]
; CHECK-NEXT: ld1w { z2.d }, p0/z, [x0, x10, lsl #2]
@@ -381,7 +381,7 @@ define void @fcvt_v8f32_v8f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v8f32_v8f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
-; CHECK-NEXT: mov x8, #4
+; CHECK-NEXT: mov x8, #4 // =0x4
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: fcvt z0.h, p0/m, z0.s
; CHECK-NEXT: st1h { z0.s }, p0, [x1]
@@ -430,7 +430,7 @@ define void @fcvt_v4f64_v4f16(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v4f64_v4f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
-; CHECK-NEXT: mov x8, #2
+; CHECK-NEXT: mov x8, #2 // =0x2
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: fcvt z0.h, p0/m, z0.d
; CHECK-NEXT: st1h { z0.d }, p0, [x1]
@@ -477,7 +477,7 @@ define void @fcvt_v4f64_v4f32(ptr %a, ptr %b) #0 {
; CHECK-LABEL: fcvt_v4f64_v4f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
-; CHECK-NEXT: mov x8, #2
+; CHECK-NEXT: mov x8, #2 // =0x2
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: fcvt z0.s, p0/m, z0.d
; CHECK-NEXT: st1w { z0.d }, p0, [x1]
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
index 28d24016e7d29..e10a01c2e3973 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-insert-vector-elt.ll
@@ -11,8 +11,8 @@ target triple = "aarch64-unknown-linux-gnu"
define <4 x i8> @insertelement_v4i8(<4 x i8> %op1) #0 {
; CHECK-LABEL: insertelement_v4i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #3
-; CHECK-NEXT: mov w9, #5
+; CHECK-NEXT: mov w8, #3 // =0x3
+; CHECK-NEXT: mov w9, #5 // =0x5
; CHECK-NEXT: index z2.h, #0, #1
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
@@ -28,8 +28,8 @@ define <4 x i8> @insertelement_v4i8(<4 x i8> %op1) #0 {
define <8 x i8> @insertelement_v8i8(<8 x i8> %op1) #0 {
; CHECK-LABEL: insertelement_v8i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #7
-; CHECK-NEXT: mov w9, #5
+; CHECK-NEXT: mov w8, #7 // =0x7
+; CHECK-NEXT: mov w9, #5 // =0x5
; CHECK-NEXT: index z2.b, #0, #1
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
@@ -45,8 +45,8 @@ define <8 x i8> @insertelement_v8i8(<8 x i8> %op1) #0 {
define <16 x i8> @insertelement_v16i8(<16 x i8> %op1) #0 {
; CHECK-LABEL: insertelement_v16i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #15
-; CHECK-NEXT: mov w9, #5
+; CHECK-NEXT: mov w8, #15 // =0xf
+; CHECK-NEXT: mov w9, #5 // =0x5
; CHECK-NEXT: index z2.b, #0, #1
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
@@ -62,8 +62,8 @@ define <16 x i8> @insertelement_v16i8(<16 x i8> %op1) #0 {
define <32 x i8> @insertelement_v32i8(<32 x i8> %op1) #0 {
; CHECK-LABEL: insertelement_v32i8:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #15
-; CHECK-NEXT: mov w9, #5
+; CHECK-NEXT: mov w8, #15 // =0xf
+; CHECK-NEXT: mov w9, #5 // =0x5
; CHECK-NEXT: index z3.b, #0, #1
; CHECK-NEXT: ptrue p0.b
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
@@ -80,8 +80,8 @@ define <32 x i8> @insertelement_v32i8(<32 x i8> %op1) #0 {
define <2 x i16> @insertelement_v2i16(<2 x i16> %op1) #0 {
; CHECK-LABEL: insertelement_v2i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #1
-; CHECK-NEXT: mov w9, #5
+; CHECK-NEXT: mov w8, #1 // =0x1
+; CHECK-NEXT: mov w9, #5 // =0x5
; CHECK-NEXT: index z2.s, #0, #1
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
@@ -97,8 +97,8 @@ define <2 x i16> @insertelement_v2i16(<2 x i16> %op1) #0 {
define <4 x i16> @insertelement_v4i16(<4 x i16> %op1) #0 {
; CHECK-LABEL: insertelement_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #3
-; CHECK-NEXT: mov w9, #5
+; CHECK-NEXT: mov w8, #3 // =0x3
+; CHECK-NEXT: mov w9, #5 // =0x5
; CHECK-NEXT: index z2.h, #0, #1
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
@@ -114,8 +114,8 @@ define <4 x i16> @insertelement_v4i16(<4 x i16> %op1) #0 {
define <8 x i16> @insertelement_v8i16(<8 x i16> %op1) #0 {
; CHECK-LABEL: insertelement_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #7
-; CHECK-NEXT: mov w9, #5
+; CHECK-NEXT: mov w8, #7 // =0x7
+; CHECK-NEXT: mov w9, #5 // =0x5
; CHECK-NEXT: index z2.h, #0, #1
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
@@ -131,8 +131,8 @@ define <8 x i16> @insertelement_v8i16(<8 x i16> %op1) #0 {
define <16 x i16> @insertelement_v16i16(<16 x i16> %op1) #0 {
; CHECK-LABEL: insertelement_v16i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #7
-; CHECK-NEXT: mov w9, #5
+; CHECK-NEXT: mov w8, #7 // =0x7
+; CHECK-NEXT: mov w9, #5 // =0x5
; CHECK-NEXT: index z3.h, #0, #1
; CHECK-NEXT: ptrue p0.h
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
@@ -149,8 +149,8 @@ define <16 x i16> @insertelement_v16i16(<16 x i16> %op1) #0 {
define <2 x i32> @insertelement_v2i32(<2 x i32> %op1) #0 {
; CHECK-LABEL: insertelement_v2i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #1
-; CHECK-NEXT: mov w9, #5
+; CHECK-NEXT: mov w8, #1 // =0x1
+; CHECK-NEXT: mov w9, #5 // =0x5
; CHECK-NEXT: index z2.s, #0, #1
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
@@ -166,8 +166,8 @@ define <2 x i32> @insertelement_v2i32(<2 x i32> %op1) #0 {
define <4 x i32> @insertelement_v4i32(<4 x i32> %op1) #0 {
; CHECK-LABEL: insertelement_v4i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #3
-; CHECK-NEXT: mov w9, #5
+; CHECK-NEXT: mov w8, #3 // =0x3
+; CHECK-NEXT: mov w9, #5 // =0x5
; CHECK-NEXT: index z2.s, #0, #1
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
@@ -183,12 +183,12 @@ define <4 x i32> @insertelement_v4i32(<4 x i32> %op1) #0 {
define <8 x i32> @insertelement_v8i32(ptr %a) #0 {
; CHECK-LABEL: insertelement_v8i32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #3
+; CHECK-NEXT: mov w8, #3 // =0x3
; CHECK-NEXT: index z3.s, #0, #1
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ptrue p0.s
; CHECK-NEXT: mov z2.s, w8
-; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov w8, #5 // =0x5
; CHECK-NEXT: cmpeq p0.s, p0/z, z3.s, z2.s
; CHECK-NEXT: mov z1.s, p0/m, w8
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
@@ -212,8 +212,8 @@ define <1 x i64> @insertelement_v1i64(<1 x i64> %op1) #0 {
define <2 x i64> @insertelement_v2i64(<2 x i64> %op1) #0 {
; CHECK-LABEL: insertelement_v2i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #1
-; CHECK-NEXT: mov w9, #5
+; CHECK-NEXT: mov w8, #1 // =0x1
+; CHECK-NEXT: mov w9, #5 // =0x5
; CHECK-NEXT: index z2.d, #0, #1
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
@@ -229,12 +229,12 @@ define <2 x i64> @insertelement_v2i64(<2 x i64> %op1) #0 {
define <4 x i64> @insertelement_v4i64(ptr %a) #0 {
; CHECK-LABEL: insertelement_v4i64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: index z3.d, #0, #1
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ptrue p0.d
; CHECK-NEXT: mov z2.d, x8
-; CHECK-NEXT: mov w8, #5
+; CHECK-NEXT: mov w8, #5 // =0x5
; CHECK-NEXT: cmpeq p0.d, p0/z, z3.d, z2.d
; CHECK-NEXT: mov z1.d, p0/m, x8
; CHECK-NEXT: // kill: def $q1 killed $q1 killed $z1
@@ -264,7 +264,7 @@ define <2 x half> @insertelement_v2f16(<2 x half> %op1) #0 {
define <4 x half> @insertelement_v4f16(<4 x half> %op1) #0 {
; CHECK-LABEL: insertelement_v4f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #3
+; CHECK-NEXT: mov w8, #3 // =0x3
; CHECK-NEXT: fmov h1, #5.00000000
; CHECK-NEXT: index z3.h, #0, #1
; CHECK-NEXT: ptrue p0.h
@@ -281,7 +281,7 @@ define <4 x half> @insertelement_v4f16(<4 x half> %op1) #0 {
define <8 x half> @insertelement_v8f16(<8 x half> %op1) #0 {
; CHECK-LABEL: insertelement_v8f16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #7
+; CHECK-NEXT: mov w8, #7 // =0x7
; CHECK-NEXT: fmov h1, #5.00000000
; CHECK-NEXT: index z3.h, #0, #1
; CHECK-NEXT: ptrue p0.h
@@ -299,7 +299,7 @@ define <16 x half> @insertelement_v16f16(ptr %a) #0 {
; CHECK-LABEL: insertelement_v16f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
-; CHECK-NEXT: mov w8, #7
+; CHECK-NEXT: mov w8, #7 // =0x7
; CHECK-NEXT: fmov h3, #5.00000000
; CHECK-NEXT: index z4.h, #0, #1
; CHECK-NEXT: ptrue p0.h
@@ -317,7 +317,7 @@ define <16 x half> @insertelement_v16f16(ptr %a) #0 {
define <2 x float> @insertelement_v2f32(<2 x float> %op1) #0 {
; CHECK-LABEL: insertelement_v2f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: fmov s1, #5.00000000
; CHECK-NEXT: index z3.s, #0, #1
; CHECK-NEXT: ptrue p0.s
@@ -334,7 +334,7 @@ define <2 x float> @insertelement_v2f32(<2 x float> %op1) #0 {
define <4 x float> @insertelement_v4f32(<4 x float> %op1) #0 {
; CHECK-LABEL: insertelement_v4f32:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #3
+; CHECK-NEXT: mov w8, #3 // =0x3
; CHECK-NEXT: fmov s1, #5.00000000
; CHECK-NEXT: index z3.s, #0, #1
; CHECK-NEXT: ptrue p0.s
@@ -352,7 +352,7 @@ define <8 x float> @insertelement_v8f32(ptr %a) #0 {
; CHECK-LABEL: insertelement_v8f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
-; CHECK-NEXT: mov w8, #3
+; CHECK-NEXT: mov w8, #3 // =0x3
; CHECK-NEXT: fmov s4, #5.00000000
; CHECK-NEXT: index z2.s, #0, #1
; CHECK-NEXT: ptrue p0.s
@@ -379,7 +379,7 @@ define <1 x double> @insertelement_v1f64(<1 x double> %op1) #0 {
define <2 x double> @insertelement_v2f64(<2 x double> %op1) #0 {
; CHECK-LABEL: insertelement_v2f64:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: fmov d1, #5.00000000
; CHECK-NEXT: index z3.d, #0, #1
; CHECK-NEXT: ptrue p0.d
@@ -397,7 +397,7 @@ define <4 x double> @insertelement_v4f64(ptr %a) #0 {
; CHECK-LABEL: insertelement_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
-; CHECK-NEXT: mov w8, #1
+; CHECK-NEXT: mov w8, #1 // =0x1
; CHECK-NEXT: fmov d4, #5.00000000
; CHECK-NEXT: index z2.d, #0, #1
; CHECK-NEXT: ptrue p0.d
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
index 68be9a465eaa3..6a78eaa42c061 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
@@ -728,7 +728,7 @@ define void @udiv_constantsplat_v8i32(ptr %a) #0 {
; CHECK-LABEL: udiv_constantsplat_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
-; CHECK-NEXT: mov w8, #8969
+; CHECK-NEXT: mov w8, #8969 // =0x2309
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: movk w8, #22765, lsl #16
; CHECK-NEXT: mov z2.s, w8
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
index c96b88c0a33e3..60637882f6e68 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
@@ -137,7 +137,7 @@ define void @alloc_v8f64(ptr %st_ptr) #0 {
; CHECK-NEXT: str x30, [sp, #64] // 8-byte Folded Spill
; CHECK-NEXT: mov x20, sp
; CHECK-NEXT: bl def
-; CHECK-NEXT: mov x8, #4
+; CHECK-NEXT: mov x8, #4 // =0x4
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: ld2d { z0.d, z1.d }, p0/z, [x20]
; CHECK-NEXT: ld2d { z2.d, z3.d }, p0/z, [x20, x8, lsl #3]
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
index 26b72b5300d04..13d84d31bce91 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
@@ -111,7 +111,7 @@ define <32 x i8> @masked_load_v32i8(ptr %src, <32 x i1> %mask) #0 {
; CHECK-NEXT: ptrue p0.b, vl16
; CHECK-NEXT: strb w10, [sp, #8]
; CHECK-NEXT: strb w8, [sp, #7]
-; CHECK-NEXT: mov w8, #16
+; CHECK-NEXT: mov w8, #16 // =0x10
; CHECK-NEXT: strb w4, [sp, #3]
; CHECK-NEXT: strb w3, [sp, #2]
; CHECK-NEXT: strb w2, [sp, #1]
@@ -194,7 +194,7 @@ define <16 x half> @masked_load_v16f16(ptr %src, <16 x i1> %mask) #0 {
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: uunpklo z1.h, z0.b
-; CHECK-NEXT: mov x8, #8
+; CHECK-NEXT: mov x8, #8 // =0x8
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: lsl z1.h, z1.h, #15
; CHECK-NEXT: uunpklo z0.h, z0.b
@@ -272,7 +272,7 @@ define <8 x float> @masked_load_v8f32(ptr %src, <8 x i1> %mask) #0 {
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: strh w10, [sp, #12]
; CHECK-NEXT: strh w8, [sp, #10]
-; CHECK-NEXT: mov x8, #4
+; CHECK-NEXT: mov x8, #4 // =0x4
; CHECK-NEXT: strh w9, [sp, #8]
; CHECK-NEXT: ldp d0, d1, [sp]
; CHECK-NEXT: uunpklo z0.s, z0.h
@@ -313,7 +313,7 @@ define <4 x double> @masked_load_v4f64(ptr %src, <4 x i1> %mask) #0 {
; CHECK-LABEL: masked_load_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT: mov x8, #2
+; CHECK-NEXT: mov x8, #2 // =0x2
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z1.d, z0.s
diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
index cefa8e2c594bb..acdbcd6ed9671 100644
--- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
+++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
@@ -115,7 +115,7 @@ define void @masked_store_v32i8(ptr %dst, <32 x i1> %mask) #0 {
; CHECK-NEXT: strb w9, [sp, #18]
; CHECK-NEXT: strb w10, [sp, #17]
; CHECK-NEXT: strb w8, [sp, #16]
-; CHECK-NEXT: mov w8, #16
+; CHECK-NEXT: mov w8, #16 // =0x10
; CHECK-NEXT: ldp q0, q1, [sp]
; CHECK-NEXT: lsl z0.b, z0.b, #7
; CHECK-NEXT: asr z0.b, z0.b, #7
@@ -193,7 +193,7 @@ define void @masked_store_v16f16(ptr %dst, <16 x i1> %mask) #0 {
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: mov z1.d, z0.d
-; CHECK-NEXT: mov x8, #8
+; CHECK-NEXT: mov x8, #8 // =0x8
; CHECK-NEXT: ext z1.b, z1.b, z0.b, #8
; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpklo z1.h, z1.b
@@ -251,7 +251,7 @@ define void @masked_store_v8f32(ptr %dst, <8 x i1> %mask) #0 {
; CHECK-NEXT: strh w9, [sp, #8]
; CHECK-NEXT: fmov w9, s0
; CHECK-NEXT: ldr d1, [sp, #8]
-; CHECK-NEXT: mov x8, #4
+; CHECK-NEXT: mov x8, #4 // =0x4
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: fmov w10, s2
; CHECK-NEXT: uunpklo z0.s, z1.h
@@ -298,7 +298,7 @@ define void @masked_store_v4f64(ptr %dst, <4 x i1> %mask) #0 {
; CHECK-LABEL: masked_store_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
-; CHECK-NEXT: mov x8, #2
+; CHECK-NEXT: mov x8, #2 // =0x2
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z1.d, z0.s
More information about the llvm-commits
mailing list