[llvm] cde91c6 - [RISCV] Canonicalize towards vid w/passthrough representation

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2023-06-14T09:36:45-07:00
New Revision: cde91c611d3232e4174e2b45b73d4aba1b772115

URL: https://github.com/llvm/llvm-project/commit/cde91c611d3232e4174e2b45b73d4aba1b772115
DIFF: https://github.com/llvm/llvm-project/commit/cde91c611d3232e4174e2b45b73d4aba1b772115.diff

LOG: [RISCV] Canonicalize towards vid w/passthrough representation

This patch teaches performCombineVMergeAndVOps how to handle a True instruction (the one being merged into) which is a _TU psuedo, but with an implicit_def passthrough operand.  These are semantically equivalent to the unsuffixed "TA" psuedos, and we can hnndle them as such.

This is a companion to D152380, and demonstrates the unsuffixed to _TA pseudo transition for a non-VMERGE case. Between the two of them, these should cover all the changes required to the post-ISEL combines, and other arithmetic-like instructions should be just TD changes.

See https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structure-policy-variants/71295 for context on the patch series.

Differential Revision: https://reviews.llvm.org/D152740

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index 69c8419a932b5..ccd0acde29745 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3291,14 +3291,21 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N, bool IsTA) {
   const RISCV::RISCVMaskedPseudoInfo *Info =
       RISCV::lookupMaskedIntrinsicByUnmaskedTA(TrueOpc);
   if (!Info && HasTiedDest) {
-    Info = RISCV::getMaskedPseudoInfo(TrueOpc);
-    IsMasked = true;
+    Info = RISCV::lookupMaskedIntrinsicByUnmaskedTU(TrueOpc);
+    if (Info && !isImplicitDef(True->getOperand(0)))
+      // We only support the TA form of the _TU pseudos
+      return false;
+    // FIXME: Expect undef operand here?
+    if (!Info) {
+      Info = RISCV::getMaskedPseudoInfo(TrueOpc);
+      IsMasked = true;
+    }
   }
 
   if (!Info)
     return false;
 
-  if (HasTiedDest) {
+  if (HasTiedDest && !isImplicitDef(True->getOperand(0))) {
     // The vmerge instruction must be TU.
     // FIXME: This could be relaxed, but we need to handle the policy for the
     // resulting op correctly.
@@ -3387,14 +3394,14 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N, bool IsTA) {
 
   SmallVector<SDValue, 8> Ops;
   if (IsMasked) {
-    Ops.append(True->op_begin(), True->op_begin() + TrueVLIndex);
+    Ops.push_back(False);
+    Ops.append(True->op_begin() + 1, True->op_begin() + TrueVLIndex);
     Ops.append({VL, /* SEW */ True.getOperand(TrueVLIndex + 1)});
     Ops.push_back(PolicyOp);
     Ops.append(True->op_begin() + TrueVLIndex + 3, True->op_end());
   } else {
-    if (!HasTiedDest)
-      Ops.push_back(False);
-    Ops.append(True->op_begin(), True->op_begin() + TrueVLIndex);
+    Ops.push_back(False);
+    Ops.append(True->op_begin() + HasTiedDest, True->op_begin() + TrueVLIndex);
     Ops.append({Mask, VL, /* SEW */ True.getOperand(TrueVLIndex + 1)});
     Ops.push_back(PolicyOp);
 

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 261b068035890..35c334a287c67 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -506,6 +506,11 @@ def lookupMaskedIntrinsicByUnmaskedTA : SearchIndex {
   let Key = ["UnmaskedPseudo"];
 }
 
+def lookupMaskedIntrinsicByUnmaskedTU : SearchIndex {
+  let Table = RISCVMaskedPseudosTable;
+  let Key = ["UnmaskedTUPseudo"];
+}
+
 def RISCVVLETable : GenericTable {
   let FilterClass = "RISCVVLE";
   let CppTypeName = "VLEPseudo";
@@ -4306,8 +4311,8 @@ multiclass VPatNullaryV<string intrinsic, string instruction>
       def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
                             (vti.Vector undef),
                             VLOpFrag)),
-                            (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX)
-                            GPR:$vl, vti.Log2SEW)>;
+                            (!cast<Instruction>(instruction#"_V_" # vti.LMul.MX # "_TU")
+                            (vti.Vector (IMPLICIT_DEF)), GPR:$vl, vti.Log2SEW)>;
       def : Pat<(vti.Vector (!cast<Intrinsic>(intrinsic)
                             (vti.Vector vti.RegClass:$merge),
                             VLOpFrag)),