[PATCH] D152821: [RISCV] Add support for Xcvmac extension in CV32E40P

[QIHAN CAI via Phabricator via llvm-commits]

realqhc updated this revision to Diff 531229.
realqhc added a comment.

address reviewers' concerns, restrict the instructions to RV32, remove unnecessary emit=0 and add -riscv-no-aliases for tests instead.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152821/new/

https://reviews.llvm.org/D152821

Files:
  llvm/docs/RISCVUsage.rst
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/RISCVFeatures.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXCvmac.td
  llvm/test/MC/RISCV/corev/XCvmac-invalid.s
  llvm/test/MC/RISCV/corev/XCvmac.s

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