[PATCH] D152821: [RISCV] Add support for Xcvmac extension in CV32E40P

[QIHAN CAI via Phabricator via llvm-commits]

realqhc added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXCvmac.td:119
+  // Signed 16x16 bit muls
+  def : InstAlias<"cv.muls $rd1, $rs1, $rs2", (CV_MULSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0), 0>;
+  def : InstAlias<"cv.mulhhs $rd1, $rs1, $rs2", (CV_MULHHSN GPR:$rd1, GPR:$rs1, GPR:$rs2, 0), 0>;
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craig.topper wrote:
> Why `Emit = 0` here?
This is the current design for Core-V's GAS implementation. Also, setting it to non-zero may cause issue with cv.mulsn ..., ..., 0 but that may not exist apart from some test cases. 


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  https://reviews.llvm.org/D152821/new/

https://reviews.llvm.org/D152821