[PATCH] D152832: [AMDGPU] Fix register class for a subreg in GCNRewritePartialRegUses.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp:100-103
+  /// Try to find register class containing registers of minimal size (but not
+  /// less than RegNumBits) for a given register class RC and used subregs as
+  /// keys in SubRegs by shifting offsets of the subregs by RShift value to the
+  /// right. If found return the resulting regclass and new shifted subregs as
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This comment is a run on sentence I'm having trouble following


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Comment at: llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp:317
   if (CoverSubreg != AMDGPU::NoSubRegister)
-    return getRegClassWithShiftedSubregs(RC, Offset, CoverSubreg, SubRegs);
+    return getRegClassWithShiftedSubregs(RC, Offset, End - Offset, CoverSubreg,
+                                         SubRegs);
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Why do you need the size? In the unknown case you still have a class from the vreg 


Repository:
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  https://reviews.llvm.org/D152832/new/

https://reviews.llvm.org/D152832