[PATCH] D152832: [AMDGPU] Fix register class for a subreg in GCNRewritePartialRegUses.

[Valery Pykhtin via Phabricator via llvm-commits]

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1. Improved code that deduces register class from instruction definitions.

Previously if some instruction didn't contain a reg class for an operand it was
condsidered as no information on register class even if other instructions
specified the class.

2. Added check on required size of resulting register because in some cases

classes with smaller registers had been selected (for example VReg_1).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152832

Files:
  llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp
  llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses-gen.mir
  llvm/test/CodeGen/AMDGPU/rewrite-partial-reg-uses.mir

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