[PATCH] D143898: [CodeGenPrepare] Relax conditions for folding addressing mode into loads/stores

[Momchil Velikov via Phabricator via llvm-commits]

chill added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:24528
+
+  if (ArgNo > 7 || AM.BaseGV || !AM.HasBaseReg)
+    return false;
----------------
efriedma wrote:
> Counting arguments like this won't do what you want if there are arguments which are passed in multiple registers.
Indeed.

For now, I'm proposing a different approach, doing the transformation entirely in `MachineSink`.
The relevant review is https://reviews.llvm.org/D152828

If it doesn't fly, I'll come back to this review and think how to solve this above issue.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D143898/new/

https://reviews.llvm.org/D143898