[PATCH] D147678: [LegalizeTypes][AArch64] Use scalar_to_vector to eliminate bitcast

Tue Jun 13 06:14:41 PDT 2023

dmgreen added a comment.

In D147678#4416899 <https://reviews.llvm.org/D147678#4416899>, @Allen wrote:

> I add a comment on **https://github.com/llvm/llvm-project/issues/61638#issuecomment-1495316614** ,  these issue can produce efficient assemble (only a **fmov s0, w0** as expected), but there is too many tests affected.
> so I'm not sure if this is a direction for further optimization?

The `<2 x i16>` across a call boundary needs to be treated like a `<2 x i32>` (as that is a legal type). To do differently would be an ABI break, which would be a lot of work. There are certainly places where we could be better for small vector types, but I don't think a `fmov s0, w0` would be valid on it's own.  My comment was more about the `bitcast i16 %word to <2 x i8>` case which is moving back and forth between gpr and vectors more than it needs to. That can be improved in other patches though.

By the way it might be worth making sure the tests cover BE too. I believe they are OK, but it would be a good idea to make sure it is tested.

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https://reviews.llvm.org/D147678