[PATCH] D147678: [LegalizeTypes][AArch64] Use scalar_to_vector to eliminate bitcast

[Allen zhong via Phabricator via llvm-commits]

Allen marked 3 inline comments as done.
Allen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22894-22897
+  [[maybe_unused]] EVT SrcVT = Op.getValueType();
+
+  assert(SrcVT.getSizeInBits() == VT.getSizeInBits() &&
+         "Expected same size for bitcast!");
----------------
paulwalker-arm wrote:
> Is this necessary given it is a requirement of `ISD::BITCAST`? By which I mean you shouldn't need to manually verify the DAG is valid here? I'd expect `getNode()` to catch such errors.
deleted assert, thanks


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22902
+  SDValue CastVal = DAG.getNode(ISD::BITCAST, DL, CastVT, Vec);
+  SDValue IdxZero = DAG.getConstant(0, DL, MVT::i64);
+  Results.push_back(
----------------
paulwalker-arm wrote:
> Please can you use `getVectorIdxConstant` here rather than hardwiring `MVT::i64`?
Apply your comment, thanks


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D147678/new/

https://reviews.llvm.org/D147678