[PATCH] D151916: [DAG] Peek through any trunc/zext when combining select into shifts.
Amaury SECHET via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 13 04:07:20 PDT 2023
deadalnix updated this revision to Diff 530856.
deadalnix added a comment.
rebase again
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D151916/new/
https://reviews.llvm.org/D151916
Files:
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/test/CodeGen/X86/dagcombine-select.ll
Index: llvm/test/CodeGen/X86/dagcombine-select.ll
===================================================================
--- llvm/test/CodeGen/X86/dagcombine-select.ll
+++ llvm/test/CodeGen/X86/dagcombine-select.ll
@@ -194,12 +194,10 @@
define i32 @shl_constant_sel_constants(i1 %cond) {
; CHECK-LABEL: shl_constant_sel_constants:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %ecx
-; CHECK-NEXT: andb $1, %cl
-; CHECK-NEXT: xorb $3, %cl
-; CHECK-NEXT: movl $1, %eax
-; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
-; CHECK-NEXT: shll %cl, %eax
+; CHECK-NEXT: notb %dil
+; CHECK-NEXT: movzbl %dil, %eax
+; CHECK-NEXT: andl $1, %eax
+; CHECK-NEXT: leal 4(,%rax,4), %eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i32 2, i32 3
%bo = shl i32 1, %sel
@@ -209,12 +207,9 @@
define i32 @lshr_constant_sel_constants(i1 %cond) {
; CHECK-LABEL: lshr_constant_sel_constants:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %ecx
-; CHECK-NEXT: andb $1, %cl
-; CHECK-NEXT: xorb $3, %cl
-; CHECK-NEXT: movl $64, %eax
-; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
-; CHECK-NEXT: shrl %cl, %eax
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT: andl $1, %edi
+; CHECK-NEXT: leal 8(,%rdi,8), %eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i32 2, i32 3
%bo = lshr i32 64, %sel
@@ -224,12 +219,10 @@
define i32 @ashr_constant_sel_constants(i1 %cond) {
; CHECK-LABEL: ashr_constant_sel_constants:
; CHECK: # %bb.0:
-; CHECK-NEXT: movl %edi, %ecx
-; CHECK-NEXT: andb $1, %cl
-; CHECK-NEXT: xorb $3, %cl
-; CHECK-NEXT: movl $128, %eax
-; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
-; CHECK-NEXT: shrl %cl, %eax
+; CHECK-NEXT: # kill: def $edi killed $edi def $rdi
+; CHECK-NEXT: andl $1, %edi
+; CHECK-NEXT: shll $4, %edi
+; CHECK-NEXT: leal 16(%rdi), %eax
; CHECK-NEXT: retq
%sel = select i1 %cond, i32 2, i32 3
%bo = ashr i32 128, %sel
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2482,6 +2482,22 @@
if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse()) {
SelOpNo = 1;
Sel = BO->getOperand(1);
+
+ // Peek through any trunc/zext to shift amount type.
+ if ((BinOpcode == ISD::SHL || BinOpcode == ISD::SRA ||
+ BinOpcode == ISD::SRL) && Sel.hasOneUse()) {
+ // This is valid when the truncated bits of x are already zero.
+ SDValue Op;
+ KnownBits Known;
+ if (isTruncateOf(DAG, Sel, Op, Known)) {
+ APInt TruncatedBits =
+ APInt::getBitsSet(Op.getScalarValueSizeInBits(),
+ Sel.getScalarValueSizeInBits(),
+ Op.getScalarValueSizeInBits());
+ if (TruncatedBits.isSubsetOf(Known.Zero))
+ Sel = Op;
+ }
+ }
}
if (Sel.getOpcode() != ISD::SELECT || !Sel.hasOneUse())
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