[PATCH] D152370: [Intrinsic] Introduce reduction intrinsics for minimum/maximum

Mon Jun 12 14:08:36 PDT 2023

anna added inline comments.

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Comment at: llvm/test/CodeGen/AArch64/vecreduce-fmaximum.ll:20
+; CHECK-NEXT:    ret
+  %b = call nnan half @llvm.vector.reduce.fmaximum.v1f16(<1 x half> %a)
+  ret half %b
----------------
anna wrote:
> nikic wrote:
> > Why do these all have `nnan` fmf?
> I'll change this to (nnan for test we actually code generate v16f32 and one without for the same test) and remove for the rest of the tests. 
removed nnan from all. they don't make a difference in the generated assembly. I thought code would be optimized for the nnan case. 

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152370/new/

https://reviews.llvm.org/D152370