[llvm] 22c17c6 - [GlobalIsel][X86] Move G_FCMP getActionDefinitionsBuilder out of setLegalizerInfo64bit and add 32-bit support

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Mon Jun 12 04:18:54 PDT 2023


Author: Simon Pilgrim
Date: 2023-06-12T12:18:37+01:00
New Revision: 22c17c6a1f732545a94bb5cfdf57f71b68b493c9

URL: https://github.com/llvm/llvm-project/commit/22c17c6a1f732545a94bb5cfdf57f71b68b493c9
DIFF: https://github.com/llvm/llvm-project/commit/22c17c6a1f732545a94bb5cfdf57f71b68b493c9.diff

LOG: [GlobalIsel][X86] Move G_FCMP getActionDefinitionsBuilder out of setLegalizerInfo64bit and add 32-bit support

We were using x86_64-only support as a SSE2 proxy

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86LegalizerInfo.cpp
    llvm/test/CodeGen/X86/GlobalISel/legalize-fcmp.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
index 4ff45417e705f..9bc9c6f518224 100644
--- a/llvm/lib/Target/X86/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/X86LegalizerInfo.cpp
@@ -319,6 +319,16 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
                (HasAVX512 && typeInSet(0, {v16s32, v8s64})(Query));
       });
 
+  // fp comparison
+  getActionDefinitionsBuilder(G_FCMP)
+      .legalIf([=](const LegalityQuery &Query) {
+        return (HasSSE1 && typePairInSet(0, 1, {{s8, s32}})(Query)) ||
+               (HasSSE2 && typePairInSet(0, 1, {{s8, s64}})(Query));
+      })
+      .clampScalar(0, s8, s8)
+      .clampScalar(1, s32, HasSSE2 ? s64 : s32)
+      .widenScalarToNextPow2(1);
+
   // fp extension
   getActionDefinitionsBuilder(G_FPEXT).legalIf([=](const LegalityQuery &Query) {
     return (HasSSE2 && typePairInSet(0, 1, {{s64, s32}})(Query)) ||
@@ -456,12 +466,6 @@ void X86LegalizerInfo::setLegalizerInfo64bit() {
       .clampScalar(0, s32, s64)
       .widenScalarToNextPow2(1);
 
-  getActionDefinitionsBuilder(G_FCMP)
-      .legalForCartesianProduct({s8}, {s32, s64})
-      .clampScalar(0, s8, s8)
-      .clampScalar(1, s32, s64)
-      .widenScalarToNextPow2(1);
-
   // Merge/Unmerge
   LegacyInfo.setAction({G_MERGE_VALUES, s128}, LegacyLegalizeActions::Legal);
   LegacyInfo.setAction({G_UNMERGE_VALUES, 1, s128},

diff  --git a/llvm/test/CodeGen/X86/GlobalISel/legalize-fcmp.mir b/llvm/test/CodeGen/X86/GlobalISel/legalize-fcmp.mir
index 3efb395b28b37..2b861c714d607 100644
--- a/llvm/test/CodeGen/X86/GlobalISel/legalize-fcmp.mir
+++ b/llvm/test/CodeGen/X86/GlobalISel/legalize-fcmp.mir
@@ -1,5 +1,8 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
 # RUN: llc -mtriple=x86_64-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+# RUN: llc -mtriple=i386-linux-gnu -mattr=+sse2 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s
+
+# TODO: x87/SSE1-only test coverage
 
 --- |
 


        


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