[llvm] e21df82 - [AVR] Optimize 8-bit rotation when rotation bits >= 4

[Ben Shi via llvm-commits]

Author: Ben Shi
Date: 2023-06-11T08:36:22+08:00
New Revision: e21df8296d09aff68039520ca1ab7dc4907922a2

URL: https://github.com/llvm/llvm-project/commit/e21df8296d09aff68039520ca1ab7dc4907922a2
DIFF: https://github.com/llvm/llvm-project/commit/e21df8296d09aff68039520ca1ab7dc4907922a2.diff

LOG: [AVR] Optimize 8-bit rotation when rotation bits >= 4

Fixes https://github.com/llvm/llvm-project/issues/63100

Reviewed By: aykevl, Patryk27, jacquesguan

Differential Revision: https://reviews.llvm.org/D152130

Added: 
    

Modified: 
    llvm/lib/Target/AVR/AVRISelLowering.cpp
    llvm/test/CodeGen/AVR/rotate.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index 606e70b32f170..d0314fb9539fc 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -427,6 +427,21 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
       Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
                            DAG.getConstant(7, dl, VT));
       ShiftAmount = 0;
+    } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 7) {
+      // Optimize left rotation 7 bits to right rotation 1 bit.
+      Victim =
+          DAG.getNode(AVRISD::ROR, dl, VT, Victim, DAG.getConstant(1, dl, VT));
+      ShiftAmount = 0;
+    } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 7) {
+      // Optimize right rotation 7 bits to left rotation 1 bit.
+      Victim =
+          DAG.getNode(AVRISD::ROL, dl, VT, Victim, DAG.getConstant(1, dl, VT));
+      ShiftAmount = 0;
+    } else if ((Op.getOpcode() == ISD::ROTR || Op.getOpcode() == ISD::ROTL) &&
+               ShiftAmount >= 4) {
+      // Optimize left/right rotation with the SWAP instruction.
+      Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
+      ShiftAmount -= 4;
     }
   } else if (VT.getSizeInBits() == 16) {
     if (Op.getOpcode() == ISD::SRA)

diff  --git a/llvm/test/CodeGen/AVR/rotate.ll b/llvm/test/CodeGen/AVR/rotate.ll
index bf31fac0ed383..938b64f494376 100644
--- a/llvm/test/CodeGen/AVR/rotate.ll
+++ b/llvm/test/CodeGen/AVR/rotate.ll
@@ -30,14 +30,7 @@ start:
 define i8 @rotl8_5(i8 %x) {
 ; CHECK-LABEL: rotl8_5:
 ; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
+; CHECK-NEXT:    swap r24
 ; CHECK-NEXT:    lsl r24
 ; CHECK-NEXT:    adc r24, r1
 ; CHECK-NEXT:    ret
@@ -49,20 +42,9 @@ start:
 define i8 @rotl8_7(i8 %x) {
 ; CHECK-LABEL: rotl8_7:
 ; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
+; CHECK-NEXT:    bst r24, 0
+; CHECK-NEXT:    ror r24
+; CHECK-NEXT:    bld r24, 7
 ; CHECK-NEXT:    ret
 start:
   %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 7)
@@ -121,18 +103,7 @@ start:
 define i8 @rotr8_5(i8 %x) {
 ; CHECK-LABEL: rotr8_5:
 ; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
+; CHECK-NEXT:    swap r24
 ; CHECK-NEXT:    bst r24, 0
 ; CHECK-NEXT:    ror r24
 ; CHECK-NEXT:    bld r24, 7
@@ -145,27 +116,8 @@ start:
 define i8 @rotr8_7(i8 %x) {
 ; CHECK-LABEL: rotr8_7:
 ; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
+; CHECK-NEXT:    lsl r24
+; CHECK-NEXT:    adc r24, r1
 ; CHECK-NEXT:    ret
 start:
   %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 7)