[llvm] 71d90f3 - [AVR] Optimize 8-bit rotation when rotation bits == 3

[Ben Shi via llvm-commits]

Author: Ben Shi
Date: 2023-06-11T08:41:47+08:00
New Revision: 71d90f310867c78532c5bdb9ba553859910ee67e

URL: https://github.com/llvm/llvm-project/commit/71d90f310867c78532c5bdb9ba553859910ee67e
DIFF: https://github.com/llvm/llvm-project/commit/71d90f310867c78532c5bdb9ba553859910ee67e.diff

LOG: [AVR] Optimize 8-bit rotation when rotation bits == 3

Fixes https://github.com/llvm/llvm-project/issues/63100

Reviewed By: aykevl

Differential Revision: https://reviews.llvm.org/D152365

Added: 
    

Modified: 
    llvm/lib/Target/AVR/AVRISelLowering.cpp
    llvm/test/CodeGen/AVR/rotate.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/AVR/AVRISelLowering.cpp b/llvm/lib/Target/AVR/AVRISelLowering.cpp
index d0314fb9539fc..ee0693cd01037 100644
--- a/llvm/lib/Target/AVR/AVRISelLowering.cpp
+++ b/llvm/lib/Target/AVR/AVRISelLowering.cpp
@@ -427,6 +427,18 @@ SDValue AVRTargetLowering::LowerShifts(SDValue Op, SelectionDAG &DAG) const {
       Victim = DAG.getNode(AVRISD::ASRBN, dl, VT, Victim,
                            DAG.getConstant(7, dl, VT));
       ShiftAmount = 0;
+    } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 3) {
+      // Optimize left rotation 3 bits to swap then right rotation 1 bit.
+      Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
+      Victim =
+          DAG.getNode(AVRISD::ROR, dl, VT, Victim, DAG.getConstant(1, dl, VT));
+      ShiftAmount = 0;
+    } else if (Op.getOpcode() == ISD::ROTR && ShiftAmount == 3) {
+      // Optimize right rotation 3 bits to swap then left rotation 1 bit.
+      Victim = DAG.getNode(AVRISD::SWAP, dl, VT, Victim);
+      Victim =
+          DAG.getNode(AVRISD::ROL, dl, VT, Victim, DAG.getConstant(1, dl, VT));
+      ShiftAmount = 0;
     } else if (Op.getOpcode() == ISD::ROTL && ShiftAmount == 7) {
       // Optimize left rotation 7 bits to right rotation 1 bit.
       Victim =

diff  --git a/llvm/test/CodeGen/AVR/rotate.ll b/llvm/test/CodeGen/AVR/rotate.ll
index 938b64f494376..79ff7928b3a39 100644
--- a/llvm/test/CodeGen/AVR/rotate.ll
+++ b/llvm/test/CodeGen/AVR/rotate.ll
@@ -15,12 +15,10 @@ start:
 define i8 @rotl8_3(i8 %x) {
 ; CHECK-LABEL: rotl8_3:
 ; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
-; CHECK-NEXT:    lsl r24
-; CHECK-NEXT:    adc r24, r1
+; CHECK-NEXT:    swap r24
+; CHECK-NEXT:    bst r24, 0
+; CHECK-NEXT:    ror r24
+; CHECK-NEXT:    bld r24, 7
 ; CHECK-NEXT:    ret
 start:
   %0 = call i8 @llvm.fshl.i8(i8 %x, i8 %x, i8 3)
@@ -85,15 +83,9 @@ start:
 define i8 @rotr8_3(i8 %x) {
 ; CHECK-LABEL: rotr8_3:
 ; CHECK:       ; %bb.0: ; %start
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
-; CHECK-NEXT:    bst r24, 0
-; CHECK-NEXT:    ror r24
-; CHECK-NEXT:    bld r24, 7
+; CHECK-NEXT:    swap r24
+; CHECK-NEXT:    lsl r24
+; CHECK-NEXT:    adc r24, r1
 ; CHECK-NEXT:    ret
 start:
   %0 = call i8 @llvm.fshr.i8(i8 %x, i8 %x, i8 3)