[PATCH] D152380: [WIP][RISCV] Canonicalize towards vmerge w/passthrough representation

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp:3442
-
-    auto IsVMergeTA = [](unsigned Opcode) {
-      return Opcode == RISCV::PseudoVMERGE_VVM_MF8 ||
----------------
Note - I'm removing the TA support entirely here, but given there's still some intrinsic users, we should probably restructure to add recognition of the implicit_def operand to _TU case without dropping the TA support.  This will make this change reviewable (though sadly not really testable) on it's own.  


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Comment at: llvm/test/CodeGen/RISCV/rvv/vector-splice.ll:12
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vmv1r.v v9, v0
 ; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
----------------
Note - This change (and others like it) look concerning.  I dug far enough in to this to be fairly sure this is a problem with pre-RA-sched, but haven't yet fully isolated the cause.  I suspect there's some missing special casing for IMPLICIT_DEF somewhere, but I haven't figured out exactly where yet.  


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152380/new/

https://reviews.llvm.org/D152380