[PATCH] D152380: [WIP][RISCV] Canonicalize towards vmerge w/passthrough representation

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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This is the first patch in a series to change how we represent tail agnostic, tail undefined, and tail undisturbed operations.  In current code, we tend to use an unsuffixed pseudo for undefined (despite calling it TA most places in code), and the _TU form for both agnostic and undisturbed (via the policy operand).

The key observation behind this patch is that we can represent tail undefined via a pseudo with a passthrough operand if that operand is IMPLICIT_DEF (aka undef).  We already have a few instances of this in tree - see vmv.s.x and vslide* - but we can do this more universally.  Once complete, we will be able to delete roughly 1/2 of our vector pseudo classes.

This patch doesn't actually remove the legacy unsuffixed pseudo as there's still some path from intrinsic lowering which uses it.  (I have not yet located it.)  This also means we don't have to modify any of the lookup tables which makes the migration simpler.  We can defer deleting the tables and pseudos until one final change once all the instructions have been migrated.

This patch is WIP, and will likely be split before landed.  I'll comment on the review to tag the open items.  I'm posting now for discussion.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D152380

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-i1.ll
  llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
  llvm/test/CodeGen/RISCV/rvv/insertelt-i1.ll
  llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll
  llvm/test/CodeGen/RISCV/rvv/vector-splice.ll

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