[PATCH] D152380: [WIP][RISCV] Canonicalize towards vmerge w/passthrough representation

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/vector-splice.ll:12
 ; CHECK:       # %bb.0:
+; CHECK-NEXT:    vmv1r.v v9, v0
 ; CHECK-NEXT:    vsetvli a0, zero, e8, mf8, ta, ma
----------------
reames wrote:
> Note - This change (and others like it) look concerning.  I dug far enough in to this to be fairly sure this is a problem with pre-RA-sched, but haven't yet fully isolated the cause.  I suspect there's some missing special casing for IMPLICIT_DEF somewhere, but I haven't figured out exactly where yet.  
For the one case I looked at, it looks like we're getting different ordering out of the SelectionDAG list scheduler when we convert to MIR. Mostly that sceduler uses IROrder from the debug location. If the IR order of nodes is the same, which will occur if something was expanded into multiple SelectionDAG nodes, the list scheduler starts examining other things to break the tie.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152380/new/

https://reviews.llvm.org/D152380