[PATCH] D152222: [RISCV] Don't fold RISCVISD::VMV_V_X_VL series node and scalar load to vector load when scalar load is update load

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead added a comment.

In D152222#4397976 <https://reviews.llvm.org/D152222#4397976>, @zixuan-wu wrote:

> In D152222#4397974 <https://reviews.llvm.org/D152222#4397974>, @craig.topper wrote:
>
>> When does a load and update node occur on RISC-v?
>
> It's actually less frequent because the standard extension does not have load update instruction. But XTHeadFMemIdx extension has load update instruction, so it appears in downstream.

`XTHeadFMemIdx` has been upstreamed so I think we may provide a



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Comment at: llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll:11
+; RV32-NEXT:  .LBB0_1: # %for.body4
+; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV32-NEXT:    j .LBB0_1
----------------
Why is there no instructions here? All of them are optimized out?


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  https://reviews.llvm.org/D152222/new/

https://reviews.llvm.org/D152222