[PATCH] D152222: [RISCV] Don't fold RISCVISD::VMV_V_X_VL series node and scalar load to vector load when scalar load is update load

[Zixuan Wu via Phabricator via llvm-commits]

zixuan-wu added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll:11
+; RV32-NEXT:  .LBB0_1: # %for.body4
+; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV32-NEXT:    j .LBB0_1
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pcwang-thead wrote:
> Why is there no instructions here? All of them are optimized out?
it's interesting. It's removed by dead-mi-elimination pass. But this is truly a case reduced from big original source to reproduce the compiling assert in DAG selection stage :)


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152222/new/

https://reviews.llvm.org/D152222