[PATCH] D152222: [RISCV] Don't fold RISCVISD::VMV_V_X_VL series node and scalar load to vector load when scalar load is update load

[Zixuan Wu via Phabricator via llvm-commits]

zixuan-wu updated this revision to Diff 528738.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D152222/new/

https://reviews.llvm.org/D152222

Files:
  llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
  llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll


Index: llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/rvv/fold-scalar-load-crash.ll
@@ -0,0 +1,44 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -mtriple=riscv32 -mattr=+v,+xtheadmemidx -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix RV32
+; RUN: llc -mtriple=riscv64 -mattr=+v,+xtheadmemidx -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s --check-prefix RV64
+
+define i32 @test(i32 %x_size, ptr %add.ptr12) {
+; RV32-LABEL: test:
+; RV32:       # %bb.0: # %entry
+; RV32-NEXT:  .LBB0_1: # %for.body4
+; RV32-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV32-NEXT:    j .LBB0_1
+;
+; RV64-LABEL: test:
+; RV64:       # %bb.0: # %entry
+; RV64-NEXT:  .LBB0_1: # %for.body4
+; RV64-NEXT:    # =>This Inner Loop Header: Depth=1
+; RV64-NEXT:    j .LBB0_1
+entry:
+  %const = bitcast i64 1 to i64
+  br label %for.body4
+
+for.body4:                                        ; preds = %for.body4.backedge, %entry
+  %add.ptr13 = getelementptr i8, ptr %add.ptr12, i32 -1
+  %add.ptr27 = getelementptr i8, ptr %add.ptr13, i32 %x_size
+  %0 = load i8, ptr %add.ptr13, align 1
+  %1 = load i8, ptr %add.ptr27, align 1
+  %2 = insertelement <8 x i8> poison, i8 %0, i64 0
+  %3 = insertelement <8 x i8> %2, i8 0, i64 %const
+  %4 = insertelement <8 x i8> zeroinitializer, i8 0, i64 %const
+  %5 = insertelement <8 x i8> %3, i8 %1, i64 0
+  %6 = icmp ult <8 x i8> %5, <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
+  %7 = bitcast <8 x i1> %6 to i8
+  %8 = zext i8 %7 to i32
+  %cond = icmp eq i32 %8, 0
+  br i1 %cond, label %if.then381, label %for.body4.backedge
+
+for.body4.backedge:                               ; preds = %for.body4, %if.then381
+  br label %for.body4
+
+if.then381:                                       ; preds = %for.body4
+  %sub382 = add i32 0, 0
+  br label %for.body4.backedge
+}
Index: llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -2067,7 +2067,9 @@
       break;
     SDValue Src = Node->getOperand(1);
     auto *Ld = dyn_cast<LoadSDNode>(Src);
-    if (!Ld)
+    // Can't fold load update node because the second
+    // output is used so that load update node can't be removed.
+    if (!Ld || Ld->isIndexed())
       break;
     EVT MemVT = Ld->getMemoryVT();
     // The memory VT should be the same size as the element type.


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D152222.528738.patch
Type: text/x-patch
Size: 2693 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230606/c47f0d73/attachment.bin>