[PATCH] D152222: [RISCV] Don't fold RISCVISD::VMV_V_X_VL series node and scalar load to vector load when scalar load is update load

[Zixuan Wu via Phabricator via llvm-commits]

zixuan-wu added a comment.

In D152222#4398334 <https://reviews.llvm.org/D152222#4398334>, @craig.topper wrote:

> HasVendorXTHeadFMemIdx is in upstream, so we should be able to write a test for this?

Theoretically, it can construct one case with XTHeadFMemIdx extension, but it only appears in downstream codebase. I am trying to reproduce it without downstream code.


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https://reviews.llvm.org/D152222