[PATCH] D151449: [RISCV] Add DAG combine for CTTZ in the case of input 0

[Djordje Todorovic via Phabricator via llvm-commits]

djtodoro marked 8 inline comments as done.
djtodoro added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11444
+      CTTZ.getOpcode() != ISD::CTTZ_ZERO_UNDEF &&
+      CTTZ.getOpcode() != RISCVISD::CTZW)
+    return SDValue();
----------------
craig.topper wrote:
> Do your tests cover the CTZW case? That node doesn't exist until after type legalization, but I suspect all your tests match before type legalization.
Hm, you are right, I m removing it for now.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11482
+
+  if (AndNode.getValueType() == llvm::MVT::i64 ||
+      N->getValueType(0) == llvm::MVT::i32) {
----------------
craig.topper wrote:
> You can use getZExtOrTrunc here to simplify this.
Oh yes, thanks!


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151449/new/

https://reviews.llvm.org/D151449