[PATCH] D151449: [RISCV] Add DAG combine for CTTZ in the case of input 0

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:11444
+      CTTZ.getOpcode() != ISD::CTTZ_ZERO_UNDEF &&
+      CTTZ.getOpcode() != RISCVISD::CTZW)
+    return SDValue();
----------------
Do your tests cover the CTZW case? That node doesn't exist until after type legalization, but I suspect all your tests match before type legalization.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151449/new/

https://reviews.llvm.org/D151449