[PATCH] D150969: [AArch64] Try to convert two XTN and two SMLSL to UZP1, SMLSL and SMLSL2

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 updated this revision to Diff 527416.
jaykang10 added a comment.

Based on the `uzp1` from dagcombine, if `uzp1` has `IMPLICIT_DEF` as low 64-bit operand, we can replace it with `xtn`'s operand.
For example,

  %4:fpr128 = LDRQui %3:gpr64common, 0 :: (load (s128) from %ir.3, align 4)
  %5:fpr64 = XTNv4i16 killed %4:fpr128
  %6:fpr64 = COPY %0.dsub:fpr128
  %7:fpr128 = LDRQui %3:gpr64common, 1 :: (load (s128) from %ir.7, align 4)
  %9:fpr128 = IMPLICIT_DEF
  %8:fpr128 = UZP1v8i16 killed %9:fpr128, killed %7:fpr128
  %10:fpr128 = SMLSLv4i16_v4i32 %1:fpr128(tied-def 0), killed %6:fpr64, killed %5:fpr64
  %11:fpr128 = SMLSLv8i16_v4i32 %10:fpr128(tied-def 0), %0:fpr128, killed %8:fpr128
  ==>
  %4:fpr128 = LDRQui %3:gpr64common, 0 :: (load (s128) from %ir.3, align 4)
  %6:fpr64 = COPY %0.dsub:fpr128
  %7:fpr128 = LDRQui %3:gpr64common, 1 :: (load (s128) from %ir.7, align 4)
  %8:fpr128 = UZP1v8i16 killed %4:fpr128, killed %7:fpr128 
  %12:fpr64 = COPY %8.dsub:fpr128
  %10:fpr128 = SMLSLv4i16_v4i32 %1:fpr128(tied-def 0), killed %6:fpr64, killed %12:fpr64 
  %11:fpr128 = SMLSLv8i16_v4i32 %10:fpr128(tied-def 0), %0:fpr128, killed %8:fpr128


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D150969/new/

https://reviews.llvm.org/D150969

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
  llvm/test/CodeGen/AArch64/aarch64-smull.ll
  llvm/test/CodeGen/AArch64/zext-to-tbl.ll

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