[PATCH] D151823: [RISCV] Combine vmv.s.x (vslideup pt, v, 1, <all-ones>, vl), scalar, vl to vslide1up
Luke Lau via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 31 17:36:03 PDT 2023
luke added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:12480
+ VL != Slide->getOperand(4) || !isNonZeroAVL(VL))
+ return SDValue();
+
----------------
It's not documented in `RISCVISelLowering.h` but I believe `RISCVISD::VSLIDEUP_VL` takes a policy operand (for both the mask and tail). It doesn't look like `RISCVISD::VSLIDE1UP_VL` has it though, so I'm not sure what policy it uses.
Either way do we need to check the vslideup's policy here?
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:12482
+
+ if (Slide->getValueType(0).getVectorElementType().getSizeInBits() !=
+ VT.getVectorElementType().getSizeInBits())
----------------
Nit, could possibly use `Slide.getScalarValueSizeInBits() != VT.getScalarSizeInBits()`
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D151823/new/
https://reviews.llvm.org/D151823
More information about the llvm-commits
mailing list