[PATCH] D151823: [RISCV] Combine vmv.s.x (vslideup pt, v, 1, <all-ones>, vl), scalar, vl to vslide1up

[Philip Reames via Phabricator via llvm-commits]

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This covers the case where we insert a scalar into lane 0 of a vector after performing the slideup.  This was triggered by offline discussion about D151736 <https://reviews.llvm.org/D151736>, and is an alternative to that approach.  I think this is cleaner and a potentially more general.

A couple things we have to be careful of:

- The type sizes need to match.  We implicitly truncate the scalar, and the shift is in SEW units.
- We need to avoid VL=0 and a mask with lane-0 disabled.  The former is just tricky to reason about, the later differs in behavior between the two forms.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151823

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vector-shuffle-vslide1up.ll

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