[PATCH] D151358: [LegalizeTypes] Improve expansion of wide SMIN/SMAX/UMIN/UMAX

Eli Friedman via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 24 13:06:29 PDT 2023

efriedma added inline comments.

Comment at: llvm/test/CodeGen/RISCV/fpclamptosat.ll:1953
+; RV32IF-NEXT:    xori a1, a1, 1
+; RV32IF-NEXT:    beqz a1, .LBB27_8
+; RV32IF-NEXT:    j .LBB27_9
craig.topper wrote:
> I wonder why this slti+xori+beqz didn't simplify.
The sequence doesn't actually exist in this form until very late, in block-placement.  In SelectionDAG, we just have a RISCVISD::SELECT_CC used as the condition of another RISCVISD::SELECT_CC , which obscures the sequence.  (For similar reasons, we have sltu+bnez instead of bltu.)

Not sure what the best solution looks like.  I guess for 64-bit compares in particular, you could define a pseudo-instruction SELECTCC_64BIT or something like that.  Maybe more generally, it would help if we transform `select(select(a,b,c),d,e)` to `select(a, select(b,d,e), select(c,d,e))`.

  rG LLVM Github Monorepo



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