[PATCH] D151212: [RISCV][InsertVSETVLI] Support constant VLs larger than immediate encoding

Wed May 24 10:09:54 PDT 2023

craig.topper accepted this revision.
craig.topper added a comment.
This revision is now accepted and ready to land.

LGTM

================
Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll:12509
 ; RV64ZVE32F-NEXT:    lbu a2, 0(a2)
 ; RV64ZVE32F-NEXT:    li a3, 32
 ; RV64ZVE32F-NEXT:    vmv.s.x v12, a2
----------------
reames wrote:
> craig.topper wrote:
> > Is this instruction dead? Do we need to try to delete these `li` instructions or run DCE after vsetvli?
> It looks like it yes.  We already kill other vsetvlis with register VLs, so it's possible we can already see this elsewhere.  Note sure about that to be honest; I can't quickly come up with a test case where we would.  
> 
> If you okay with it, I'd like to address this in a following patch.  
We can address it as a follow up.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151212/new/

https://reviews.llvm.org/D151212