[PATCH] D151212: [RISCV][InsertVSETVLI] Support constant VLs larger than immediate encoding

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll:12509
 ; RV64ZVE32F-NEXT:    lbu a2, 0(a2)
 ; RV64ZVE32F-NEXT:    li a3, 32
 ; RV64ZVE32F-NEXT:    vmv.s.x v12, a2
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craig.topper wrote:
> Is this instruction dead? Do we need to try to delete these `li` instructions or run DCE after vsetvli?
It looks like it yes.  We already kill other vsetvlis with register VLs, so it's possible we can already see this elsewhere.  Note sure about that to be honest; I can't quickly come up with a test case where we would.  

If you okay with it, I'd like to address this in a following patch.  


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D151212/new/

https://reviews.llvm.org/D151212