[PATCH] D151221: [RISCV] Scalarize constant stores of fixed vectors up to 32 bits

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll:134-142
+; RV32-NEXT:    lui a4, 1040368
+; RV32-NEXT:    addi a4, a4, -256
+; RV32-NEXT:    sw a4, 0(a0)
+; RV32-NEXT:    sw a4, 0(a1)
+; RV32-NEXT:    lui a0, 1040352
+; RV32-NEXT:    sw a0, 0(a2)
+; RV32-NEXT:    lui a0, 1036288
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I'm wondering if we should detect constants that are sequences (`BuildVectorSDNode::isConstantSequence`) to prevent this.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D151221/new/

https://reviews.llvm.org/D151221