[PATCH] D151221: [RISCV] Scalarize constant stores of fixed vectors up to 32 bits

[Luke Lau via Phabricator via llvm-commits]

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For stores of small fixed-length vector constants, we can store them
with a sequence of lui/addi/sh/sw to avoid the cost of building the
vector and the vsetivli toggle.

Note that this only handles vectors that are 32 bits or smaller, but
could be expanded to 64 bits if we know that the constant
materialization cost isn't too high.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151221

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-store.ll

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