[PATCH] D151182: [LegalizeTypes][ARM][AArch6][RISCV][VE][WebAssembly] Add special case for smin(X, -1) and smax(X, 0) to ExpandIntRes_MINMAX.

[Craig Topper via Phabricator via llvm-commits]

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We can compute a simpler expression for Lo for these cases. This
is an alternative for the test cases in D151180 <https://reviews.llvm.org/D151180> that works for
more targets.

I view this as similar to some of the special cases we
have for expanding setcc operands.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D151182

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  llvm/test/CodeGen/AArch64/fpclamptosat.ll
  llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
  llvm/test/CodeGen/ARM/fpclamptosat.ll
  llvm/test/CodeGen/ARM/fpclamptosat_vec.ll
  llvm/test/CodeGen/RISCV/fpclamptosat.ll
  llvm/test/CodeGen/RISCV/min-max.ll
  llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
  llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
  llvm/test/CodeGen/VE/Scalar/smax.ll
  llvm/test/CodeGen/WebAssembly/fpclamptosat.ll
  llvm/test/CodeGen/WebAssembly/fpclamptosat_vec.ll

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